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Add FPGA Altera Cyclone 2 support
[people/ms/u-boot.git] / cpu / ppc4xx / 405gp_pci.c
CommitLineData
c609719b
WD		 1/*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21/*----------------------------------------------------------------------------+
22 *
23 * File Name: 405gp_pci.c
24 *
25 * Function: Initialization code for the 405GP PCI Configuration regs.
26 *
27 * Author: Mark Game
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 09-Sep-98 Created MCG
34 * 02-Nov-98 Removed External arbiter selected message JWB
35 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
36 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
37 * from (0 to n) to (1 to n).
38 * 17-May-99 Port to Walnut JWB
39 * 17-Jun-99 Updated for VGA support JWB
40 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
41 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
42 * target latency timer values are not supported).
43 * Should be fixed in pass 2.
44 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
45 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
46 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
47 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
48 * really required after a reset since PMMxMAs are already
49 * disabled but is a good practice nonetheless. JWB
50 * 12-Jun-01 stefan.roese@esd-electronics.com
51 * - PCI host/adapter handling reworked
52 * 09-Jul-01 stefan.roese@esd-electronics.com
53 * - PCI host now configures from device 0 (not 1) to max_dev,
54 * (host configures itself)
55 * - On CPCI-405 pci base address and size is generated from
56 * SDRAM and FLASH size (CFG regs not used anymore)
57 * - Some minor changes for CPCI-405-A (adapter version)
58 * 14-Sep-01 stefan.roese@esd-electronics.com
59 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
60 * 28-Sep-01 stefan.roese@esd-electronics.com
61 * - Changed pci master configuration for linux compatibility
62 * (no need for bios_fixup() anymore)
63 * 26-Feb-02 stefan.roese@esd-electronics.com
64 * - Bug fixed in pci configuration (Andrew May)
65 * - Removed pci class code init for CPCI405 board
66 * 15-May-02 stefan.roese@esd-electronics.com
67 * - New vga device handling
68 * 29-May-02 stefan.roese@esd-electronics.com
69 * - PCI class code init added (if defined)
70 *----------------------------------------------------------------------------*/
71
72#include <common.h>
73#include <command.h>
c609719b
WD		 74#if !defined(CONFIG_440)
75#include <405gp_pci.h>
76#endif
77#include <asm/processor.h>
78#include <pci.h>
79
d87080b7
WD		 80DECLARE_GLOBAL_DATA_PTR;
81
b867d705 82#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
c609719b
WD		 83
84#ifdef CONFIG_PCI
85
2076d0a1
SR		 86#if defined(CONFIG_PMC405)
87ushort pmc405_pci_subsys_deviceid(void);
88#endif
89
c609719b
WD		 90/*#define DEBUG*/
91
92/*-----------------------------------------------------------------------------+
93 * pci_init. Initializes the 405GP PCI Configuration regs.
94 *-----------------------------------------------------------------------------*/
95void pci_405gp_init(struct pci_controller *hose)
96{
c609719b
WD		 97 int i, reg_num = 0;
98 bd_t *bd = gd->bd;
99
100 unsigned short temp_short;
101 unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
5e746fce 102#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
fddae7b8 103 char *ptmla_str, *ptmms_str;
2076d0a1 104#endif
c609719b
WD		 105 unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
106 unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
c609719b
WD		 107#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
108 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
109 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
110 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
111 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
112#else
113 unsigned long pmmla[3] = {0x80000000, 0,0};
114 unsigned long pmmma[3] = {0xC0000001, 0,0};
115 unsigned long pmmpcila[3] = {0x80000000, 0,0};
116 unsigned long pmmpciha[3] = {0x00000000, 0,0};
5e746fce
SR		 117#endif
118#ifdef CONFIG_PCI_PNP
119#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
120 char *s;
121#endif
c609719b
WD		 122#endif
123
fddae7b8
SR		 124#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
125 ptmla_str = getenv("ptm1la");
126 ptmms_str = getenv("ptm1ms");
127 if(NULL != ptmla_str && NULL != ptmms_str ) {
128 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
129 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
130 }
131
132 ptmla_str = getenv("ptm2la");
133 ptmms_str = getenv("ptm2ms");
134 if(NULL != ptmla_str && NULL != ptmms_str ) {
135 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
136 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
137 }
138#endif
139
c609719b
WD		 140 /*
141 * Register the hose
142 */
143 hose->first_busno = 0;
144 hose->last_busno = 0xff;
145
146 /* ISA/PCI I/O space */
147 pci_set_region(hose->regions + reg_num++,
148 MIN_PCI_PCI_IOADDR,
149 MIN_PLB_PCI_IOADDR,
150 0x10000,
151 PCI_REGION_IO);
152
153 /* PCI I/O space */
154 pci_set_region(hose->regions + reg_num++,
155 0x00800000,
156 0xe8800000,
157 0x03800000,
158 PCI_REGION_IO);
159
160 reg_num = 2;
161
162 /* Memory spaces */
163 for (i=0; i<2; i++)
164 if (ptmms[i] & 1)
165 {
166 if (!i) hose->pci_fb = hose->regions + reg_num;
167
168 pci_set_region(hose->regions + reg_num++,
169 ptmpcila[i], ptmla[i],
170 ~(ptmms[i] & 0xfffff000) + 1,
171 PCI_REGION_MEM |
172 PCI_REGION_MEMORY);
173 }
174
175 /* PCI memory spaces */
176 for (i=0; i<3; i++)
177 if (pmmma[i] & 1)
178 {
179 pci_set_region(hose->regions + reg_num++,
180 pmmpcila[i], pmmla[i],
181 ~(pmmma[i] & 0xfffff000) + 1,
182 PCI_REGION_MEM);
183 }
184
185 hose->region_count = reg_num;
186
187 pci_setup_indirect(hose,
188 PCICFGADR,
189 PCICFGDATA);
190
191 if (hose->pci_fb)
192 pciauto_region_init(hose->pci_fb);
193
194 pci_register_hose(hose);
195
196 /*--------------------------------------------------------------------------+
197 * 405GP PCI Master configuration.
198 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
199 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
200 * Use byte reversed out routines to handle endianess.
201 *--------------------------------------------------------------------------*/
f3e0de60 202 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
c609719b
WD		 203 out32r(PMM0LA, pmmla[0]);
204 out32r(PMM0PCILA, pmmpcila[0]);
205 out32r(PMM0PCIHA, pmmpciha[0]);
206 out32r(PMM0MA, pmmma[0]);
207
208 /*--------------------------------------------------------------------------+
209 * PMM1 is not used. Initialize them to zero.
210 *--------------------------------------------------------------------------*/
f3e0de60 211 out32r(PMM1MA, (pmmma[1]&~0x1));
c609719b
WD		 212 out32r(PMM1LA, pmmla[1]);
213 out32r(PMM1PCILA, pmmpcila[1]);
214 out32r(PMM1PCIHA, pmmpciha[1]);
215 out32r(PMM1MA, pmmma[1]);
216
217 /*--------------------------------------------------------------------------+
218 * PMM2 is not used. Initialize them to zero.
219 *--------------------------------------------------------------------------*/
8bde7f77 220 out32r(PMM2MA, (pmmma[2]&~0x1));
c609719b
WD		 221 out32r(PMM2LA, pmmla[2]);
222 out32r(PMM2PCILA, pmmpcila[2]);
223 out32r(PMM2PCIHA, pmmpciha[2]);
224 out32r(PMM2MA, pmmma[2]);
225
226 /*--------------------------------------------------------------------------+
227 * 405GP PCI Target configuration. (PTM1)
228 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
229 *--------------------------------------------------------------------------*/
230 out32r(PTM1LA, ptmla[0]); /* insert address */
231 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
4654af27 232 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
c609719b
WD		 233
234 /*--------------------------------------------------------------------------+
235 * 405GP PCI Target configuration. (PTM2)
236 *--------------------------------------------------------------------------*/
237 out32r(PTM2LA, ptmla[1]); /* insert address */
4654af27
WD		 238 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
239
c609719b
WD		 240 if (ptmms[1] == 0)
241 {
242 out32r(PTM2MS, 0x00000001); /* set enable bit */
243 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
244 out32r(PTM2MS, 0x00000000); /* disable */
245 }
246 else
247 {
248 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
249 }
250
251 /*
252 * Insert Subsystem Vendor and Device ID
253 */
254 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
255#ifdef CONFIG_CPCI405
256 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
257 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
258 else
259 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
260#else
261 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
262#endif
263
264 /*
265 * Insert Class-code
266 */
267#ifdef CFG_PCI_CLASSCODE
268 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
269#endif /* CFG_PCI_CLASSCODE */
270
271 /*--------------------------------------------------------------------------+
272 * If PCI speed = 66Mhz, set 66Mhz capable bit.
273 *--------------------------------------------------------------------------*/
274 if (bd->bi_pci_busfreq >= 66000000) {
275 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
276 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
277 }
278
279#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
4654af27 280#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
5e746fce
SR		 281 if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
282 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
c609719b
WD		 283#endif
284 {
285 /*--------------------------------------------------------------------------+
286 * Write the 405GP PCI Configuration regs.
287 * Enable 405GP to be a master on the PCI bus (PMM).
288 * Enable 405GP to act as a PCI memory target (PTM).
289 *--------------------------------------------------------------------------*/
290 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
291 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
292 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
293 }
294#endif
295
428c5639
SR		 296#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
297 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
298#endif
299
c609719b
WD		 300 /*
301 * Set HCE bit (Host Configuration Enabled)
302 */
303 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
304 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
305
306#ifdef CONFIG_PCI_PNP
307 /*--------------------------------------------------------------------------+
308 * Scan the PCI bus and configure devices found.
309 *--------------------------------------------------------------------------*/
310#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
5e746fce
SR		 311 if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
312 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
c609719b
WD		 313#endif
314 {
315#ifdef CONFIG_PCI_SCAN_SHOW
316 printf("PCI: Bus Dev VenId DevId Class Int\n");
317#endif
c609719b
WD		 318 hose->last_busno = pci_hose_scan(hose);
319 }
320#endif /* CONFIG_PCI_PNP */
321
322}
323
324/*
325 * drivers/pci.c skips every host bridge but the 405GP since it could
326 * be set as an Adapter.
327 *
328 * I (Andrew May) don't know what we should do here, but I don't want
329 * the auto setup of a PCI device disabling what is done pci_405gp_init
330 * as has happened before.
331 */
332void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
333 struct pci_config_table *entry)
334{
335#ifdef DEBUG
8bde7f77 336 printf("405gp_setup_bridge\n");
c609719b
WD		 337#endif
338}
339
340/*
341 *
342 */
343
344void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
345{
346 unsigned char int_line = 0xff;
347
348 /*
349 * Write pci interrupt line register (cpci405 specific)
350 */
351 switch (PCI_DEV(dev) & 0x03)
352 {
353 case 0:
354 int_line = 27 + 2;
355 break;
356 case 1:
357 int_line = 27 + 3;
358 break;
359 case 2:
360 int_line = 27 + 0;
361 break;
362 case 3:
363 int_line = 27 + 1;
364 break;
365 }
366
367 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
368}
369
370void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
371 struct pci_config_table *entry)
372{
373 unsigned int cmdstat = 0;
374
f3fecfe6 375 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b
WD		 376
377 /* always enable io space on vga boards */
378 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
379 cmdstat |= PCI_COMMAND_IO;
380 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
381}
382
383#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
384
385/*
386 *As is these functs get called out of flash Not a horrible
387 *thing, but something to keep in mind. (no statics?)
388 */
389static struct pci_config_table pci_405gp_config_table[] = {
390/*if VendID is 0 it terminates the table search (ie Walnut)*/
42dfe7a1 391#ifdef CFG_PCI_SUBSYS_VENDORID
c609719b
WD		 392 {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
393 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
394#endif
395 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
396 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
397
398 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
399 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
400
401 { }
402};
403
404static struct pci_controller hose = {
405 fixup_irq: pci_405gp_fixup_irq,
406 config_table: pci_405gp_config_table,
407};
408
ad10dd9a 409void pci_init_board(void)
c609719b
WD		 410{
411 /*we want the ptrs to RAM not flash (ie don't use init list)*/
412 hose.fixup_irq = pci_405gp_fixup_irq;
413 hose.config_table = pci_405gp_config_table;
414 pci_405gp_init(&hose);
415}
416
417#endif
418
419#endif /* CONFIG_PCI */
420
421#endif /* CONFIG_405GP */
422
423/*-----------------------------------------------------------------------------+
424 * CONFIG_440
425 *-----------------------------------------------------------------------------*/
426#if defined(CONFIG_440) && defined(CONFIG_PCI)
427
428static struct pci_controller ppc440_hose = {0};
429
430
431void pci_440_init (struct pci_controller *hose)
432{
433 int reg_num = 0;
c609719b 434
5568e613 435#ifndef CONFIG_DISABLE_PISE_TEST
c609719b
WD		 436 /*--------------------------------------------------------------------------+
437 * The PCI initialization sequence enable bit must be set ... if not abort
3c74e32a 438 * pci setup since updating the bit requires chip reset.
c609719b 439 *--------------------------------------------------------------------------*/
6c5879f3 440#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
5568e613
SR		 441 unsigned long strap;
442
3c74e32a 443 mfsdr(sdr_sdstp1,strap);
6e7fb6ea 444 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
3c74e32a
WD		 445 printf("PCI: SDR0_STRP1[PISE] not set.\n");
446 printf("PCI: Configuration aborted.\n");
447 return;
448 }
5568e613
SR		 449#elif defined(CONFIG_440GP)
450 unsigned long strap;
451
3c74e32a 452 strap = mfdcr(cpc0_strp1);
6e7fb6ea 453 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
3c74e32a
WD		 454 printf("PCI: CPC0_STRP1[PISE] not set.\n");
455 printf("PCI: Configuration aborted.\n");
456 return;
457 }
458#endif
5568e613
SR		 459#endif /* CONFIG_DISABLE_PISE_TEST */
460
c609719b
WD		 461 /*--------------------------------------------------------------------------+
462 * PCI controller init
463 *--------------------------------------------------------------------------*/
464 hose->first_busno = 0;
465 hose->last_busno = 0xff;
466
fbb0b559 467 /* PCI I/O space */
c609719b
WD		 468 pci_set_region(hose->regions + reg_num++,
469 0x00000000,
6e7fb6ea
SR		 470 PCIX0_IOBASE,
471 0x10000,
472 PCI_REGION_IO);
c609719b 473
fbb0b559 474 /* PCI memory space */
c609719b
WD		 475 pci_set_region(hose->regions + reg_num++,
476 CFG_PCI_TARGBASE,
6e7fb6ea
SR		 477 CFG_PCI_MEMBASE,
478 0x10000000,
479 PCI_REGION_MEM );
fbb0b559
MB		 480
481#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
482 defined(CONFIG_PCI_SYS_MEM_SIZE)
483 /* System memory space */
484 pci_set_region(hose->regions + reg_num++,
485 CONFIG_PCI_SYS_MEM_BUS,
486 CONFIG_PCI_SYS_MEM_PHYS,
487 CONFIG_PCI_SYS_MEM_SIZE,
488 PCI_REGION_MEM | PCI_REGION_MEMORY );
489#endif
490
c609719b
WD		 491 hose->region_count = reg_num;
492
493 pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
494
495#if defined(CFG_PCI_PRE_INIT)
6e7fb6ea
SR		 496 /* Let board change/modify hose & do initial checks */
497 if (pci_pre_init (hose) == 0) {
498 printf("PCI: Board-specific initialization failed.\n");
499 printf("PCI: Configuration aborted.\n");
500 return;
501 }
c609719b
WD		 502#endif
503
504 pci_register_hose( hose );
505
506 /*--------------------------------------------------------------------------+
507 * PCI target init
508 *--------------------------------------------------------------------------*/
509#if defined(CFG_PCI_TARGET_INIT)
510 pci_target_init(hose); /* Let board setup pci target */
511#else
6e7fb6ea
SR		 512 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
513 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
514 out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
c609719b
WD		 515#endif
516
6c5879f3 517#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
3c74e32a
WD		 518 out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
519 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
c157d8e2 520#elif defined(PCIX0_BRDGOPT1)
3c74e32a
WD		 521 out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
522 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
523#endif
c609719b
WD		 524
525 /*--------------------------------------------------------------------------+
526 * PCI master init: default is one 256MB region for PCI memory:
527 * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE
528 *--------------------------------------------------------------------------*/
529#if defined(CFG_PCI_MASTER_INIT)
530 pci_master_init(hose); /* Let board setup pci master */
531#else
532 out32r( PCIX0_POM0SA, 0 ); /* disable */
533 out32r( PCIX0_POM1SA, 0 ); /* disable */
534 out32r( PCIX0_POM2SA, 0 ); /* disable */
6c5879f3
MB		 535#if defined(CONFIG_440SPE)
536 out32r( PCIX0_POM0LAL, 0x10000000 );
537 out32r( PCIX0_POM0LAH, 0x0000000c );
538#else
c609719b
WD		 539 out32r( PCIX0_POM0LAL, 0x00000000 );
540 out32r( PCIX0_POM0LAH, 0x00000003 );
6c5879f3 541#endif
c609719b
WD		 542 out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
543 out32r( PCIX0_POM0PCIAH, 0x00000000 );
544 out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
6e7fb6ea 545 out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
c609719b
WD		 546#endif
547
548 /*--------------------------------------------------------------------------+
549 * PCI host configuration -- we don't make any assumptions here ... the
6e7fb6ea
SR		 550 * _board_must_indicate_ what to do -- there's just too many runtime
551 * scenarios in environments like cPCI, PPMC, etc. to make a determination
552 * based on hard-coded values or state of arbiter enable.
c609719b 553 *--------------------------------------------------------------------------*/
6e7fb6ea 554 if (is_pci_host(hose)) {
c609719b 555#ifdef CONFIG_PCI_SCAN_SHOW
6e7fb6ea 556 printf("PCI: Bus Dev VenId DevId Class Int\n");
c609719b 557#endif
846b0dd2 558#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
6e7fb6ea 559 out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
c157d8e2 560#endif
6e7fb6ea
SR		 561 hose->last_busno = pci_hose_scan(hose);
562 }
c609719b
WD		 563}
564
ad10dd9a 565void pci_init_board(void)
c609719b
WD		 566{
567 pci_440_init (&ppc440_hose);
692519b1
RJ		 568#if defined(CONFIG_440SPE)
569 pcie_setup_hoses();
570#endif
c609719b
WD		 571}
572
573#endif /* CONFIG_440 & CONFIG_PCI */
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