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Commit | Line | Data |
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fe8c2806 | 1 | /* |
36d830c9 SR |
2 | * cpu/ppc4xx/44x_spd_ddr.c |
3 | * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a | |
4 | * DDR controller. Those are 440GP/GX/EP/GR. | |
5 | * | |
fe8c2806 WD |
6 | * (C) Copyright 2001 |
7 | * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com | |
8 | * | |
9 | * Based on code by: | |
10 | * | |
db2f721f WD |
11 | * Kenneth Johansson ,Ericsson AB. |
12 | * kenneth.johansson@etx.ericsson.se | |
fe8c2806 WD |
13 | * |
14 | * hacked up by bill hunter. fixed so we could run before | |
15 | * serial_init and console_init. previous version avoided this by | |
16 | * running out of cache memory during serial/console init, then running | |
17 | * this code later. | |
18 | * | |
19 | * (C) Copyright 2002 | |
20 | * Jun Gu, Artesyn Technology, jung@artesyncp.com | |
0c8721a4 | 21 | * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. |
fe8c2806 | 22 | * |
d2d43276 | 23 | * (C) Copyright 2005-2007 |
c157d8e2 SR |
24 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
25 | * | |
fe8c2806 WD |
26 | * See file CREDITS for list of people who contributed to this |
27 | * project. | |
28 | * | |
29 | * This program is free software; you can redistribute it and/or | |
30 | * modify it under the terms of the GNU General Public License as | |
31 | * published by the Free Software Foundation; either version 2 of | |
32 | * the License, or (at your option) any later version. | |
33 | * | |
34 | * This program is distributed in the hope that it will be useful, | |
35 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
36 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
37 | * GNU General Public License for more details. | |
38 | * | |
39 | * You should have received a copy of the GNU General Public License | |
40 | * along with this program; if not, write to the Free Software | |
41 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
42 | * MA 02111-1307 USA | |
43 | */ | |
44 | ||
d2d43276 SR |
45 | /* define DEBUG for debugging output (obviously ;-)) */ |
46 | #if 0 | |
47 | #define DEBUG | |
48 | #endif | |
49 | ||
fe8c2806 WD |
50 | #include <common.h> |
51 | #include <asm/processor.h> | |
52 | #include <i2c.h> | |
53 | #include <ppc4xx.h> | |
e2ebe696 | 54 | #include <asm/mmu.h> |
fe8c2806 | 55 | |
36d830c9 SR |
56 | #if defined(CONFIG_SPD_EEPROM) && \ |
57 | (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ | |
58 | defined(CONFIG_440EP) || defined(CONFIG_440GR)) | |
fe8c2806 WD |
59 | |
60 | /* | |
61 | * Set default values | |
62 | */ | |
f013dacf WD |
63 | #ifndef CFG_I2C_SPEED |
64 | #define CFG_I2C_SPEED 50000 | |
fe8c2806 WD |
65 | #endif |
66 | ||
f013dacf WD |
67 | #ifndef CFG_I2C_SLAVE |
68 | #define CFG_I2C_SLAVE 0xFE | |
fe8c2806 WD |
69 | #endif |
70 | ||
f013dacf | 71 | #define ONE_BILLION 1000000000 |
c157d8e2 | 72 | |
a5d71e29 HS |
73 | /* |
74 | * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed | |
75 | */ | |
76 | void __spd_ddr_init_hang (void) | |
77 | { | |
78 | hang (); | |
79 | } | |
80 | void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); | |
566a494f | 81 | |
fe8c2806 | 82 | /*----------------------------------------------------------------------------- |
c157d8e2 SR |
83 | | Memory Controller Options 0 |
84 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
85 | #define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ |
86 | #define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ | |
87 | #define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ | |
88 | #define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ | |
89 | #define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ | |
90 | #define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ | |
91 | #define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ | |
92 | #define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ | |
93 | #define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ | |
94 | #define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ | |
95 | #define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ | |
96 | #define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ | |
fe8c2806 WD |
97 | |
98 | /*----------------------------------------------------------------------------- | |
c157d8e2 SR |
99 | | Memory Controller Options 1 |
100 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
101 | #define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ |
102 | #define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ | |
fe8c2806 WD |
103 | |
104 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
105 | | SDRAM DEVPOT Options |
106 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
107 | #define SDRAM_DEVOPT_DLL 0x80000000 |
108 | #define SDRAM_DEVOPT_DS 0x40000000 | |
fe8c2806 WD |
109 | |
110 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
111 | | SDRAM MCSTS Options |
112 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
113 | #define SDRAM_MCSTS_MRSC 0x80000000 |
114 | #define SDRAM_MCSTS_SRMS 0x40000000 | |
115 | #define SDRAM_MCSTS_CIS 0x20000000 | |
fe8c2806 WD |
116 | |
117 | /*----------------------------------------------------------------------------- | |
c157d8e2 SR |
118 | | SDRAM Refresh Timer Register |
119 | +-----------------------------------------------------------------------------*/ | |
f013dacf | 120 | #define SDRAM_RTR_RINT_MASK 0xFFFF0000 |
fe8c2806 | 121 | #define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) |
f013dacf | 122 | #define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) |
fe8c2806 WD |
123 | |
124 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
125 | | SDRAM UABus Base Address Reg |
126 | +-----------------------------------------------------------------------------*/ | |
f013dacf | 127 | #define SDRAM_UABBA_UBBA_MASK 0x0000000F |
fe8c2806 WD |
128 | |
129 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
130 | | Memory Bank 0-7 configuration |
131 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
132 | #define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ |
133 | #define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ | |
134 | #define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ | |
135 | #define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ | |
136 | #define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ | |
137 | #define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ | |
138 | #define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ | |
139 | #define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ | |
140 | #define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ | |
141 | #define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ | |
142 | #define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ | |
143 | #define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ | |
144 | #define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ | |
145 | #define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ | |
146 | #define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ | |
fe8c2806 WD |
147 | |
148 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
149 | | SDRAM TR0 Options |
150 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
151 | #define SDRAM_TR0_SDWR_MASK 0x80000000 |
152 | #define SDRAM_TR0_SDWR_2_CLK 0x00000000 | |
153 | #define SDRAM_TR0_SDWR_3_CLK 0x80000000 | |
154 | #define SDRAM_TR0_SDWD_MASK 0x40000000 | |
155 | #define SDRAM_TR0_SDWD_0_CLK 0x00000000 | |
156 | #define SDRAM_TR0_SDWD_1_CLK 0x40000000 | |
157 | #define SDRAM_TR0_SDCL_MASK 0x01800000 | |
158 | #define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 | |
159 | #define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 | |
160 | #define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 | |
161 | #define SDRAM_TR0_SDPA_MASK 0x000C0000 | |
162 | #define SDRAM_TR0_SDPA_2_CLK 0x00040000 | |
163 | #define SDRAM_TR0_SDPA_3_CLK 0x00080000 | |
164 | #define SDRAM_TR0_SDPA_4_CLK 0x000C0000 | |
165 | #define SDRAM_TR0_SDCP_MASK 0x00030000 | |
166 | #define SDRAM_TR0_SDCP_2_CLK 0x00000000 | |
167 | #define SDRAM_TR0_SDCP_3_CLK 0x00010000 | |
168 | #define SDRAM_TR0_SDCP_4_CLK 0x00020000 | |
169 | #define SDRAM_TR0_SDCP_5_CLK 0x00030000 | |
170 | #define SDRAM_TR0_SDLD_MASK 0x0000C000 | |
171 | #define SDRAM_TR0_SDLD_1_CLK 0x00000000 | |
172 | #define SDRAM_TR0_SDLD_2_CLK 0x00004000 | |
173 | #define SDRAM_TR0_SDRA_MASK 0x0000001C | |
174 | #define SDRAM_TR0_SDRA_6_CLK 0x00000000 | |
175 | #define SDRAM_TR0_SDRA_7_CLK 0x00000004 | |
176 | #define SDRAM_TR0_SDRA_8_CLK 0x00000008 | |
177 | #define SDRAM_TR0_SDRA_9_CLK 0x0000000C | |
178 | #define SDRAM_TR0_SDRA_10_CLK 0x00000010 | |
179 | #define SDRAM_TR0_SDRA_11_CLK 0x00000014 | |
180 | #define SDRAM_TR0_SDRA_12_CLK 0x00000018 | |
181 | #define SDRAM_TR0_SDRA_13_CLK 0x0000001C | |
182 | #define SDRAM_TR0_SDRD_MASK 0x00000003 | |
183 | #define SDRAM_TR0_SDRD_2_CLK 0x00000001 | |
184 | #define SDRAM_TR0_SDRD_3_CLK 0x00000002 | |
185 | #define SDRAM_TR0_SDRD_4_CLK 0x00000003 | |
fe8c2806 WD |
186 | |
187 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
188 | | SDRAM TR1 Options |
189 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
190 | #define SDRAM_TR1_RDSS_MASK 0xC0000000 |
191 | #define SDRAM_TR1_RDSS_TR0 0x00000000 | |
192 | #define SDRAM_TR1_RDSS_TR1 0x40000000 | |
193 | #define SDRAM_TR1_RDSS_TR2 0x80000000 | |
194 | #define SDRAM_TR1_RDSS_TR3 0xC0000000 | |
195 | #define SDRAM_TR1_RDSL_MASK 0x00C00000 | |
196 | #define SDRAM_TR1_RDSL_STAGE1 0x00000000 | |
197 | #define SDRAM_TR1_RDSL_STAGE2 0x00400000 | |
198 | #define SDRAM_TR1_RDSL_STAGE3 0x00800000 | |
199 | #define SDRAM_TR1_RDCD_MASK 0x00000800 | |
200 | #define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 | |
201 | #define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 | |
202 | #define SDRAM_TR1_RDCT_MASK 0x000001FF | |
203 | #define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) | |
204 | #define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) | |
205 | #define SDRAM_TR1_RDCT_MIN 0x00000000 | |
206 | #define SDRAM_TR1_RDCT_MAX 0x000001FF | |
fe8c2806 WD |
207 | |
208 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
209 | | SDRAM WDDCTR Options |
210 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
211 | #define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 |
212 | #define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 | |
213 | #define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 | |
214 | #define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 | |
215 | #define SDRAM_WDDCTR_DCD_MASK 0x000001FF | |
fe8c2806 WD |
216 | |
217 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
218 | | SDRAM CLKTR Options |
219 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
220 | #define SDRAM_CLKTR_CLKP_MASK 0xC0000000 |
221 | #define SDRAM_CLKTR_CLKP_0DEG 0x00000000 | |
222 | #define SDRAM_CLKTR_CLKP_90DEG 0x40000000 | |
223 | #define SDRAM_CLKTR_CLKP_180DEG 0x80000000 | |
224 | #define SDRAM_CLKTR_DCDT_MASK 0x000001FF | |
fe8c2806 WD |
225 | |
226 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
227 | | SDRAM DLYCAL Options |
228 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
229 | #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC |
230 | #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) | |
231 | #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) | |
fe8c2806 WD |
232 | |
233 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
234 | | General Definition |
235 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
236 | #define DEFAULT_SPD_ADDR1 0x53 |
237 | #define DEFAULT_SPD_ADDR2 0x52 | |
238 | #define MAXBANKS 4 /* at most 4 dimm banks */ | |
239 | #define MAX_SPD_BYTES 256 | |
240 | #define NUMHALFCYCLES 4 | |
241 | #define NUMMEMTESTS 8 | |
242 | #define NUMMEMWORDS 8 | |
243 | #define MAXBXCR 4 | |
244 | #define TRUE 1 | |
245 | #define FALSE 0 | |
fe8c2806 | 246 | |
e2ebe696 SR |
247 | /* |
248 | * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory | |
249 | * region. Right now the cache should still be disabled in U-Boot because of the | |
250 | * EMAC driver, that need it's buffer descriptor to be located in non cached | |
251 | * memory. | |
252 | * | |
253 | * If at some time this restriction doesn't apply anymore, just define | |
254 | * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup | |
255 | * everything correctly. | |
256 | */ | |
257 | #ifdef CFG_ENABLE_SDRAM_CACHE | |
258 | #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ | |
259 | #else | |
260 | #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ | |
261 | #endif | |
262 | ||
fd49bf02 SR |
263 | /* bank_parms is used to sort the bank sizes by descending order */ |
264 | struct bank_param { | |
265 | unsigned long cr; | |
266 | unsigned long bank_size_bytes; | |
267 | }; | |
268 | ||
269 | typedef struct bank_param BANKPARMS; | |
270 | ||
271 | #ifdef CFG_SIMULATE_SPD_EEPROM | |
d2f68006 | 272 | extern const unsigned char cfg_simulate_spd_eeprom[128]; |
fd49bf02 | 273 | #endif |
fe8c2806 | 274 | |
d2d43276 SR |
275 | static unsigned char spd_read(uchar chip, uint addr); |
276 | static void get_spd_info(unsigned long *dimm_populated, | |
277 | unsigned char *iic0_dimm_addr, | |
278 | unsigned long num_dimm_banks); | |
279 | static void check_mem_type(unsigned long *dimm_populated, | |
280 | unsigned char *iic0_dimm_addr, | |
281 | unsigned long num_dimm_banks); | |
282 | static void check_volt_type(unsigned long *dimm_populated, | |
283 | unsigned char *iic0_dimm_addr, | |
284 | unsigned long num_dimm_banks); | |
285 | static void program_cfg0(unsigned long *dimm_populated, | |
286 | unsigned char *iic0_dimm_addr, | |
287 | unsigned long num_dimm_banks); | |
288 | static void program_cfg1(unsigned long *dimm_populated, | |
289 | unsigned char *iic0_dimm_addr, | |
290 | unsigned long num_dimm_banks); | |
291 | static void program_rtr(unsigned long *dimm_populated, | |
292 | unsigned char *iic0_dimm_addr, | |
293 | unsigned long num_dimm_banks); | |
294 | static void program_tr0(unsigned long *dimm_populated, | |
295 | unsigned char *iic0_dimm_addr, | |
296 | unsigned long num_dimm_banks); | |
297 | static void program_tr1(void); | |
298 | ||
299 | #ifdef CONFIG_DDR_ECC | |
300 | static void program_ecc(unsigned long num_bytes); | |
301 | #endif | |
fe8c2806 | 302 | |
d2d43276 SR |
303 | static unsigned long program_bxcr(unsigned long *dimm_populated, |
304 | unsigned char *iic0_dimm_addr, | |
305 | unsigned long num_dimm_banks); | |
fe8c2806 WD |
306 | |
307 | /* | |
308 | * This function is reading data from the DIMM module EEPROM over the SPD bus | |
309 | * and uses that to program the sdram controller. | |
310 | * | |
0c8721a4 | 311 | * This works on boards that has the same schematics that the AMCC walnut has. |
fe8c2806 WD |
312 | * |
313 | * BUG: Don't handle ECC memory | |
314 | * BUG: A few values in the TR register is currently hardcoded | |
315 | */ | |
fe8c2806 | 316 | long int spd_sdram(void) { |
c157d8e2 SR |
317 | unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; |
318 | unsigned long dimm_populated[sizeof(iic0_dimm_addr)]; | |
319 | unsigned long total_size; | |
320 | unsigned long cfg0; | |
321 | unsigned long mcsts; | |
f013dacf | 322 | unsigned long num_dimm_banks; /* on board dimm banks */ |
fe8c2806 | 323 | |
c157d8e2 | 324 | num_dimm_banks = sizeof(iic0_dimm_addr); |
fe8c2806 WD |
325 | |
326 | /* | |
327 | * Make sure I2C controller is initialized | |
328 | * before continuing. | |
329 | */ | |
330 | i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); | |
331 | ||
c157d8e2 SR |
332 | /* |
333 | * Read the SPD information using I2C interface. Check to see if the | |
334 | * DIMM slots are populated. | |
335 | */ | |
336 | get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
fe8c2806 | 337 | |
c157d8e2 SR |
338 | /* |
339 | * Check the memory type for the dimms plugged. | |
340 | */ | |
341 | check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
fe8c2806 | 342 | |
c157d8e2 SR |
343 | /* |
344 | * Check the voltage type for the dimms plugged. | |
345 | */ | |
346 | check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
fe8c2806 | 347 | |
ed4633c9 | 348 | #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) |
c157d8e2 SR |
349 | /* |
350 | * Soft-reset SDRAM controller. | |
351 | */ | |
352 | mtsdr(sdr_srst, SDR0_SRST_DMC); | |
353 | mtsdr(sdr_srst, 0x00000000); | |
63153492 WD |
354 | #endif |
355 | ||
c157d8e2 SR |
356 | /* |
357 | * program 440GP SDRAM controller options (SDRAM0_CFG0) | |
358 | */ | |
359 | program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
360 | ||
361 | /* | |
362 | * program 440GP SDRAM controller options (SDRAM0_CFG1) | |
363 | */ | |
364 | program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
365 | ||
366 | /* | |
367 | * program SDRAM refresh register (SDRAM0_RTR) | |
368 | */ | |
369 | program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
370 | ||
371 | /* | |
372 | * program SDRAM Timing Register 0 (SDRAM0_TR0) | |
373 | */ | |
374 | program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
375 | ||
376 | /* | |
377 | * program the BxCR registers to find out total sdram installed | |
378 | */ | |
379 | total_size = program_bxcr(dimm_populated, iic0_dimm_addr, | |
380 | num_dimm_banks); | |
381 | ||
e2ebe696 SR |
382 | #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */ |
383 | /* and program tlb entries for this size (dynamic) */ | |
dbca2085 | 384 | program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE); |
e2ebe696 SR |
385 | #endif |
386 | ||
c157d8e2 SR |
387 | /* |
388 | * program SDRAM Clock Timing Register (SDRAM0_CLKTR) | |
389 | */ | |
390 | mtsdram(mem_clktr, 0x40000000); | |
391 | ||
392 | /* | |
393 | * delay to ensure 200 usec has elapsed | |
394 | */ | |
395 | udelay(400); | |
396 | ||
397 | /* | |
398 | * enable the memory controller | |
399 | */ | |
400 | mfsdram(mem_cfg0, cfg0); | |
401 | mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN); | |
402 | ||
403 | /* | |
404 | * wait for SDRAM_CFG0_DC_EN to complete | |
405 | */ | |
406 | while (1) { | |
407 | mfsdram(mem_mcsts, mcsts); | |
d2d43276 | 408 | if ((mcsts & SDRAM_MCSTS_MRSC) != 0) |
c157d8e2 | 409 | break; |
8bde7f77 | 410 | } |
fe8c2806 | 411 | |
c157d8e2 SR |
412 | /* |
413 | * program SDRAM Timing Register 1, adding some delays | |
414 | */ | |
415 | program_tr1(); | |
fe8c2806 | 416 | |
d2d43276 | 417 | #ifdef CONFIG_DDR_ECC |
c157d8e2 | 418 | /* |
d2d43276 | 419 | * If ecc is enabled, initialize the parity bits. |
c157d8e2 | 420 | */ |
d2d43276 SR |
421 | program_ecc(total_size); |
422 | #endif | |
fe8c2806 WD |
423 | |
424 | return total_size; | |
425 | } | |
426 | ||
d2d43276 | 427 | static unsigned char spd_read(uchar chip, uint addr) |
fd49bf02 | 428 | { |
fe8c2806 WD |
429 | unsigned char data[2]; |
430 | ||
fd49bf02 SR |
431 | #ifdef CFG_SIMULATE_SPD_EEPROM |
432 | if (chip == CFG_SIMULATE_SPD_EEPROM) { | |
433 | /* | |
434 | * Onboard spd eeprom requested -> simulate values | |
435 | */ | |
436 | return cfg_simulate_spd_eeprom[addr]; | |
437 | } | |
438 | #endif /* CFG_SIMULATE_SPD_EEPROM */ | |
439 | ||
c157d8e2 SR |
440 | if (i2c_probe(chip) == 0) { |
441 | if (i2c_read(chip, addr, 1, data, 1) == 0) { | |
442 | return data[0]; | |
443 | } | |
444 | } | |
445 | ||
446 | return 0; | |
fe8c2806 WD |
447 | } |
448 | ||
d2d43276 SR |
449 | static void get_spd_info(unsigned long *dimm_populated, |
450 | unsigned char *iic0_dimm_addr, | |
451 | unsigned long num_dimm_banks) | |
fe8c2806 | 452 | { |
c157d8e2 SR |
453 | unsigned long dimm_num; |
454 | unsigned long dimm_found; | |
455 | unsigned char num_of_bytes; | |
456 | unsigned char total_size; | |
457 | ||
458 | dimm_found = FALSE; | |
459 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
460 | num_of_bytes = 0; | |
461 | total_size = 0; | |
462 | ||
463 | num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); | |
464 | total_size = spd_read(iic0_dimm_addr[dimm_num], 1); | |
465 | ||
466 | if ((num_of_bytes != 0) && (total_size != 0)) { | |
467 | dimm_populated[dimm_num] = TRUE; | |
468 | dimm_found = TRUE; | |
d2d43276 | 469 | debug("DIMM slot %lu: populated\n", dimm_num); |
c157d8e2 SR |
470 | } else { |
471 | dimm_populated[dimm_num] = FALSE; | |
d2d43276 | 472 | debug("DIMM slot %lu: Not populated\n", dimm_num); |
c157d8e2 | 473 | } |
8bde7f77 | 474 | } |
fe8c2806 | 475 | |
c157d8e2 SR |
476 | if (dimm_found == FALSE) { |
477 | printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); | |
a5d71e29 | 478 | spd_ddr_init_hang (); |
c157d8e2 | 479 | } |
fe8c2806 WD |
480 | } |
481 | ||
d2d43276 SR |
482 | static void check_mem_type(unsigned long *dimm_populated, |
483 | unsigned char *iic0_dimm_addr, | |
484 | unsigned long num_dimm_banks) | |
fe8c2806 | 485 | { |
c157d8e2 SR |
486 | unsigned long dimm_num; |
487 | unsigned char dimm_type; | |
488 | ||
489 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
490 | if (dimm_populated[dimm_num] == TRUE) { | |
491 | dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); | |
492 | switch (dimm_type) { | |
493 | case 7: | |
d2d43276 | 494 | debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num); |
c157d8e2 SR |
495 | break; |
496 | default: | |
497 | printf("ERROR: Unsupported DIMM detected in slot %lu.\n", | |
498 | dimm_num); | |
499 | printf("Only DDR SDRAM DIMMs are supported.\n"); | |
500 | printf("Replace the DIMM module with a supported DIMM.\n\n"); | |
a5d71e29 | 501 | spd_ddr_init_hang (); |
c157d8e2 SR |
502 | break; |
503 | } | |
504 | } | |
8bde7f77 | 505 | } |
fe8c2806 WD |
506 | } |
507 | ||
d2d43276 SR |
508 | static void check_volt_type(unsigned long *dimm_populated, |
509 | unsigned char *iic0_dimm_addr, | |
510 | unsigned long num_dimm_banks) | |
fe8c2806 | 511 | { |
c157d8e2 SR |
512 | unsigned long dimm_num; |
513 | unsigned long voltage_type; | |
514 | ||
515 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
516 | if (dimm_populated[dimm_num] == TRUE) { | |
517 | voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); | |
518 | if (voltage_type != 0x04) { | |
519 | printf("ERROR: DIMM %lu with unsupported voltage level.\n", | |
520 | dimm_num); | |
a5d71e29 | 521 | spd_ddr_init_hang (); |
c157d8e2 | 522 | } else { |
d2d43276 | 523 | debug("DIMM %lu voltage level supported.\n", dimm_num); |
c157d8e2 SR |
524 | } |
525 | break; | |
526 | } | |
8bde7f77 | 527 | } |
fe8c2806 WD |
528 | } |
529 | ||
d2d43276 SR |
530 | static void program_cfg0(unsigned long *dimm_populated, |
531 | unsigned char *iic0_dimm_addr, | |
532 | unsigned long num_dimm_banks) | |
fe8c2806 | 533 | { |
c157d8e2 SR |
534 | unsigned long dimm_num; |
535 | unsigned long cfg0; | |
536 | unsigned long ecc_enabled; | |
537 | unsigned char ecc; | |
538 | unsigned char attributes; | |
539 | unsigned long data_width; | |
540 | unsigned long dimm_32bit; | |
541 | unsigned long dimm_64bit; | |
542 | ||
543 | /* | |
544 | * get Memory Controller Options 0 data | |
545 | */ | |
546 | mfsdram(mem_cfg0, cfg0); | |
547 | ||
548 | /* | |
549 | * clear bits | |
550 | */ | |
551 | cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK | | |
552 | SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD | | |
553 | SDRAM_CFG0_DMWD_MASK | | |
554 | SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP); | |
555 | ||
556 | ||
557 | /* | |
558 | * FIXME: assume the DDR SDRAMs in both banks are the same | |
559 | */ | |
560 | ecc_enabled = TRUE; | |
561 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
562 | if (dimm_populated[dimm_num] == TRUE) { | |
563 | ecc = spd_read(iic0_dimm_addr[dimm_num], 11); | |
564 | if (ecc != 0x02) { | |
565 | ecc_enabled = FALSE; | |
566 | } | |
567 | ||
568 | /* | |
569 | * program Registered DIMM Enable | |
570 | */ | |
571 | attributes = spd_read(iic0_dimm_addr[dimm_num], 21); | |
572 | if ((attributes & 0x02) != 0x00) { | |
573 | cfg0 |= SDRAM_CFG0_RDEN; | |
574 | } | |
575 | ||
576 | /* | |
577 | * program DDR SDRAM Data Width | |
578 | */ | |
579 | data_width = | |
580 | (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) + | |
581 | (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8); | |
582 | if (data_width == 64 || data_width == 72) { | |
583 | dimm_64bit = TRUE; | |
584 | cfg0 |= SDRAM_CFG0_DMWD_64; | |
585 | } else if (data_width == 32 || data_width == 40) { | |
586 | dimm_32bit = TRUE; | |
587 | cfg0 |= SDRAM_CFG0_DMWD_32; | |
588 | } else { | |
589 | printf("WARNING: DIMM with datawidth of %lu bits.\n", | |
590 | data_width); | |
591 | printf("Only DIMMs with 32 or 64 bit datawidths supported.\n"); | |
a5d71e29 | 592 | spd_ddr_init_hang (); |
c157d8e2 SR |
593 | } |
594 | break; | |
595 | } | |
8bde7f77 | 596 | } |
c157d8e2 SR |
597 | |
598 | /* | |
599 | * program Memory Data Error Checking | |
600 | */ | |
601 | if (ecc_enabled == TRUE) { | |
602 | cfg0 |= SDRAM_CFG0_MCHK_GEN; | |
603 | } else { | |
604 | cfg0 |= SDRAM_CFG0_MCHK_NON; | |
605 | } | |
606 | ||
607 | /* | |
a2c95a72 | 608 | * program Page Management Unit (0 == enabled) |
c157d8e2 | 609 | */ |
a2c95a72 | 610 | cfg0 &= ~SDRAM_CFG0_PMUD; |
c157d8e2 SR |
611 | |
612 | /* | |
613 | * program Memory Controller Options 0 | |
614 | * Note: DCEN must be enabled after all DDR SDRAM controller | |
615 | * configuration registers get initialized. | |
616 | */ | |
617 | mtsdram(mem_cfg0, cfg0); | |
fe8c2806 WD |
618 | } |
619 | ||
d2d43276 SR |
620 | static void program_cfg1(unsigned long *dimm_populated, |
621 | unsigned char *iic0_dimm_addr, | |
622 | unsigned long num_dimm_banks) | |
fe8c2806 | 623 | { |
c157d8e2 SR |
624 | unsigned long cfg1; |
625 | mfsdram(mem_cfg1, cfg1); | |
626 | ||
627 | /* | |
628 | * Self-refresh exit, disable PM | |
629 | */ | |
630 | cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN); | |
631 | ||
632 | /* | |
633 | * program Memory Controller Options 1 | |
634 | */ | |
635 | mtsdram(mem_cfg1, cfg1); | |
fe8c2806 WD |
636 | } |
637 | ||
d2d43276 SR |
638 | static void program_rtr(unsigned long *dimm_populated, |
639 | unsigned char *iic0_dimm_addr, | |
640 | unsigned long num_dimm_banks) | |
fe8c2806 | 641 | { |
c157d8e2 SR |
642 | unsigned long dimm_num; |
643 | unsigned long bus_period_x_10; | |
644 | unsigned long refresh_rate = 0; | |
645 | unsigned char refresh_rate_type; | |
646 | unsigned long refresh_interval; | |
647 | unsigned long sdram_rtr; | |
087dfdb7 | 648 | PPC4xx_SYS_INFO sys_info; |
c157d8e2 SR |
649 | |
650 | /* | |
651 | * get the board info | |
652 | */ | |
653 | get_sys_info(&sys_info); | |
654 | bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); | |
655 | ||
c157d8e2 SR |
656 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
657 | if (dimm_populated[dimm_num] == TRUE) { | |
658 | refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); | |
659 | switch (refresh_rate_type) { | |
660 | case 0x00: | |
661 | refresh_rate = 15625; | |
662 | break; | |
663 | case 0x01: | |
664 | refresh_rate = 15625/4; | |
665 | break; | |
666 | case 0x02: | |
667 | refresh_rate = 15625/2; | |
668 | break; | |
669 | case 0x03: | |
670 | refresh_rate = 15626*2; | |
671 | break; | |
672 | case 0x04: | |
673 | refresh_rate = 15625*4; | |
674 | break; | |
675 | case 0x05: | |
676 | refresh_rate = 15625*8; | |
677 | break; | |
678 | default: | |
679 | printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n", | |
680 | dimm_num); | |
681 | printf("Replace the DIMM module with a supported DIMM.\n"); | |
682 | break; | |
683 | } | |
684 | ||
685 | break; | |
686 | } | |
8bde7f77 | 687 | } |
fe8c2806 | 688 | |
c157d8e2 SR |
689 | refresh_interval = refresh_rate * 10 / bus_period_x_10; |
690 | sdram_rtr = (refresh_interval & 0x3ff8) << 16; | |
fe8c2806 | 691 | |
c157d8e2 SR |
692 | /* |
693 | * program Refresh Timer Register (SDRAM0_RTR) | |
694 | */ | |
695 | mtsdram(mem_rtr, sdram_rtr); | |
fe8c2806 WD |
696 | } |
697 | ||
d2d43276 SR |
698 | static void program_tr0(unsigned long *dimm_populated, |
699 | unsigned char *iic0_dimm_addr, | |
700 | unsigned long num_dimm_banks) | |
fe8c2806 | 701 | { |
c157d8e2 SR |
702 | unsigned long dimm_num; |
703 | unsigned long tr0; | |
704 | unsigned char wcsbc; | |
705 | unsigned char t_rp_ns; | |
706 | unsigned char t_rcd_ns; | |
707 | unsigned char t_ras_ns; | |
708 | unsigned long t_rp_clk; | |
709 | unsigned long t_ras_rcd_clk; | |
710 | unsigned long t_rcd_clk; | |
711 | unsigned long t_rfc_clk; | |
712 | unsigned long plb_check; | |
713 | unsigned char cas_bit; | |
714 | unsigned long cas_index; | |
715 | unsigned char cas_2_0_available; | |
716 | unsigned char cas_2_5_available; | |
717 | unsigned char cas_3_0_available; | |
718 | unsigned long cycle_time_ns_x_10[3]; | |
719 | unsigned long tcyc_3_0_ns_x_10; | |
720 | unsigned long tcyc_2_5_ns_x_10; | |
721 | unsigned long tcyc_2_0_ns_x_10; | |
722 | unsigned long tcyc_reg; | |
723 | unsigned long bus_period_x_10; | |
087dfdb7 | 724 | PPC4xx_SYS_INFO sys_info; |
c157d8e2 | 725 | unsigned long residue; |
8bde7f77 | 726 | |
c157d8e2 SR |
727 | /* |
728 | * get the board info | |
729 | */ | |
730 | get_sys_info(&sys_info); | |
731 | bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); | |
8bde7f77 | 732 | |
c157d8e2 SR |
733 | /* |
734 | * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits | |
735 | */ | |
736 | mfsdram(mem_tr0, tr0); | |
737 | tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK | | |
738 | SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK | | |
739 | SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK | | |
740 | SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK); | |
741 | ||
742 | /* | |
743 | * initialization | |
744 | */ | |
745 | wcsbc = 0; | |
746 | t_rp_ns = 0; | |
747 | t_rcd_ns = 0; | |
748 | t_ras_ns = 0; | |
749 | cas_2_0_available = TRUE; | |
750 | cas_2_5_available = TRUE; | |
751 | cas_3_0_available = TRUE; | |
752 | tcyc_2_0_ns_x_10 = 0; | |
753 | tcyc_2_5_ns_x_10 = 0; | |
754 | tcyc_3_0_ns_x_10 = 0; | |
755 | ||
756 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
757 | if (dimm_populated[dimm_num] == TRUE) { | |
758 | wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); | |
f013dacf | 759 | t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; |
c157d8e2 SR |
760 | t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; |
761 | t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30); | |
762 | cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); | |
763 | ||
764 | for (cas_index = 0; cas_index < 3; cas_index++) { | |
765 | switch (cas_index) { | |
766 | case 0: | |
767 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); | |
768 | break; | |
769 | case 1: | |
770 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); | |
771 | break; | |
772 | default: | |
773 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); | |
774 | break; | |
775 | } | |
776 | ||
777 | if ((tcyc_reg & 0x0F) >= 10) { | |
778 | printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n", | |
779 | dimm_num); | |
a5d71e29 | 780 | spd_ddr_init_hang (); |
c157d8e2 SR |
781 | } |
782 | ||
783 | cycle_time_ns_x_10[cas_index] = | |
784 | (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F); | |
785 | } | |
786 | ||
787 | cas_index = 0; | |
788 | ||
789 | if ((cas_bit & 0x80) != 0) { | |
790 | cas_index += 3; | |
791 | } else if ((cas_bit & 0x40) != 0) { | |
792 | cas_index += 2; | |
793 | } else if ((cas_bit & 0x20) != 0) { | |
794 | cas_index += 1; | |
795 | } | |
796 | ||
797 | if (((cas_bit & 0x10) != 0) && (cas_index < 3)) { | |
798 | tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; | |
799 | cas_index++; | |
800 | } else { | |
801 | if (cas_index != 0) { | |
802 | cas_index++; | |
803 | } | |
804 | cas_3_0_available = FALSE; | |
805 | } | |
806 | ||
807 | if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { | |
808 | tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index]; | |
809 | cas_index++; | |
810 | } else { | |
811 | if (cas_index != 0) { | |
812 | cas_index++; | |
813 | } | |
814 | cas_2_5_available = FALSE; | |
815 | } | |
816 | ||
817 | if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { | |
818 | tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; | |
819 | cas_index++; | |
820 | } else { | |
821 | if (cas_index != 0) { | |
822 | cas_index++; | |
823 | } | |
824 | cas_2_0_available = FALSE; | |
825 | } | |
826 | ||
827 | break; | |
8bde7f77 | 828 | } |
c157d8e2 SR |
829 | } |
830 | ||
831 | /* | |
832 | * Program SD_WR and SD_WCSBC fields | |
833 | */ | |
f013dacf | 834 | tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */ |
c157d8e2 SR |
835 | switch (wcsbc) { |
836 | case 0: | |
837 | tr0 |= SDRAM_TR0_SDWD_0_CLK; | |
838 | break; | |
839 | default: | |
840 | tr0 |= SDRAM_TR0_SDWD_1_CLK; | |
841 | break; | |
842 | } | |
843 | ||
844 | /* | |
845 | * Program SD_CASL field | |
846 | */ | |
847 | if ((cas_2_0_available == TRUE) && | |
848 | (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { | |
849 | tr0 |= SDRAM_TR0_SDCL_2_0_CLK; | |
850 | } else if ((cas_2_5_available == TRUE) && | |
851 | (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { | |
852 | tr0 |= SDRAM_TR0_SDCL_2_5_CLK; | |
853 | } else if ((cas_3_0_available == TRUE) && | |
854 | (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { | |
855 | tr0 |= SDRAM_TR0_SDCL_3_0_CLK; | |
856 | } else { | |
857 | printf("ERROR: No supported CAS latency with the installed DIMMs.\n"); | |
858 | printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); | |
859 | printf("Make sure the PLB speed is within the supported range.\n"); | |
a5d71e29 | 860 | spd_ddr_init_hang (); |
c157d8e2 SR |
861 | } |
862 | ||
863 | /* | |
864 | * Calculate Trp in clock cycles and round up if necessary | |
865 | * Program SD_PTA field | |
866 | */ | |
867 | t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION; | |
868 | plb_check = ONE_BILLION * t_rp_clk / t_rp_ns; | |
869 | if (sys_info.freqPLB != plb_check) { | |
870 | t_rp_clk++; | |
871 | } | |
872 | switch ((unsigned long)t_rp_clk) { | |
873 | case 0: | |
874 | case 1: | |
875 | case 2: | |
876 | tr0 |= SDRAM_TR0_SDPA_2_CLK; | |
877 | break; | |
878 | case 3: | |
879 | tr0 |= SDRAM_TR0_SDPA_3_CLK; | |
880 | break; | |
881 | default: | |
882 | tr0 |= SDRAM_TR0_SDPA_4_CLK; | |
883 | break; | |
884 | } | |
885 | ||
886 | /* | |
887 | * Program SD_CTP field | |
888 | */ | |
889 | t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION; | |
890 | plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns); | |
891 | if (sys_info.freqPLB != plb_check) { | |
892 | t_ras_rcd_clk++; | |
893 | } | |
894 | switch (t_ras_rcd_clk) { | |
895 | case 0: | |
896 | case 1: | |
897 | case 2: | |
898 | tr0 |= SDRAM_TR0_SDCP_2_CLK; | |
899 | break; | |
900 | case 3: | |
901 | tr0 |= SDRAM_TR0_SDCP_3_CLK; | |
902 | break; | |
903 | case 4: | |
904 | tr0 |= SDRAM_TR0_SDCP_4_CLK; | |
905 | break; | |
906 | default: | |
907 | tr0 |= SDRAM_TR0_SDCP_5_CLK; | |
908 | break; | |
909 | } | |
910 | ||
911 | /* | |
912 | * Program SD_LDF field | |
913 | */ | |
914 | tr0 |= SDRAM_TR0_SDLD_2_CLK; | |
915 | ||
916 | /* | |
917 | * Program SD_RFTA field | |
918 | * FIXME tRFC hardcoded as 75 nanoseconds | |
919 | */ | |
920 | t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75); | |
921 | residue = sys_info.freqPLB % (ONE_BILLION / 75); | |
922 | if (residue >= (ONE_BILLION / 150)) { | |
923 | t_rfc_clk++; | |
924 | } | |
925 | switch (t_rfc_clk) { | |
926 | case 0: | |
927 | case 1: | |
928 | case 2: | |
929 | case 3: | |
930 | case 4: | |
931 | case 5: | |
932 | case 6: | |
933 | tr0 |= SDRAM_TR0_SDRA_6_CLK; | |
934 | break; | |
935 | case 7: | |
936 | tr0 |= SDRAM_TR0_SDRA_7_CLK; | |
937 | break; | |
938 | case 8: | |
939 | tr0 |= SDRAM_TR0_SDRA_8_CLK; | |
940 | break; | |
941 | case 9: | |
942 | tr0 |= SDRAM_TR0_SDRA_9_CLK; | |
943 | break; | |
944 | case 10: | |
945 | tr0 |= SDRAM_TR0_SDRA_10_CLK; | |
946 | break; | |
947 | case 11: | |
948 | tr0 |= SDRAM_TR0_SDRA_11_CLK; | |
949 | break; | |
950 | case 12: | |
951 | tr0 |= SDRAM_TR0_SDRA_12_CLK; | |
952 | break; | |
953 | default: | |
954 | tr0 |= SDRAM_TR0_SDRA_13_CLK; | |
955 | break; | |
956 | } | |
8bde7f77 | 957 | |
c157d8e2 SR |
958 | /* |
959 | * Program SD_RCD field | |
960 | */ | |
961 | t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION; | |
962 | plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns; | |
963 | if (sys_info.freqPLB != plb_check) { | |
964 | t_rcd_clk++; | |
965 | } | |
966 | switch (t_rcd_clk) { | |
967 | case 0: | |
968 | case 1: | |
969 | case 2: | |
970 | tr0 |= SDRAM_TR0_SDRD_2_CLK; | |
971 | break; | |
972 | case 3: | |
973 | tr0 |= SDRAM_TR0_SDRD_3_CLK; | |
974 | break; | |
975 | default: | |
976 | tr0 |= SDRAM_TR0_SDRD_4_CLK; | |
977 | break; | |
8bde7f77 | 978 | } |
fe8c2806 | 979 | |
d2d43276 | 980 | debug("tr0: %x\n", tr0); |
c157d8e2 | 981 | mtsdram(mem_tr0, tr0); |
fe8c2806 WD |
982 | } |
983 | ||
d2d43276 SR |
984 | static int short_mem_test(void) |
985 | { | |
986 | unsigned long i, j; | |
987 | unsigned long bxcr_num; | |
988 | unsigned long *membase; | |
989 | const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { | |
990 | {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, | |
991 | 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, | |
992 | {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, | |
993 | 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, | |
994 | {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, | |
995 | 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, | |
996 | {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, | |
997 | 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, | |
998 | {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, | |
999 | 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, | |
1000 | {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, | |
1001 | 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, | |
1002 | {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, | |
1003 | 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, | |
1004 | {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, | |
1005 | 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; | |
1006 | ||
1007 | for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { | |
1008 | mtdcr(memcfga, mem_b0cr + (bxcr_num << 2)); | |
1009 | if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { | |
1010 | /* Bank is enabled */ | |
1011 | membase = (unsigned long*) | |
1012 | (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); | |
1013 | ||
1014 | /* | |
1015 | * Run the short memory test | |
1016 | */ | |
1017 | for (i = 0; i < NUMMEMTESTS; i++) { | |
1018 | for (j = 0; j < NUMMEMWORDS; j++) { | |
239f05ee | 1019 | /* printf("bank enabled base:%x\n", &membase[j]); */ |
d2d43276 SR |
1020 | membase[j] = test[i][j]; |
1021 | ppcDcbf((unsigned long)&(membase[j])); | |
1022 | } | |
1023 | ||
1024 | for (j = 0; j < NUMMEMWORDS; j++) { | |
1025 | if (membase[j] != test[i][j]) { | |
1026 | ppcDcbf((unsigned long)&(membase[j])); | |
1027 | return 0; | |
1028 | } | |
1029 | ppcDcbf((unsigned long)&(membase[j])); | |
1030 | } | |
1031 | ||
1032 | if (j < NUMMEMWORDS) | |
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * see if the rdclt value passed | |
1038 | */ | |
1039 | if (i < NUMMEMTESTS) | |
1040 | return 0; | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | return 1; | |
1045 | } | |
1046 | ||
1047 | static void program_tr1(void) | |
fe8c2806 | 1048 | { |
c157d8e2 SR |
1049 | unsigned long tr0; |
1050 | unsigned long tr1; | |
1051 | unsigned long cfg0; | |
1052 | unsigned long ecc_temp; | |
1053 | unsigned long dlycal; | |
1054 | unsigned long dly_val; | |
d2d43276 | 1055 | unsigned long k; |
c157d8e2 SR |
1056 | unsigned long max_pass_length; |
1057 | unsigned long current_pass_length; | |
1058 | unsigned long current_fail_length; | |
1059 | unsigned long current_start; | |
1060 | unsigned long rdclt; | |
1061 | unsigned long rdclt_offset; | |
1062 | long max_start; | |
1063 | long max_end; | |
1064 | long rdclt_average; | |
1065 | unsigned char window_found; | |
1066 | unsigned char fail_found; | |
1067 | unsigned char pass_found; | |
087dfdb7 | 1068 | PPC4xx_SYS_INFO sys_info; |
c157d8e2 SR |
1069 | |
1070 | /* | |
1071 | * get the board info | |
1072 | */ | |
1073 | get_sys_info(&sys_info); | |
1074 | ||
1075 | /* | |
1076 | * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits | |
1077 | */ | |
1078 | mfsdram(mem_tr1, tr1); | |
1079 | tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK | | |
1080 | SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK); | |
1081 | ||
1082 | mfsdram(mem_tr0, tr0); | |
1083 | if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) && | |
1084 | (sys_info.freqPLB > 100000000)) { | |
1085 | tr1 |= SDRAM_TR1_RDSS_TR2; | |
1086 | tr1 |= SDRAM_TR1_RDSL_STAGE3; | |
1087 | tr1 |= SDRAM_TR1_RDCD_RCD_1_2; | |
1088 | } else { | |
1089 | tr1 |= SDRAM_TR1_RDSS_TR1; | |
1090 | tr1 |= SDRAM_TR1_RDSL_STAGE2; | |
1091 | tr1 |= SDRAM_TR1_RDCD_RCD_0_0; | |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * save CFG0 ECC setting to a temporary variable and turn ECC off | |
1096 | */ | |
1097 | mfsdram(mem_cfg0, cfg0); | |
1098 | ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK; | |
1099 | mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); | |
1100 | ||
1101 | /* | |
1102 | * get the delay line calibration register value | |
1103 | */ | |
1104 | mfsdram(mem_dlycal, dlycal); | |
1105 | dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; | |
1106 | ||
1107 | max_pass_length = 0; | |
1108 | max_start = 0; | |
1109 | max_end = 0; | |
1110 | current_pass_length = 0; | |
1111 | current_fail_length = 0; | |
1112 | current_start = 0; | |
1113 | rdclt_offset = 0; | |
1114 | window_found = FALSE; | |
1115 | fail_found = FALSE; | |
1116 | pass_found = FALSE; | |
d2d43276 SR |
1117 | debug("Starting memory test "); |
1118 | ||
c157d8e2 | 1119 | for (k = 0; k < NUMHALFCYCLES; k++) { |
d2d43276 | 1120 | for (rdclt = 0; rdclt < dly_val; rdclt++) { |
c157d8e2 SR |
1121 | /* |
1122 | * Set the timing reg for the test. | |
1123 | */ | |
1124 | mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); | |
1125 | ||
d2d43276 | 1126 | if (short_mem_test()) { |
c157d8e2 SR |
1127 | if (fail_found == TRUE) { |
1128 | pass_found = TRUE; | |
1129 | if (current_pass_length == 0) { | |
1130 | current_start = rdclt_offset + rdclt; | |
1131 | } | |
1132 | ||
1133 | current_fail_length = 0; | |
1134 | current_pass_length++; | |
1135 | ||
1136 | if (current_pass_length > max_pass_length) { | |
1137 | max_pass_length = current_pass_length; | |
1138 | max_start = current_start; | |
1139 | max_end = rdclt_offset + rdclt; | |
1140 | } | |
1141 | } | |
1142 | } else { | |
1143 | current_pass_length = 0; | |
1144 | current_fail_length++; | |
1145 | ||
1146 | if (current_fail_length >= (dly_val>>2)) { | |
1147 | if (fail_found == FALSE) { | |
1148 | fail_found = TRUE; | |
1149 | } else if (pass_found == TRUE) { | |
1150 | window_found = TRUE; | |
1151 | break; | |
1152 | } | |
1153 | } | |
8bde7f77 | 1154 | } |
8bde7f77 | 1155 | } |
d2d43276 SR |
1156 | debug("."); |
1157 | ||
c157d8e2 | 1158 | if (window_found == TRUE) { |
8bde7f77 | 1159 | break; |
8bde7f77 | 1160 | } |
c157d8e2 SR |
1161 | |
1162 | tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; | |
1163 | rdclt_offset += dly_val; | |
8bde7f77 | 1164 | } |
d2d43276 | 1165 | debug("\n"); |
c157d8e2 SR |
1166 | |
1167 | /* | |
1168 | * make sure we find the window | |
1169 | */ | |
1170 | if (window_found == FALSE) { | |
1171 | printf("ERROR: Cannot determine a common read delay.\n"); | |
a5d71e29 | 1172 | spd_ddr_init_hang (); |
8bde7f77 | 1173 | } |
fe8c2806 | 1174 | |
c157d8e2 SR |
1175 | /* |
1176 | * restore the orignal ECC setting | |
1177 | */ | |
1178 | mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); | |
1179 | ||
1180 | /* | |
1181 | * set the SDRAM TR1 RDCD value | |
1182 | */ | |
1183 | tr1 &= ~SDRAM_TR1_RDCD_MASK; | |
1184 | if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) { | |
1185 | tr1 |= SDRAM_TR1_RDCD_RCD_1_2; | |
1186 | } else { | |
1187 | tr1 |= SDRAM_TR1_RDCD_RCD_0_0; | |
1188 | } | |
fe8c2806 | 1189 | |
c157d8e2 SR |
1190 | /* |
1191 | * set the SDRAM TR1 RDCLT value | |
1192 | */ | |
1193 | tr1 &= ~SDRAM_TR1_RDCT_MASK; | |
1194 | while (max_end >= (dly_val << 1)) { | |
1195 | max_end -= (dly_val << 1); | |
1196 | max_start -= (dly_val << 1); | |
1197 | } | |
1198 | ||
1199 | rdclt_average = ((max_start + max_end) >> 1); | |
1200 | if (rdclt_average >= 0x60) | |
1201 | while (1) | |
1202 | ; | |
1203 | ||
1204 | if (rdclt_average < 0) { | |
1205 | rdclt_average = 0; | |
1206 | } | |
1207 | ||
1208 | if (rdclt_average >= dly_val) { | |
1209 | rdclt_average -= dly_val; | |
1210 | tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; | |
1211 | } | |
1212 | tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average); | |
fe8c2806 | 1213 | |
d2d43276 SR |
1214 | debug("tr1: %x\n", tr1); |
1215 | ||
c157d8e2 SR |
1216 | /* |
1217 | * program SDRAM Timing Register 1 TR1 | |
1218 | */ | |
1219 | mtsdram(mem_tr1, tr1); | |
fe8c2806 WD |
1220 | } |
1221 | ||
d2d43276 SR |
1222 | static unsigned long program_bxcr(unsigned long *dimm_populated, |
1223 | unsigned char *iic0_dimm_addr, | |
1224 | unsigned long num_dimm_banks) | |
fe8c2806 | 1225 | { |
c157d8e2 | 1226 | unsigned long dimm_num; |
c157d8e2 | 1227 | unsigned long bank_base_addr; |
c157d8e2 SR |
1228 | unsigned long cr; |
1229 | unsigned long i; | |
fd49bf02 | 1230 | unsigned long j; |
c157d8e2 SR |
1231 | unsigned long temp; |
1232 | unsigned char num_row_addr; | |
1233 | unsigned char num_col_addr; | |
1234 | unsigned char num_banks; | |
1235 | unsigned char bank_size_id; | |
fd49bf02 SR |
1236 | unsigned long ctrl_bank_num[MAXBANKS]; |
1237 | unsigned long bx_cr_num; | |
1238 | unsigned long largest_size_index; | |
f013dacf WD |
1239 | unsigned long largest_size; |
1240 | unsigned long current_size_index; | |
fd49bf02 SR |
1241 | BANKPARMS bank_parms[MAXBXCR]; |
1242 | unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */ | |
1243 | unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/ | |
c157d8e2 SR |
1244 | |
1245 | /* | |
1246 | * Set the BxCR regs. First, wipe out the bank config registers. | |
1247 | */ | |
fd49bf02 SR |
1248 | for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { |
1249 | mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2)); | |
c157d8e2 | 1250 | mtdcr(memcfgd, 0x00000000); |
fd49bf02 | 1251 | bank_parms[bx_cr_num].bank_size_bytes = 0; |
c157d8e2 | 1252 | } |
fd49bf02 SR |
1253 | |
1254 | #ifdef CONFIG_BAMBOO | |
1255 | /* | |
1256 | * This next section is hardware dependent and must be programmed | |
d2d43276 SR |
1257 | * to match the hardware. For bamboo, the following holds... |
1258 | * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard) | |
fd49bf02 SR |
1259 | * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1 |
1260 | * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1 | |
1261 | * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3 | |
1262 | * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM | |
1263 | */ | |
1264 | ctrl_bank_num[0] = 0; | |
1265 | ctrl_bank_num[1] = 1; | |
1266 | ctrl_bank_num[2] = 3; | |
1267 | #else | |
d2d43276 SR |
1268 | /* |
1269 | * Ocotea, Ebony and the other IBM/AMCC eval boards have | |
1270 | * 2 DIMM slots with each max 2 banks | |
1271 | */ | |
fd49bf02 | 1272 | ctrl_bank_num[0] = 0; |
d2d43276 | 1273 | ctrl_bank_num[1] = 2; |
17f50f22 | 1274 | #endif |
c157d8e2 SR |
1275 | |
1276 | /* | |
1277 | * reset the bank_base address | |
1278 | */ | |
1279 | bank_base_addr = CFG_SDRAM_BASE; | |
1280 | ||
1281 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
1282 | if (dimm_populated[dimm_num] == TRUE) { | |
1283 | num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); | |
1284 | num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); | |
1285 | num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); | |
1286 | bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); | |
d2d43276 SR |
1287 | debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num, |
1288 | num_row_addr, num_col_addr, num_banks); | |
c157d8e2 SR |
1289 | |
1290 | /* | |
1291 | * Set the SDRAM0_BxCR regs | |
1292 | */ | |
1293 | cr = 0; | |
c157d8e2 SR |
1294 | switch (bank_size_id) { |
1295 | case 0x02: | |
1296 | cr |= SDRAM_BXCR_SDSZ_8; | |
1297 | break; | |
1298 | case 0x04: | |
1299 | cr |= SDRAM_BXCR_SDSZ_16; | |
1300 | break; | |
1301 | case 0x08: | |
1302 | cr |= SDRAM_BXCR_SDSZ_32; | |
1303 | break; | |
1304 | case 0x10: | |
1305 | cr |= SDRAM_BXCR_SDSZ_64; | |
1306 | break; | |
1307 | case 0x20: | |
1308 | cr |= SDRAM_BXCR_SDSZ_128; | |
1309 | break; | |
1310 | case 0x40: | |
1311 | cr |= SDRAM_BXCR_SDSZ_256; | |
1312 | break; | |
1313 | case 0x80: | |
1314 | cr |= SDRAM_BXCR_SDSZ_512; | |
1315 | break; | |
1316 | default: | |
1317 | printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", | |
1318 | dimm_num); | |
1319 | printf("ERROR: Unsupported value for the banksize: %d.\n", | |
1320 | bank_size_id); | |
1321 | printf("Replace the DIMM module with a supported DIMM.\n\n"); | |
a5d71e29 | 1322 | spd_ddr_init_hang (); |
c157d8e2 SR |
1323 | } |
1324 | ||
1325 | switch (num_col_addr) { | |
1326 | case 0x08: | |
1327 | cr |= SDRAM_BXCR_SDAM_1; | |
1328 | break; | |
1329 | case 0x09: | |
1330 | cr |= SDRAM_BXCR_SDAM_2; | |
1331 | break; | |
1332 | case 0x0A: | |
1333 | cr |= SDRAM_BXCR_SDAM_3; | |
1334 | break; | |
1335 | case 0x0B: | |
1336 | cr |= SDRAM_BXCR_SDAM_4; | |
1337 | break; | |
1338 | default: | |
1339 | printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", | |
1340 | dimm_num); | |
1341 | printf("ERROR: Unsupported value for number of " | |
1342 | "column addresses: %d.\n", num_col_addr); | |
1343 | printf("Replace the DIMM module with a supported DIMM.\n\n"); | |
a5d71e29 | 1344 | spd_ddr_init_hang (); |
c157d8e2 SR |
1345 | } |
1346 | ||
1347 | /* | |
1348 | * enable the bank | |
1349 | */ | |
1350 | cr |= SDRAM_BXCR_SDBE; | |
1351 | ||
1636d1c8 | 1352 | for (i = 0; i < num_banks; i++) { |
d2d43276 SR |
1353 | bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = |
1354 | (4 << 20) * bank_size_id; | |
1355 | bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; | |
1356 | debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n", | |
1357 | dimm_num, i, ctrl_bank_num[dimm_num]+i, | |
1358 | bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes); | |
1636d1c8 | 1359 | } |
8bde7f77 | 1360 | } |
8bde7f77 | 1361 | } |
fe8c2806 | 1362 | |
fd49bf02 SR |
1363 | /* Initialize sort tables */ |
1364 | for (i = 0; i < MAXBXCR; i++) { | |
1365 | sorted_bank_num[i] = i; | |
1366 | sorted_bank_size[i] = bank_parms[i].bank_size_bytes; | |
1367 | } | |
1368 | ||
1369 | for (i = 0; i < MAXBXCR-1; i++) { | |
1370 | largest_size = sorted_bank_size[i]; | |
1371 | largest_size_index = 255; | |
1372 | ||
1373 | /* Find the largest remaining value */ | |
1374 | for (j = i + 1; j < MAXBXCR; j++) { | |
1375 | if (sorted_bank_size[j] > largest_size) { | |
1376 | /* Save largest remaining value and its index */ | |
1377 | largest_size = sorted_bank_size[j]; | |
1378 | largest_size_index = j; | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | if (largest_size_index != 255) { | |
1383 | /* Swap the current and largest values */ | |
1384 | current_size_index = sorted_bank_num[largest_size_index]; | |
1385 | sorted_bank_size[largest_size_index] = sorted_bank_size[i]; | |
1386 | sorted_bank_size[i] = largest_size; | |
1387 | sorted_bank_num[largest_size_index] = sorted_bank_num[i]; | |
1388 | sorted_bank_num[i] = current_size_index; | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | /* Set the SDRAM0_BxCR regs thanks to sort tables */ | |
1393 | for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { | |
1394 | if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { | |
1395 | mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); | |
1396 | temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | | |
1397 | SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); | |
1398 | temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | | |
1399 | bank_parms[sorted_bank_num[bx_cr_num]].cr; | |
1400 | mtdcr(memcfgd, temp); | |
1401 | bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; | |
d2d43276 | 1402 | debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp); |
fd49bf02 SR |
1403 | } |
1404 | } | |
1405 | ||
c157d8e2 | 1406 | return(bank_base_addr); |
fe8c2806 WD |
1407 | } |
1408 | ||
d2d43276 SR |
1409 | #ifdef CONFIG_DDR_ECC |
1410 | static void program_ecc(unsigned long num_bytes) | |
fe8c2806 | 1411 | { |
c157d8e2 SR |
1412 | unsigned long bank_base_addr; |
1413 | unsigned long current_address; | |
1414 | unsigned long end_address; | |
1415 | unsigned long address_increment; | |
1416 | unsigned long cfg0; | |
8bde7f77 | 1417 | |
c157d8e2 SR |
1418 | /* |
1419 | * get Memory Controller Options 0 data | |
1420 | */ | |
1421 | mfsdram(mem_cfg0, cfg0); | |
8bde7f77 | 1422 | |
c157d8e2 SR |
1423 | /* |
1424 | * reset the bank_base address | |
1425 | */ | |
1426 | bank_base_addr = CFG_SDRAM_BASE; | |
1427 | ||
1428 | if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { | |
d2d43276 | 1429 | mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN); |
c157d8e2 | 1430 | |
d2d43276 | 1431 | if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) |
c157d8e2 | 1432 | address_increment = 4; |
d2d43276 | 1433 | else |
c157d8e2 | 1434 | address_increment = 8; |
c157d8e2 SR |
1435 | |
1436 | current_address = (unsigned long)(bank_base_addr); | |
1437 | end_address = (unsigned long)(bank_base_addr) + num_bytes; | |
8bde7f77 | 1438 | |
c157d8e2 SR |
1439 | while (current_address < end_address) { |
1440 | *((unsigned long*)current_address) = 0x00000000; | |
1441 | current_address += address_increment; | |
1442 | } | |
1443 | ||
1444 | mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | | |
1445 | SDRAM_CFG0_MCHK_CHK); | |
1446 | } | |
fe8c2806 | 1447 | } |
d2d43276 | 1448 | #endif /* CONFIG_DDR_ECC */ |
fe8c2806 | 1449 | #endif /* CONFIG_SPD_EEPROM */ |