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ba56f625 WD |
1 | /*-----------------------------------------------------------------------------+ |
2 | * | |
265817c7 WD |
3 | * This source code has been made available to you by IBM on an AS-IS |
4 | * basis. Anyone receiving this source is licensed under IBM | |
5 | * copyrights to use it in any way he or she deems fit, including | |
6 | * copying it, modifying it, compiling it, and redistributing it either | |
7 | * with or without modifications. No license under IBM patents or | |
8 | * patent applications is to be implied by the copyright license. | |
ba56f625 | 9 | * |
265817c7 WD |
10 | * Any user of this software should understand that IBM cannot provide |
11 | * technical support for this software and will not be responsible for | |
12 | * any consequences resulting from the use of this software. | |
ba56f625 | 13 | * |
265817c7 WD |
14 | * Any person who transfers this source code or any derivative work |
15 | * must include the IBM copyright notice, this paragraph, and the | |
16 | * preceding two paragraphs in the transferred software. | |
ba56f625 | 17 | * |
265817c7 WD |
18 | * COPYRIGHT I B M CORPORATION 1995 |
19 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
ba56f625 WD |
20 | *-----------------------------------------------------------------------------*/ |
21 | /*-----------------------------------------------------------------------------+ | |
22 | * | |
265817c7 | 23 | * File Name: enetemac.c |
ba56f625 | 24 | * |
265817c7 | 25 | * Function: Device driver for the ethernet EMAC3 macro on the 405GP. |
ba56f625 | 26 | * |
265817c7 | 27 | * Author: Mark Wisner |
ba56f625 WD |
28 | * |
29 | * Change Activity- | |
30 | * | |
265817c7 WD |
31 | * Date Description of Change BY |
32 | * --------- --------------------- --- | |
33 | * 05-May-99 Created MKW | |
34 | * 27-Jun-99 Clean up JWB | |
35 | * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW | |
36 | * 29-Jul-99 Added Full duplex support MKW | |
37 | * 06-Aug-99 Changed names for Mal CR reg MKW | |
38 | * 23-Aug-99 Turned off SYE when running at 10Mbs MKW | |
39 | * 24-Aug-99 Marked descriptor empty after call_xlc MKW | |
40 | * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG | |
41 | * to avoid chaining maximum sized packets. Push starting | |
42 | * RX descriptor address up to the next cache line boundary. | |
43 | * 16-Jan-00 Added support for booting with IP of 0x0 MKW | |
44 | * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the | |
45 | * EMAC_RXM register. JWB | |
46 | * 12-Mar-01 anne-sophie.harnois@nextream.fr | |
47 | * - Variables are compatible with those already defined in | |
48 | * include/net.h | |
49 | * - Receive buffer descriptor ring is used to send buffers | |
50 | * to the user | |
51 | * - Info print about send/received/handled packet number if | |
52 | * INFO_405_ENET is set | |
53 | * 17-Apr-01 stefan.roese@esd-electronics.com | |
54 | * - MAL reset in "eth_halt" included | |
55 | * - Enet speed and duplex output now in one line | |
56 | * 08-May-01 stefan.roese@esd-electronics.com | |
57 | * - MAL error handling added (eth_init called again) | |
58 | * 13-Nov-01 stefan.roese@esd-electronics.com | |
59 | * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex | |
60 | * 04-Jan-02 stefan.roese@esd-electronics.com | |
61 | * - Wait for PHY auto negotiation to complete added | |
62 | * 06-Feb-02 stefan.roese@esd-electronics.com | |
63 | * - Bug fixed in waiting for auto negotiation to complete | |
64 | * 26-Feb-02 stefan.roese@esd-electronics.com | |
65 | * - rx and tx buffer descriptors now allocated (no fixed address | |
66 | * used anymore) | |
67 | * 17-Jun-02 stefan.roese@esd-electronics.com | |
68 | * - MAL error debug printf 'M' removed (rx de interrupt may | |
69 | * occur upon many incoming packets with only 4 rx buffers). | |
ba56f625 | 70 | *-----------------------------------------------------------------------------* |
265817c7 WD |
71 | * 17-Nov-03 travis.sawyer@sandburst.com |
72 | * - ported from 405gp_enet.c to utilized upto 4 EMAC ports | |
73 | * in the 440GX. This port should work with the 440GP | |
74 | * (2 EMACs) also | |
75 | * 15-Aug-05 sr@denx.de | |
76 | * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c | |
77 | now handling all 4xx cpu's. | |
ba56f625 WD |
78 | *-----------------------------------------------------------------------------*/ |
79 | ||
80 | #include <config.h> | |
ba56f625 WD |
81 | #include <common.h> |
82 | #include <net.h> | |
83 | #include <asm/processor.h> | |
ba56f625 | 84 | #include <commproc.h> |
d6c61aab SR |
85 | #include <ppc4xx.h> |
86 | #include <ppc4xx_enet.h> | |
ba56f625 WD |
87 | #include <405_mal.h> |
88 | #include <miiphy.h> | |
89 | #include <malloc.h> | |
90 | #include "vecnum.h" | |
91 | ||
d6c61aab | 92 | /* |
0c8721a4 | 93 | * Only compile for platform with AMCC EMAC ethernet controller and |
d6c61aab SR |
94 | * network support enabled. |
95 | * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! | |
96 | */ | |
97 | #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) | |
98 | ||
99 | #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) | |
100 | #error "CONFIG_MII has to be defined!" | |
101 | #endif | |
ba56f625 | 102 | |
1e25f957 SR |
103 | #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI) |
104 | #error "CONFIG_NET_MULTI has to be defined for NetConsole" | |
105 | #endif | |
106 | ||
265817c7 | 107 | #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ |
ba56f625 WD |
108 | #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ |
109 | ||
ba56f625 WD |
110 | /* Ethernet Transmit and Receive Buffers */ |
111 | /* AS.HARNOIS | |
112 | * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from | |
113 | * PKTSIZE and PKTSIZE_ALIGN (include/net.h) | |
114 | */ | |
265817c7 | 115 | #define ENET_MAX_MTU PKTSIZE |
ba56f625 WD |
116 | #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN |
117 | ||
ba56f625 WD |
118 | /*-----------------------------------------------------------------------------+ |
119 | * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal | |
120 | * Interrupt Controller). | |
121 | *-----------------------------------------------------------------------------*/ | |
122 | #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) | |
123 | #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) | |
124 | #define EMAC_UIC_DEF UIC_ENET | |
d6c61aab SR |
125 | #define EMAC_UIC_DEF1 UIC_ENET1 |
126 | #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET ) | |
ba56f625 | 127 | |
d6c61aab | 128 | #undef INFO_4XX_ENET |
ba56f625 | 129 | |
265817c7 WD |
130 | #define BI_PHYMODE_NONE 0 |
131 | #define BI_PHYMODE_ZMII 1 | |
3c74e32a WD |
132 | #define BI_PHYMODE_RGMII 2 |
133 | ||
d6c61aab | 134 | |
ba56f625 WD |
135 | /*-----------------------------------------------------------------------------+ |
136 | * Global variables. TX and RX descriptors and buffers. | |
137 | *-----------------------------------------------------------------------------*/ | |
138 | /* IER globals */ | |
139 | static uint32_t mal_ier; | |
140 | ||
d6c61aab | 141 | #if !defined(CONFIG_NET_MULTI) |
4f92ac36 | 142 | struct eth_device *emac0_dev = NULL; |
d6c61aab SR |
143 | #endif |
144 | ||
1e25f957 SR |
145 | /* |
146 | * Get count of EMAC devices (doesn't have to be the max. possible number | |
147 | * supported by the cpu) | |
148 | */ | |
149 | #if defined(CONFIG_HAS_ETH3) | |
150 | #define LAST_EMAC_NUM 4 | |
151 | #elif defined(CONFIG_HAS_ETH2) | |
152 | #define LAST_EMAC_NUM 3 | |
153 | #elif defined(CONFIG_HAS_ETH1) | |
154 | #define LAST_EMAC_NUM 2 | |
155 | #else | |
156 | #define LAST_EMAC_NUM 1 | |
157 | #endif | |
d6c61aab | 158 | |
ba56f625 WD |
159 | /*-----------------------------------------------------------------------------+ |
160 | * Prototypes and externals. | |
161 | *-----------------------------------------------------------------------------*/ | |
162 | static void enet_rcv (struct eth_device *dev, unsigned long malisr); | |
163 | ||
164 | int enetInt (struct eth_device *dev); | |
165 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
166 | unsigned long uic, unsigned long maldef, | |
167 | unsigned long mal_errr); | |
168 | static void emac_err (struct eth_device *dev, unsigned long isr); | |
169 | ||
63ff004c MB |
170 | extern int phy_setup_aneg (char *devname, unsigned char addr); |
171 | extern int emac4xx_miiphy_read (char *devname, unsigned char addr, | |
172 | unsigned char reg, unsigned short *value); | |
173 | extern int emac4xx_miiphy_write (char *devname, unsigned char addr, | |
174 | unsigned char reg, unsigned short value); | |
d6c61aab | 175 | |
ba56f625 | 176 | /*-----------------------------------------------------------------------------+ |
d6c61aab | 177 | | ppc_4xx_eth_halt |
ba56f625 | 178 | | Disable MAL channel, and EMACn |
ba56f625 | 179 | +-----------------------------------------------------------------------------*/ |
d6c61aab | 180 | static void ppc_4xx_eth_halt (struct eth_device *dev) |
ba56f625 | 181 | { |
d6c61aab | 182 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
183 | uint32_t failsafe = 10000; |
184 | ||
185 | out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ | |
186 | ||
187 | /* 1st reset MAL channel */ | |
188 | /* Note: writing a 0 to a channel has no effect */ | |
d6c61aab SR |
189 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
190 | mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); | |
191 | #else | |
ba56f625 | 192 | mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
d6c61aab | 193 | #endif |
ba56f625 WD |
194 | mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
195 | ||
196 | /* wait for reset */ | |
d6c61aab | 197 | while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { |
ba56f625 WD |
198 | udelay (1000); /* Delay 1 MS so as not to hammer the register */ |
199 | failsafe--; | |
200 | if (failsafe == 0) | |
201 | break; | |
ba56f625 WD |
202 | } |
203 | ||
204 | /* EMAC RESET */ | |
205 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); | |
206 | ||
a93316c5 | 207 | #ifndef CONFIG_NETCONSOLE |
c157d8e2 | 208 | hw_p->print_speed = 1; /* print speed message again next time */ |
a93316c5 | 209 | #endif |
c157d8e2 | 210 | |
ba56f625 WD |
211 | return; |
212 | } | |
213 | ||
846b0dd2 | 214 | #if defined (CONFIG_440GX) |
d6c61aab | 215 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
855a496f WD |
216 | { |
217 | unsigned long pfc1; | |
218 | unsigned long zmiifer; | |
219 | unsigned long rmiifer; | |
220 | ||
221 | mfsdr(sdr_pfc1, pfc1); | |
222 | pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); | |
223 | ||
224 | zmiifer = 0; | |
225 | rmiifer = 0; | |
226 | ||
227 | switch (pfc1) { | |
228 | case 1: | |
229 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
230 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
231 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
232 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
233 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
234 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
235 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
236 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
237 | break; | |
238 | case 2: | |
239 | zmiifer = ZMII_FER_SMII << ZMII_FER_V(0); | |
240 | zmiifer = ZMII_FER_SMII << ZMII_FER_V(1); | |
241 | zmiifer = ZMII_FER_SMII << ZMII_FER_V(2); | |
242 | zmiifer = ZMII_FER_SMII << ZMII_FER_V(3); | |
243 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
244 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
245 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
246 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
247 | break; | |
248 | case 3: | |
249 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
250 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
251 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
252 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
253 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
254 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
255 | break; | |
256 | case 4: | |
257 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
258 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
259 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); | |
260 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); | |
261 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
262 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
263 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
264 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
265 | break; | |
266 | case 5: | |
267 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
268 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
269 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); | |
270 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
271 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
272 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
273 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
274 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
275 | break; | |
276 | case 6: | |
277 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
278 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
279 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
855a496f WD |
280 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
281 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
282 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
855a496f WD |
283 | break; |
284 | case 0: | |
285 | default: | |
286 | zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); | |
287 | rmiifer = 0x0; | |
288 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
289 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
290 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
291 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
292 | break; | |
293 | } | |
294 | ||
295 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
296 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); | |
297 | ||
298 | out32 (ZMII_FER, zmiifer); | |
299 | out32 (RGMII_FER, rmiifer); | |
300 | ||
301 | return ((int)pfc1); | |
302 | ||
303 | } | |
304 | #endif | |
305 | ||
d6c61aab | 306 | static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
ba56f625 | 307 | { |
b79316f2 | 308 | int i, j; |
d6c61aab | 309 | unsigned long reg = 0; |
ba56f625 WD |
310 | unsigned long msr; |
311 | unsigned long speed; | |
312 | unsigned long duplex; | |
313 | unsigned long failsafe; | |
314 | unsigned mode_reg; | |
315 | unsigned short devnum; | |
316 | unsigned short reg_short; | |
846b0dd2 | 317 | #if defined(CONFIG_440GX) |
d6c61aab | 318 | sys_info_t sysinfo; |
855a496f | 319 | int ethgroup; |
c157d8e2 | 320 | #endif |
ba56f625 | 321 | |
d6c61aab | 322 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
323 | |
324 | /* before doing anything, figure out if we have a MAC address */ | |
325 | /* if not, bail */ | |
4f92ac36 SR |
326 | if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { |
327 | printf("ERROR: ethaddr not set!\n"); | |
ba56f625 | 328 | return -1; |
4f92ac36 | 329 | } |
ba56f625 | 330 | |
d6c61aab | 331 | #if defined(CONFIG_440GX) |
ba56f625 WD |
332 | /* Need to get the OPB frequency so we can access the PHY */ |
333 | get_sys_info (&sysinfo); | |
d6c61aab | 334 | #endif |
ba56f625 | 335 | |
ba56f625 WD |
336 | msr = mfmsr (); |
337 | mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ | |
338 | ||
339 | devnum = hw_p->devnum; | |
340 | ||
d6c61aab | 341 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
342 | /* AS.HARNOIS |
343 | * We should have : | |
265817c7 | 344 | * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX |
ba56f625 WD |
345 | * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it |
346 | * is possible that new packets (without relationship with | |
347 | * current transfer) have got the time to arrived before | |
348 | * netloop calls eth_halt | |
349 | */ | |
350 | printf ("About preceeding transfer (eth%d):\n" | |
351 | "- Sent packet number %d\n" | |
352 | "- Received packet number %d\n" | |
353 | "- Handled packet number %d\n", | |
354 | hw_p->devnum, | |
355 | hw_p->stats.pkts_tx, | |
356 | hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); | |
357 | ||
358 | hw_p->stats.pkts_tx = 0; | |
359 | hw_p->stats.pkts_rx = 0; | |
360 | hw_p->stats.pkts_handled = 0; | |
361 | #endif | |
362 | ||
265817c7 WD |
363 | hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ |
364 | hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ | |
ba56f625 WD |
365 | |
366 | hw_p->rx_slot = 0; /* MAL Receive Slot */ | |
367 | hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ | |
368 | hw_p->rx_u_index = 0; /* Receive User Queue Index */ | |
369 | ||
370 | hw_p->tx_slot = 0; /* MAL Transmit Slot */ | |
371 | hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ | |
372 | hw_p->tx_u_index = 0; /* Transmit User Queue Index */ | |
373 | ||
d6c61aab | 374 | #if defined(CONFIG_440) |
ba56f625 WD |
375 | /* set RMII mode */ |
376 | /* NOTE: 440GX spec states that mode is mutually exclusive */ | |
377 | /* NOTE: Therefore, disable all other EMACS, since we handle */ | |
378 | /* NOTE: only one emac at a time */ | |
379 | reg = 0; | |
380 | out32 (ZMII_FER, 0); | |
381 | udelay (100); | |
ba56f625 | 382 | |
846b0dd2 | 383 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
265817c7 | 384 | out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
846b0dd2 | 385 | #elif defined(CONFIG_440GX) |
d6c61aab | 386 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); |
4a3cd9e6 SR |
387 | #elif defined(CONFIG_440GP) |
388 | /* set RMII mode */ | |
389 | out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); | |
0e6d798c WD |
390 | #else |
391 | if ((devnum == 0) || (devnum == 1)) { | |
392 | out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); | |
393 | } | |
394 | else { /* ((devnum == 2) || (devnum == 3)) */ | |
395 | out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); | |
ba56f625 WD |
396 | out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | |
397 | (RGMII_FER_RGMII << RGMII_FER_V (3)))); | |
0e6d798c WD |
398 | } |
399 | #endif | |
c57c7980 | 400 | |
0e6d798c | 401 | out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); |
d6c61aab SR |
402 | #endif /* defined(CONFIG_440) */ |
403 | ||
0e6d798c WD |
404 | __asm__ volatile ("eieio"); |
405 | ||
406 | /* reset emac so we have access to the phy */ | |
407 | ||
408 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); | |
ba56f625 WD |
409 | __asm__ volatile ("eieio"); |
410 | ||
411 | failsafe = 1000; | |
412 | while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { | |
413 | udelay (1000); | |
414 | failsafe--; | |
415 | } | |
416 | ||
846b0dd2 | 417 | #if defined(CONFIG_440GX) |
ba56f625 WD |
418 | /* Whack the M1 register */ |
419 | mode_reg = 0x0; | |
420 | mode_reg &= ~0x00000038; | |
421 | if (sysinfo.freqOPB <= 50000000); | |
422 | else if (sysinfo.freqOPB <= 66666667) | |
423 | mode_reg |= EMAC_M1_OBCI_66; | |
424 | else if (sysinfo.freqOPB <= 83333333) | |
425 | mode_reg |= EMAC_M1_OBCI_83; | |
426 | else if (sysinfo.freqOPB <= 100000000) | |
427 | mode_reg |= EMAC_M1_OBCI_100; | |
428 | else | |
429 | mode_reg |= EMAC_M1_OBCI_GT100; | |
430 | ||
431 | out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); | |
846b0dd2 | 432 | #endif /* defined(CONFIG_440GX) */ |
ba56f625 WD |
433 | |
434 | /* wait for PHY to complete auto negotiation */ | |
435 | reg_short = 0; | |
436 | #ifndef CONFIG_CS8952_PHY | |
437 | switch (devnum) { | |
438 | case 0: | |
439 | reg = CONFIG_PHY_ADDR; | |
440 | break; | |
d6c61aab | 441 | #if defined (CONFIG_PHY1_ADDR) |
ba56f625 WD |
442 | case 1: |
443 | reg = CONFIG_PHY1_ADDR; | |
444 | break; | |
d6c61aab | 445 | #endif |
846b0dd2 | 446 | #if defined (CONFIG_440GX) |
ba56f625 WD |
447 | case 2: |
448 | reg = CONFIG_PHY2_ADDR; | |
449 | break; | |
450 | case 3: | |
451 | reg = CONFIG_PHY3_ADDR; | |
452 | break; | |
453 | #endif | |
454 | default: | |
455 | reg = CONFIG_PHY_ADDR; | |
456 | break; | |
457 | } | |
458 | ||
3c74e32a WD |
459 | bis->bi_phynum[devnum] = reg; |
460 | ||
d6c61aab | 461 | #if defined(CONFIG_PHY_RESET) |
a06752e3 WD |
462 | /* |
463 | * Reset the phy, only if its the first time through | |
464 | * otherwise, just check the speeds & feeds | |
465 | */ | |
466 | if (hw_p->first_init == 0) { | |
63ff004c | 467 | miiphy_reset (dev->name, reg); |
ba56f625 | 468 | |
846b0dd2 | 469 | #if defined(CONFIG_440GX) |
0e6d798c | 470 | #if defined(CONFIG_CIS8201_PHY) |
fc1cfcdb | 471 | /* |
17f50f22 SR |
472 | * Cicada 8201 PHY needs to have an extended register whacked |
473 | * for RGMII mode. | |
fc1cfcdb | 474 | */ |
17f50f22 | 475 | if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) { |
b79316f2 | 476 | #if defined(CONFIG_CIS8201_SHORT_ETCH) |
63ff004c | 477 | miiphy_write (dev->name, reg, 23, 0x1300); |
b79316f2 | 478 | #else |
63ff004c | 479 | miiphy_write (dev->name, reg, 23, 0x1000); |
b79316f2 | 480 | #endif |
17f50f22 SR |
481 | /* |
482 | * Vitesse VSC8201/Cicada CIS8201 errata: | |
483 | * Interoperability problem with Intel 82547EI phys | |
484 | * This work around (provided by Vitesse) changes | |
485 | * the default timer convergence from 8ms to 12ms | |
486 | */ | |
63ff004c MB |
487 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); |
488 | miiphy_write (dev->name, reg, 0x08, 0x0200); | |
489 | miiphy_write (dev->name, reg, 0x1f, 0x52b5); | |
490 | miiphy_write (dev->name, reg, 0x02, 0x0004); | |
491 | miiphy_write (dev->name, reg, 0x01, 0x0671); | |
492 | miiphy_write (dev->name, reg, 0x00, 0x8fae); | |
493 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); | |
494 | miiphy_write (dev->name, reg, 0x08, 0x0000); | |
495 | miiphy_write (dev->name, reg, 0x1f, 0x0000); | |
17f50f22 SR |
496 | /* end Vitesse/Cicada errata */ |
497 | } | |
0e6d798c | 498 | #endif |
855a496f | 499 | #endif |
a06752e3 | 500 | /* Start/Restart autonegotiation */ |
63ff004c | 501 | phy_setup_aneg (dev->name, reg); |
a06752e3 WD |
502 | udelay (1000); |
503 | } | |
d6c61aab | 504 | #endif /* defined(CONFIG_PHY_RESET) */ |
ba56f625 | 505 | |
63ff004c | 506 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
507 | |
508 | /* | |
0e6d798c | 509 | * Wait if PHY is capable of autonegotiation and autonegotiation is not complete |
ba56f625 WD |
510 | */ |
511 | if ((reg_short & PHY_BMSR_AUTN_ABLE) | |
512 | && !(reg_short & PHY_BMSR_AUTN_COMP)) { | |
513 | puts ("Waiting for PHY auto negotiation to complete"); | |
514 | i = 0; | |
515 | while (!(reg_short & PHY_BMSR_AUTN_COMP)) { | |
516 | /* | |
517 | * Timeout reached ? | |
518 | */ | |
519 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
520 | puts (" TIMEOUT !\n"); | |
521 | break; | |
522 | } | |
523 | ||
524 | if ((i++ % 1000) == 0) { | |
525 | putc ('.'); | |
526 | } | |
527 | udelay (1000); /* 1 ms */ | |
63ff004c | 528 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
529 | |
530 | } | |
531 | puts (" done\n"); | |
532 | udelay (500000); /* another 500 ms (results in faster booting) */ | |
533 | } | |
d6c61aab SR |
534 | #endif /* #ifndef CONFIG_CS8952_PHY */ |
535 | ||
63ff004c MB |
536 | speed = miiphy_speed (dev->name, reg); |
537 | duplex = miiphy_duplex (dev->name, reg); | |
ba56f625 WD |
538 | |
539 | if (hw_p->print_speed) { | |
540 | hw_p->print_speed = 0; | |
541 | printf ("ENET Speed is %d Mbps - %s duplex connection\n", | |
542 | (int) speed, (duplex == HALF) ? "HALF" : "FULL"); | |
543 | } | |
544 | ||
d6c61aab | 545 | #if defined(CONFIG_440) |
846b0dd2 | 546 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
547 | mfsdr(sdr_mfr, reg); |
548 | if (speed == 100) { | |
549 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; | |
550 | } else { | |
551 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; | |
552 | } | |
553 | mtsdr(sdr_mfr, reg); | |
554 | #endif | |
c57c7980 | 555 | |
ba56f625 WD |
556 | /* Set ZMII/RGMII speed according to the phy link speed */ |
557 | reg = in32 (ZMII_SSR); | |
855a496f | 558 | if ( (speed == 100) || (speed == 1000) ) |
ba56f625 WD |
559 | out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); |
560 | else | |
c57c7980 | 561 | out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); |
ba56f625 WD |
562 | |
563 | if ((devnum == 2) || (devnum == 3)) { | |
564 | if (speed == 1000) | |
565 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); | |
566 | else if (speed == 100) | |
567 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); | |
568 | else | |
569 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); | |
570 | ||
571 | out32 (RGMII_SSR, reg); | |
572 | } | |
d6c61aab | 573 | #endif /* defined(CONFIG_440) */ |
ba56f625 WD |
574 | |
575 | /* set the Mal configuration reg */ | |
846b0dd2 | 576 | #if defined(CONFIG_440GX) |
17f50f22 SR |
577 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | |
578 | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); | |
579 | #else | |
580 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); | |
ba56f625 | 581 | /* Errata 1.12: MAL_1 -- Disable MAL bursting */ |
17f50f22 SR |
582 | if (get_pvr() == PVR_440GP_RB) { |
583 | mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); | |
584 | } | |
585 | #endif | |
ba56f625 WD |
586 | |
587 | /* Free "old" buffers */ | |
588 | if (hw_p->alloc_tx_buf) | |
589 | free (hw_p->alloc_tx_buf); | |
590 | if (hw_p->alloc_rx_buf) | |
591 | free (hw_p->alloc_rx_buf); | |
592 | ||
593 | /* | |
594 | * Malloc MAL buffer desciptors, make sure they are | |
595 | * aligned on cache line boundary size | |
596 | * (401/403/IOP480 = 16, 405 = 32) | |
597 | * and doesn't cross cache block boundaries. | |
598 | */ | |
599 | hw_p->alloc_tx_buf = | |
600 | (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) + | |
601 | ((2 * CFG_CACHELINE_SIZE) - 2)); | |
b79316f2 SR |
602 | if (NULL == hw_p->alloc_tx_buf) |
603 | return -1; | |
ba56f625 WD |
604 | if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) { |
605 | hw_p->tx = | |
606 | (mal_desc_t *) ((int) hw_p->alloc_tx_buf + | |
607 | CFG_CACHELINE_SIZE - | |
608 | ((int) hw_p-> | |
609 | alloc_tx_buf & CACHELINE_MASK)); | |
610 | } else { | |
611 | hw_p->tx = hw_p->alloc_tx_buf; | |
612 | } | |
613 | ||
614 | hw_p->alloc_rx_buf = | |
615 | (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) + | |
616 | ((2 * CFG_CACHELINE_SIZE) - 2)); | |
b79316f2 SR |
617 | if (NULL == hw_p->alloc_rx_buf) { |
618 | free(hw_p->alloc_tx_buf); | |
619 | hw_p->alloc_tx_buf = NULL; | |
620 | return -1; | |
621 | } | |
622 | ||
ba56f625 WD |
623 | if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) { |
624 | hw_p->rx = | |
625 | (mal_desc_t *) ((int) hw_p->alloc_rx_buf + | |
626 | CFG_CACHELINE_SIZE - | |
627 | ((int) hw_p-> | |
628 | alloc_rx_buf & CACHELINE_MASK)); | |
629 | } else { | |
630 | hw_p->rx = hw_p->alloc_rx_buf; | |
631 | } | |
632 | ||
633 | for (i = 0; i < NUM_TX_BUFF; i++) { | |
634 | hw_p->tx[i].ctrl = 0; | |
635 | hw_p->tx[i].data_len = 0; | |
b79316f2 | 636 | if (hw_p->first_init == 0) { |
ba56f625 WD |
637 | hw_p->txbuf_ptr = |
638 | (char *) malloc (ENET_MAX_MTU_ALIGNED); | |
b79316f2 SR |
639 | if (NULL == hw_p->txbuf_ptr) { |
640 | free(hw_p->alloc_rx_buf); | |
641 | free(hw_p->alloc_tx_buf); | |
642 | hw_p->alloc_rx_buf = NULL; | |
643 | hw_p->alloc_tx_buf = NULL; | |
644 | for(j = 0; j < i; j++) { | |
645 | free(hw_p->tx[i].data_ptr); | |
646 | hw_p->tx[i].data_ptr = NULL; | |
647 | } | |
648 | } | |
649 | } | |
ba56f625 WD |
650 | hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; |
651 | if ((NUM_TX_BUFF - 1) == i) | |
652 | hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; | |
653 | hw_p->tx_run[i] = -1; | |
654 | #if 0 | |
655 | printf ("TX_BUFF %d @ 0x%08lx\n", i, | |
656 | (ulong) hw_p->tx[i].data_ptr); | |
657 | #endif | |
658 | } | |
659 | ||
660 | for (i = 0; i < NUM_RX_BUFF; i++) { | |
661 | hw_p->rx[i].ctrl = 0; | |
662 | hw_p->rx[i].data_len = 0; | |
265817c7 | 663 | /* rx[i].data_ptr = (char *) &rx_buff[i]; */ |
ba56f625 WD |
664 | hw_p->rx[i].data_ptr = (char *) NetRxPackets[i]; |
665 | if ((NUM_RX_BUFF - 1) == i) | |
666 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; | |
667 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; | |
668 | hw_p->rx_ready[i] = -1; | |
669 | #if 0 | |
670 | printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); | |
671 | #endif | |
672 | } | |
673 | ||
674 | reg = 0x00000000; | |
675 | ||
676 | reg |= dev->enetaddr[0]; /* set high address */ | |
677 | reg = reg << 8; | |
678 | reg |= dev->enetaddr[1]; | |
679 | ||
680 | out32 (EMAC_IAH + hw_p->hw_addr, reg); | |
681 | ||
682 | reg = 0x00000000; | |
683 | reg |= dev->enetaddr[2]; /* set low address */ | |
684 | reg = reg << 8; | |
685 | reg |= dev->enetaddr[3]; | |
686 | reg = reg << 8; | |
687 | reg |= dev->enetaddr[4]; | |
688 | reg = reg << 8; | |
689 | reg |= dev->enetaddr[5]; | |
690 | ||
691 | out32 (EMAC_IAL + hw_p->hw_addr, reg); | |
692 | ||
693 | switch (devnum) { | |
694 | case 1: | |
695 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 696 | #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) |
c157d8e2 SR |
697 | mtdcr (maltxctp2r, hw_p->tx); |
698 | #else | |
ba56f625 | 699 | mtdcr (maltxctp1r, hw_p->tx); |
c157d8e2 | 700 | #endif |
d6c61aab | 701 | #if defined(CONFIG_440) |
c157d8e2 | 702 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 703 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 704 | #endif |
ba56f625 WD |
705 | mtdcr (malrxctp1r, hw_p->rx); |
706 | /* set RX buffer size */ | |
707 | mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); | |
708 | break; | |
846b0dd2 | 709 | #if defined (CONFIG_440GX) |
ba56f625 WD |
710 | case 2: |
711 | /* setup MAL tx & rx channel pointers */ | |
712 | mtdcr (maltxbattr, 0x0); | |
ba56f625 | 713 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 714 | mtdcr (maltxctp2r, hw_p->tx); |
ba56f625 WD |
715 | mtdcr (malrxctp2r, hw_p->rx); |
716 | /* set RX buffer size */ | |
717 | mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); | |
718 | break; | |
719 | case 3: | |
720 | /* setup MAL tx & rx channel pointers */ | |
721 | mtdcr (maltxbattr, 0x0); | |
722 | mtdcr (maltxctp3r, hw_p->tx); | |
723 | mtdcr (malrxbattr, 0x0); | |
724 | mtdcr (malrxctp3r, hw_p->rx); | |
725 | /* set RX buffer size */ | |
726 | mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); | |
727 | break; | |
c57c7980 | 728 | #endif /* CONFIG_440GX */ |
ba56f625 WD |
729 | case 0: |
730 | default: | |
731 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 732 | #if defined(CONFIG_440) |
ba56f625 | 733 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 734 | mtdcr (malrxbattr, 0x0); |
d6c61aab SR |
735 | #endif |
736 | mtdcr (maltxctp0r, hw_p->tx); | |
ba56f625 WD |
737 | mtdcr (malrxctp0r, hw_p->rx); |
738 | /* set RX buffer size */ | |
739 | mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); | |
740 | break; | |
741 | } | |
742 | ||
743 | /* Enable MAL transmit and receive channels */ | |
d6c61aab | 744 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
745 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); |
746 | #else | |
ba56f625 | 747 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
c157d8e2 | 748 | #endif |
ba56f625 WD |
749 | mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
750 | ||
751 | /* set transmit enable & receive enable */ | |
752 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); | |
753 | ||
754 | /* set receive fifo to 4k and tx fifo to 2k */ | |
755 | mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); | |
756 | mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; | |
757 | ||
758 | /* set speed */ | |
855a496f WD |
759 | if (speed == _1000BASET) |
760 | mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; | |
761 | else if (speed == _100BASET) | |
ba56f625 WD |
762 | mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; |
763 | else | |
764 | mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ | |
765 | if (duplex == FULL) | |
766 | mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; | |
767 | ||
768 | out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); | |
769 | ||
770 | /* Enable broadcast and indvidual address */ | |
771 | /* TBS: enabling runts as some misbehaved nics will send runts */ | |
772 | out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); | |
773 | ||
774 | /* we probably need to set the tx mode1 reg? maybe at tx time */ | |
775 | ||
776 | /* set transmit request threshold register */ | |
777 | out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ | |
778 | ||
265817c7 | 779 | /* set receive low/high water mark register */ |
d6c61aab | 780 | #if defined(CONFIG_440) |
ba56f625 WD |
781 | /* 440GP has a 64 byte burst length */ |
782 | out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); | |
d6c61aab SR |
783 | #else |
784 | /* 405s have a 16 byte burst length */ | |
785 | out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); | |
786 | #endif /* defined(CONFIG_440) */ | |
ba56f625 WD |
787 | out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); |
788 | ||
789 | /* Set fifo limit entry in tx mode 0 */ | |
790 | out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); | |
791 | /* Frame gap set */ | |
792 | out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); | |
793 | ||
794 | /* Set EMAC IER */ | |
d6c61aab | 795 | hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; |
ba56f625 WD |
796 | if (speed == _100BASET) |
797 | hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; | |
798 | ||
799 | out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ | |
800 | out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); | |
801 | ||
802 | if (hw_p->first_init == 0) { | |
803 | /* | |
804 | * Connect interrupt service routines | |
805 | */ | |
ba56f625 WD |
806 | irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), |
807 | (interrupt_handler_t *) enetInt, dev); | |
808 | } | |
ba56f625 WD |
809 | |
810 | mtmsr (msr); /* enable interrupts again */ | |
811 | ||
812 | hw_p->bis = bis; | |
813 | hw_p->first_init = 1; | |
814 | ||
815 | return (1); | |
816 | } | |
817 | ||
818 | ||
d6c61aab | 819 | static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, |
ba56f625 WD |
820 | int len) |
821 | { | |
822 | struct enet_frame *ef_ptr; | |
823 | ulong time_start, time_now; | |
824 | unsigned long temp_txm0; | |
d6c61aab | 825 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
826 | |
827 | ef_ptr = (struct enet_frame *) ptr; | |
828 | ||
829 | /*-----------------------------------------------------------------------+ | |
830 | * Copy in our address into the frame. | |
831 | *-----------------------------------------------------------------------*/ | |
832 | (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); | |
833 | ||
834 | /*-----------------------------------------------------------------------+ | |
835 | * If frame is too long or too short, modify length. | |
836 | *-----------------------------------------------------------------------*/ | |
837 | /* TBS: where does the fragment go???? */ | |
838 | if (len > ENET_MAX_MTU) | |
839 | len = ENET_MAX_MTU; | |
840 | ||
841 | /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ | |
842 | memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); | |
843 | ||
844 | /*-----------------------------------------------------------------------+ | |
845 | * set TX Buffer busy, and send it | |
846 | *-----------------------------------------------------------------------*/ | |
847 | hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | | |
848 | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & | |
849 | ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); | |
850 | if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) | |
851 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; | |
852 | ||
853 | hw_p->tx[hw_p->tx_slot].data_len = (short) len; | |
854 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; | |
855 | ||
856 | __asm__ volatile ("eieio"); | |
857 | ||
858 | out32 (EMAC_TXM0 + hw_p->hw_addr, | |
859 | in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); | |
d6c61aab | 860 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
861 | hw_p->stats.pkts_tx++; |
862 | #endif | |
863 | ||
864 | /*-----------------------------------------------------------------------+ | |
865 | * poll unitl the packet is sent and then make sure it is OK | |
866 | *-----------------------------------------------------------------------*/ | |
867 | time_start = get_timer (0); | |
868 | while (1) { | |
869 | temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); | |
870 | /* loop until either TINT turns on or 3 seconds elapse */ | |
871 | if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { | |
872 | /* transmit is done, so now check for errors | |
873 | * If there is an error, an interrupt should | |
874 | * happen when we return | |
875 | */ | |
876 | time_now = get_timer (0); | |
877 | if ((time_now - time_start) > 3000) { | |
878 | return (-1); | |
879 | } | |
880 | } else { | |
881 | return (len); | |
882 | } | |
883 | } | |
884 | } | |
885 | ||
d6c61aab | 886 | #if defined (CONFIG_440) |
ba56f625 WD |
887 | |
888 | int enetInt (struct eth_device *dev) | |
889 | { | |
890 | int serviced; | |
891 | int rc = -1; /* default to not us */ | |
892 | unsigned long mal_isr; | |
893 | unsigned long emac_isr = 0; | |
894 | unsigned long mal_rx_eob; | |
895 | unsigned long my_uic0msr, my_uic1msr; | |
896 | ||
846b0dd2 | 897 | #if defined(CONFIG_440GX) |
ba56f625 WD |
898 | unsigned long my_uic2msr; |
899 | #endif | |
d6c61aab | 900 | EMAC_4XX_HW_PST hw_p; |
ba56f625 WD |
901 | |
902 | /* | |
903 | * Because the mal is generic, we need to get the current | |
904 | * eth device | |
905 | */ | |
d6c61aab SR |
906 | #if defined(CONFIG_NET_MULTI) |
907 | dev = eth_get_dev(); | |
908 | #else | |
909 | dev = emac0_dev; | |
910 | #endif | |
ba56f625 WD |
911 | |
912 | hw_p = dev->priv; | |
913 | ||
914 | ||
915 | /* enter loop that stays in interrupt code until nothing to service */ | |
916 | do { | |
917 | serviced = 0; | |
918 | ||
919 | my_uic0msr = mfdcr (uic0msr); | |
920 | my_uic1msr = mfdcr (uic1msr); | |
846b0dd2 | 921 | #if defined(CONFIG_440GX) |
ba56f625 WD |
922 | my_uic2msr = mfdcr (uic2msr); |
923 | #endif | |
924 | if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) | |
925 | && !(my_uic1msr & | |
926 | (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | | |
927 | UIC_MRDE))) { | |
928 | /* not for us */ | |
929 | return (rc); | |
930 | } | |
846b0dd2 | 931 | #if defined (CONFIG_440GX) |
ba56f625 WD |
932 | if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) |
933 | && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) { | |
934 | /* not for us */ | |
935 | return (rc); | |
936 | } | |
937 | #endif | |
938 | /* get and clear controller status interrupts */ | |
939 | /* look at Mal and EMAC interrupts */ | |
940 | if ((my_uic0msr & (UIC_MRE | UIC_MTE)) | |
941 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
942 | /* we have a MAL interrupt */ | |
943 | mal_isr = mfdcr (malesr); | |
944 | /* look for mal error */ | |
945 | if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { | |
946 | mal_err (dev, mal_isr, my_uic0msr, | |
947 | MAL_UIC_DEF, MAL_UIC_ERR); | |
948 | serviced = 1; | |
949 | rc = 0; | |
950 | } | |
951 | } | |
952 | ||
953 | /* port by port dispatch of emac interrupts */ | |
954 | if (hw_p->devnum == 0) { | |
955 | if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */ | |
956 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
957 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
958 | emac_err (dev, emac_isr); | |
959 | serviced = 1; | |
960 | rc = 0; | |
961 | } | |
962 | } | |
963 | if ((hw_p->emac_ier & emac_isr) | |
964 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
965 | mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */ | |
966 | mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ | |
967 | return (rc); /* we had errors so get out */ | |
968 | } | |
969 | } | |
970 | ||
971 | if (hw_p->devnum == 1) { | |
972 | if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */ | |
973 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
974 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
975 | emac_err (dev, emac_isr); | |
976 | serviced = 1; | |
977 | rc = 0; | |
978 | } | |
979 | } | |
980 | if ((hw_p->emac_ier & emac_isr) | |
981 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
982 | mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */ | |
983 | mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ | |
984 | return (rc); /* we had errors so get out */ | |
985 | } | |
986 | } | |
846b0dd2 | 987 | #if defined (CONFIG_440GX) |
ba56f625 WD |
988 | if (hw_p->devnum == 2) { |
989 | if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ | |
990 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
991 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
992 | emac_err (dev, emac_isr); | |
993 | serviced = 1; | |
994 | rc = 0; | |
995 | } | |
996 | } | |
997 | if ((hw_p->emac_ier & emac_isr) | |
998 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
999 | mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */ | |
1000 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ | |
1001 | mtdcr (uic2sr, UIC_ETH2); | |
1002 | return (rc); /* we had errors so get out */ | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | if (hw_p->devnum == 3) { | |
1007 | if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ | |
1008 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
1009 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1010 | emac_err (dev, emac_isr); | |
1011 | serviced = 1; | |
1012 | rc = 0; | |
1013 | } | |
1014 | } | |
1015 | if ((hw_p->emac_ier & emac_isr) | |
1016 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
1017 | mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */ | |
1018 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ | |
1019 | mtdcr (uic2sr, UIC_ETH3); | |
1020 | return (rc); /* we had errors so get out */ | |
1021 | } | |
1022 | } | |
846b0dd2 | 1023 | #endif /* CONFIG_440GX */ |
ba56f625 WD |
1024 | /* handle MAX TX EOB interrupt from a tx */ |
1025 | if (my_uic0msr & UIC_MTE) { | |
1026 | mal_rx_eob = mfdcr (maltxeobisr); | |
1027 | mtdcr (maltxeobisr, mal_rx_eob); | |
1028 | mtdcr (uic0sr, UIC_MTE); | |
1029 | } | |
1030 | /* handle MAL RX EOB interupt from a receive */ | |
fc1cfcdb | 1031 | /* check for EOB on valid channels */ |
ba56f625 WD |
1032 | if (my_uic0msr & UIC_MRE) { |
1033 | mal_rx_eob = mfdcr (malrxeobisr); | |
265817c7 | 1034 | if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ |
ba56f625 WD |
1035 | /* clear EOB |
1036 | mtdcr(malrxeobisr, mal_rx_eob); */ | |
1037 | enet_rcv (dev, emac_isr); | |
1038 | /* indicate that we serviced an interrupt */ | |
1039 | serviced = 1; | |
1040 | rc = 0; | |
1041 | } | |
1042 | } | |
1043 | mtdcr (uic0sr, UIC_MRE); /* Clear */ | |
1044 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ | |
1045 | switch (hw_p->devnum) { | |
1046 | case 0: | |
1047 | mtdcr (uic1sr, UIC_ETH0); | |
1048 | break; | |
1049 | case 1: | |
1050 | mtdcr (uic1sr, UIC_ETH1); | |
1051 | break; | |
846b0dd2 | 1052 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1053 | case 2: |
1054 | mtdcr (uic2sr, UIC_ETH2); | |
1055 | break; | |
1056 | case 3: | |
1057 | mtdcr (uic2sr, UIC_ETH3); | |
1058 | break; | |
846b0dd2 | 1059 | #endif /* CONFIG_440GX */ |
ba56f625 WD |
1060 | default: |
1061 | break; | |
1062 | } | |
1063 | } while (serviced); | |
1064 | ||
1065 | return (rc); | |
1066 | } | |
1067 | ||
d6c61aab SR |
1068 | #else /* CONFIG_440 */ |
1069 | ||
1070 | int enetInt (struct eth_device *dev) | |
1071 | { | |
1072 | int serviced; | |
1073 | int rc = -1; /* default to not us */ | |
1074 | unsigned long mal_isr; | |
1075 | unsigned long emac_isr = 0; | |
1076 | unsigned long mal_rx_eob; | |
1077 | unsigned long my_uicmsr; | |
1078 | ||
1079 | EMAC_4XX_HW_PST hw_p; | |
1080 | ||
1081 | /* | |
1082 | * Because the mal is generic, we need to get the current | |
1083 | * eth device | |
1084 | */ | |
1085 | #if defined(CONFIG_NET_MULTI) | |
1086 | dev = eth_get_dev(); | |
1087 | #else | |
1088 | dev = emac0_dev; | |
1089 | #endif | |
1090 | ||
1091 | hw_p = dev->priv; | |
1092 | ||
1093 | /* enter loop that stays in interrupt code until nothing to service */ | |
1094 | do { | |
1095 | serviced = 0; | |
1096 | ||
1097 | my_uicmsr = mfdcr (uicmsr); | |
1098 | ||
1099 | if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */ | |
1100 | return (rc); | |
1101 | } | |
1102 | /* get and clear controller status interrupts */ | |
1103 | /* look at Mal and EMAC interrupts */ | |
1104 | if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */ | |
1105 | mal_isr = mfdcr (malesr); | |
1106 | /* look for mal error */ | |
1107 | if ((my_uicmsr & MAL_UIC_ERR) != 0) { | |
1108 | mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR); | |
1109 | serviced = 1; | |
1110 | rc = 0; | |
1111 | } | |
1112 | } | |
1113 | ||
1114 | /* port by port dispatch of emac interrupts */ | |
1115 | ||
1116 | if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ | |
1117 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
1118 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1119 | emac_err (dev, emac_isr); | |
1120 | serviced = 1; | |
1121 | rc = 0; | |
1122 | } | |
1123 | } | |
1124 | if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) { | |
1125 | mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */ | |
1126 | return (rc); /* we had errors so get out */ | |
1127 | } | |
1128 | ||
1129 | /* handle MAX TX EOB interrupt from a tx */ | |
1130 | if (my_uicmsr & UIC_MAL_TXEOB) { | |
1131 | mal_rx_eob = mfdcr (maltxeobisr); | |
1132 | mtdcr (maltxeobisr, mal_rx_eob); | |
1133 | mtdcr (uicsr, UIC_MAL_TXEOB); | |
1134 | } | |
1135 | /* handle MAL RX EOB interupt from a receive */ | |
1136 | /* check for EOB on valid channels */ | |
1137 | if (my_uicmsr & UIC_MAL_RXEOB) | |
1138 | { | |
1139 | mal_rx_eob = mfdcr (malrxeobisr); | |
265817c7 | 1140 | if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ |
d6c61aab SR |
1141 | /* clear EOB |
1142 | mtdcr(malrxeobisr, mal_rx_eob); */ | |
1143 | enet_rcv (dev, emac_isr); | |
1144 | /* indicate that we serviced an interrupt */ | |
1145 | serviced = 1; | |
1146 | rc = 0; | |
1147 | } | |
1148 | } | |
1149 | mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ | |
1150 | } | |
1151 | while (serviced); | |
1152 | ||
1153 | return (rc); | |
1154 | } | |
1155 | ||
1156 | #endif /* CONFIG_440 */ | |
1157 | ||
ba56f625 WD |
1158 | /*-----------------------------------------------------------------------------+ |
1159 | * MAL Error Routine | |
1160 | *-----------------------------------------------------------------------------*/ | |
1161 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
1162 | unsigned long uic, unsigned long maldef, | |
1163 | unsigned long mal_errr) | |
1164 | { | |
d6c61aab | 1165 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1166 | |
1167 | mtdcr (malesr, isr); /* clear interrupt */ | |
1168 | ||
1169 | /* clear DE interrupt */ | |
1170 | mtdcr (maltxdeir, 0xC0000000); | |
1171 | mtdcr (malrxdeir, 0x80000000); | |
1172 | ||
d6c61aab | 1173 | #ifdef INFO_4XX_ENET |
265817c7 | 1174 | printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); |
ba56f625 WD |
1175 | #endif |
1176 | ||
1177 | eth_init (hw_p->bis); /* start again... */ | |
1178 | } | |
1179 | ||
1180 | /*-----------------------------------------------------------------------------+ | |
1181 | * EMAC Error Routine | |
1182 | *-----------------------------------------------------------------------------*/ | |
1183 | static void emac_err (struct eth_device *dev, unsigned long isr) | |
1184 | { | |
d6c61aab | 1185 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1186 | |
1187 | printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); | |
1188 | out32 (EMAC_ISR + hw_p->hw_addr, isr); | |
1189 | } | |
1190 | ||
1191 | /*-----------------------------------------------------------------------------+ | |
1192 | * enet_rcv() handles the ethernet receive data | |
1193 | *-----------------------------------------------------------------------------*/ | |
1194 | static void enet_rcv (struct eth_device *dev, unsigned long malisr) | |
1195 | { | |
1196 | struct enet_frame *ef_ptr; | |
1197 | unsigned long data_len; | |
1198 | unsigned long rx_eob_isr; | |
d6c61aab | 1199 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1200 | |
1201 | int handled = 0; | |
1202 | int i; | |
1203 | int loop_count = 0; | |
1204 | ||
1205 | rx_eob_isr = mfdcr (malrxeobisr); | |
1206 | if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) { | |
1207 | /* clear EOB */ | |
1208 | mtdcr (malrxeobisr, rx_eob_isr); | |
1209 | ||
1210 | /* EMAC RX done */ | |
1211 | while (1) { /* do all */ | |
1212 | i = hw_p->rx_slot; | |
1213 | ||
1214 | if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) | |
1215 | || (loop_count >= NUM_RX_BUFF)) | |
1216 | break; | |
1217 | loop_count++; | |
1218 | hw_p->rx_slot++; | |
1219 | if (NUM_RX_BUFF == hw_p->rx_slot) | |
1220 | hw_p->rx_slot = 0; | |
1221 | handled++; | |
1222 | data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */ | |
1223 | if (data_len) { | |
1224 | if (data_len > ENET_MAX_MTU) /* Check len */ | |
1225 | data_len = 0; | |
1226 | else { | |
1227 | if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ | |
1228 | data_len = 0; | |
1229 | hw_p->stats.rx_err_log[hw_p-> | |
1230 | rx_err_index] | |
1231 | = hw_p->rx[i].ctrl; | |
1232 | hw_p->rx_err_index++; | |
1233 | if (hw_p->rx_err_index == | |
1234 | MAX_ERR_LOG) | |
1235 | hw_p->rx_err_index = | |
1236 | 0; | |
fc1cfcdb | 1237 | } /* emac_erros */ |
ba56f625 | 1238 | } /* data_len < max mtu */ |
fc1cfcdb | 1239 | } /* if data_len */ |
ba56f625 WD |
1240 | if (!data_len) { /* no data */ |
1241 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ | |
1242 | ||
1243 | hw_p->stats.data_len_err++; /* Error at Rx */ | |
1244 | } | |
1245 | ||
1246 | /* !data_len */ | |
1247 | /* AS.HARNOIS */ | |
1248 | /* Check if user has already eaten buffer */ | |
1249 | /* if not => ERROR */ | |
1250 | else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { | |
1251 | if (hw_p->is_receiving) | |
1252 | printf ("ERROR : Receive buffers are full!\n"); | |
1253 | break; | |
1254 | } else { | |
1255 | hw_p->stats.rx_frames++; | |
1256 | hw_p->stats.rx += data_len; | |
1257 | ef_ptr = (struct enet_frame *) hw_p->rx[i]. | |
1258 | data_ptr; | |
d6c61aab | 1259 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1260 | hw_p->stats.pkts_rx++; |
1261 | #endif | |
1262 | /* AS.HARNOIS | |
1263 | * use ring buffer | |
1264 | */ | |
1265 | hw_p->rx_ready[hw_p->rx_i_index] = i; | |
1266 | hw_p->rx_i_index++; | |
1267 | if (NUM_RX_BUFF == hw_p->rx_i_index) | |
1268 | hw_p->rx_i_index = 0; | |
1269 | ||
ba56f625 WD |
1270 | /* AS.HARNOIS |
1271 | * free receive buffer only when | |
1272 | * buffer has been handled (eth_rx) | |
1273 | rx[i].ctrl |= MAL_RX_CTRL_EMPTY; | |
1274 | */ | |
1275 | } /* if data_len */ | |
1276 | } /* while */ | |
1277 | } /* if EMACK_RXCHL */ | |
1278 | } | |
1279 | ||
1280 | ||
d6c61aab | 1281 | static int ppc_4xx_eth_rx (struct eth_device *dev) |
ba56f625 WD |
1282 | { |
1283 | int length; | |
1284 | int user_index; | |
1285 | unsigned long msr; | |
d6c61aab | 1286 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 1287 | |
265817c7 | 1288 | hw_p->is_receiving = 1; /* tell driver */ |
ba56f625 WD |
1289 | |
1290 | for (;;) { | |
1291 | /* AS.HARNOIS | |
1292 | * use ring buffer and | |
1293 | * get index from rx buffer desciptor queue | |
1294 | */ | |
1295 | user_index = hw_p->rx_ready[hw_p->rx_u_index]; | |
1296 | if (user_index == -1) { | |
1297 | length = -1; | |
1298 | break; /* nothing received - leave for() loop */ | |
1299 | } | |
1300 | ||
1301 | msr = mfmsr (); | |
1302 | mtmsr (msr & ~(MSR_EE)); | |
1303 | ||
1304 | length = hw_p->rx[user_index].data_len; | |
1305 | ||
1306 | /* Pass the packet up to the protocol layers. */ | |
265817c7 WD |
1307 | /* NetReceive(NetRxPackets[rxIdx], length - 4); */ |
1308 | /* NetReceive(NetRxPackets[i], length); */ | |
ba56f625 WD |
1309 | NetReceive (NetRxPackets[user_index], length - 4); |
1310 | /* Free Recv Buffer */ | |
1311 | hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; | |
1312 | /* Free rx buffer descriptor queue */ | |
1313 | hw_p->rx_ready[hw_p->rx_u_index] = -1; | |
1314 | hw_p->rx_u_index++; | |
1315 | if (NUM_RX_BUFF == hw_p->rx_u_index) | |
1316 | hw_p->rx_u_index = 0; | |
1317 | ||
d6c61aab | 1318 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1319 | hw_p->stats.pkts_handled++; |
1320 | #endif | |
1321 | ||
1322 | mtmsr (msr); /* Enable IRQ's */ | |
1323 | } | |
1324 | ||
265817c7 | 1325 | hw_p->is_receiving = 0; /* tell driver */ |
ba56f625 WD |
1326 | |
1327 | return length; | |
1328 | } | |
1329 | ||
d6c61aab | 1330 | int ppc_4xx_eth_initialize (bd_t * bis) |
ba56f625 WD |
1331 | { |
1332 | static int virgin = 0; | |
ba56f625 WD |
1333 | struct eth_device *dev; |
1334 | int eth_num = 0; | |
d6c61aab | 1335 | EMAC_4XX_HW_PST hw = NULL; |
ba56f625 | 1336 | |
846b0dd2 | 1337 | #if defined(CONFIG_440GX) |
c157d8e2 SR |
1338 | unsigned long pfc1; |
1339 | ||
ba56f625 WD |
1340 | mfsdr (sdr_pfc1, pfc1); |
1341 | pfc1 &= ~(0x01e00000); | |
1342 | pfc1 |= 0x01200000; | |
1343 | mtsdr (sdr_pfc1, pfc1); | |
c157d8e2 | 1344 | #endif |
3c74e32a WD |
1345 | /* set phy num and mode */ |
1346 | bis->bi_phynum[0] = CONFIG_PHY_ADDR; | |
c157d8e2 | 1347 | #if defined(CONFIG_PHY1_ADDR) |
3c74e32a | 1348 | bis->bi_phynum[1] = CONFIG_PHY1_ADDR; |
c157d8e2 | 1349 | #endif |
846b0dd2 | 1350 | #if defined(CONFIG_440GX) |
3c74e32a WD |
1351 | bis->bi_phynum[2] = CONFIG_PHY2_ADDR; |
1352 | bis->bi_phynum[3] = CONFIG_PHY3_ADDR; | |
1353 | bis->bi_phymode[0] = 0; | |
1354 | bis->bi_phymode[1] = 0; | |
1355 | bis->bi_phymode[2] = 2; | |
1356 | bis->bi_phymode[3] = 2; | |
ba56f625 | 1357 | |
846b0dd2 | 1358 | #if defined (CONFIG_440GX) |
d6c61aab | 1359 | ppc_4xx_eth_setup_bridge(0, bis); |
c157d8e2 | 1360 | #endif |
a06752e3 WD |
1361 | #endif |
1362 | ||
1e25f957 | 1363 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { |
ba56f625 WD |
1364 | |
1365 | /* See if we can actually bring up the interface, otherwise, skip it */ | |
1366 | switch (eth_num) { | |
e2ffd59b | 1367 | default: /* fall through */ |
ba56f625 | 1368 | case 0: |
3c74e32a WD |
1369 | if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { |
1370 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
ba56f625 | 1371 | continue; |
3c74e32a | 1372 | } |
ba56f625 | 1373 | break; |
e2ffd59b | 1374 | #ifdef CONFIG_HAS_ETH1 |
ba56f625 | 1375 | case 1: |
3c74e32a WD |
1376 | if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) { |
1377 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
ba56f625 | 1378 | continue; |
3c74e32a | 1379 | } |
ba56f625 | 1380 | break; |
e2ffd59b WD |
1381 | #endif |
1382 | #ifdef CONFIG_HAS_ETH2 | |
ba56f625 | 1383 | case 2: |
3c74e32a WD |
1384 | if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) { |
1385 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
ba56f625 | 1386 | continue; |
3c74e32a | 1387 | } |
ba56f625 | 1388 | break; |
e2ffd59b WD |
1389 | #endif |
1390 | #ifdef CONFIG_HAS_ETH3 | |
ba56f625 | 1391 | case 3: |
3c74e32a WD |
1392 | if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) { |
1393 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
ba56f625 | 1394 | continue; |
3c74e32a | 1395 | } |
ba56f625 | 1396 | break; |
e2ffd59b | 1397 | #endif |
ba56f625 WD |
1398 | } |
1399 | ||
1400 | /* Allocate device structure */ | |
1401 | dev = (struct eth_device *) malloc (sizeof (*dev)); | |
1402 | if (dev == NULL) { | |
d6c61aab | 1403 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 1404 | "Cannot allocate eth_device %d\n", eth_num); |
ba56f625 WD |
1405 | return (-1); |
1406 | } | |
b2532eff | 1407 | memset(dev, 0, sizeof(*dev)); |
ba56f625 WD |
1408 | |
1409 | /* Allocate our private use data */ | |
d6c61aab | 1410 | hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); |
ba56f625 | 1411 | if (hw == NULL) { |
d6c61aab | 1412 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 1413 | "Cannot allocate private hw data for eth_device %d", |
ba56f625 WD |
1414 | eth_num); |
1415 | free (dev); | |
1416 | return (-1); | |
1417 | } | |
b2532eff | 1418 | memset(hw, 0, sizeof(*hw)); |
ba56f625 WD |
1419 | |
1420 | switch (eth_num) { | |
e2ffd59b | 1421 | default: /* fall through */ |
ba56f625 WD |
1422 | case 0: |
1423 | hw->hw_addr = 0; | |
1424 | memcpy (dev->enetaddr, bis->bi_enetaddr, 6); | |
1425 | break; | |
e2ffd59b | 1426 | #ifdef CONFIG_HAS_ETH1 |
ba56f625 WD |
1427 | case 1: |
1428 | hw->hw_addr = 0x100; | |
1429 | memcpy (dev->enetaddr, bis->bi_enet1addr, 6); | |
1430 | break; | |
e2ffd59b WD |
1431 | #endif |
1432 | #ifdef CONFIG_HAS_ETH2 | |
ba56f625 WD |
1433 | case 2: |
1434 | hw->hw_addr = 0x400; | |
1435 | memcpy (dev->enetaddr, bis->bi_enet2addr, 6); | |
1436 | break; | |
e2ffd59b WD |
1437 | #endif |
1438 | #ifdef CONFIG_HAS_ETH3 | |
ba56f625 WD |
1439 | case 3: |
1440 | hw->hw_addr = 0x600; | |
1441 | memcpy (dev->enetaddr, bis->bi_enet3addr, 6); | |
1442 | break; | |
e2ffd59b | 1443 | #endif |
ba56f625 WD |
1444 | } |
1445 | ||
1446 | hw->devnum = eth_num; | |
c157d8e2 | 1447 | hw->print_speed = 1; |
ba56f625 | 1448 | |
d6c61aab | 1449 | sprintf (dev->name, "ppc_4xx_eth%d", eth_num); |
ba56f625 | 1450 | dev->priv = (void *) hw; |
d6c61aab SR |
1451 | dev->init = ppc_4xx_eth_init; |
1452 | dev->halt = ppc_4xx_eth_halt; | |
1453 | dev->send = ppc_4xx_eth_send; | |
1454 | dev->recv = ppc_4xx_eth_rx; | |
ba56f625 WD |
1455 | |
1456 | if (0 == virgin) { | |
1457 | /* set the MAL IER ??? names may change with new spec ??? */ | |
1458 | mal_ier = | |
1459 | MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | | |
1460 | MAL_IER_OPBE | MAL_IER_PLBE; | |
1461 | mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ | |
1462 | mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ | |
1463 | mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ | |
1464 | mtdcr (malier, mal_ier); | |
1465 | ||
1466 | /* install MAL interrupt handler */ | |
1467 | irq_install_handler (VECNUM_MS, | |
1468 | (interrupt_handler_t *) enetInt, | |
1469 | dev); | |
1470 | irq_install_handler (VECNUM_MTE, | |
1471 | (interrupt_handler_t *) enetInt, | |
1472 | dev); | |
1473 | irq_install_handler (VECNUM_MRE, | |
1474 | (interrupt_handler_t *) enetInt, | |
1475 | dev); | |
1476 | irq_install_handler (VECNUM_TXDE, | |
1477 | (interrupt_handler_t *) enetInt, | |
1478 | dev); | |
1479 | irq_install_handler (VECNUM_RXDE, | |
1480 | (interrupt_handler_t *) enetInt, | |
1481 | dev); | |
1482 | virgin = 1; | |
1483 | } | |
1484 | ||
d6c61aab | 1485 | #if defined(CONFIG_NET_MULTI) |
ba56f625 | 1486 | eth_register (dev); |
d6c61aab SR |
1487 | #else |
1488 | emac0_dev = dev; | |
1489 | #endif | |
63ff004c MB |
1490 | #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) |
1491 | miiphy_register (dev->name, | |
1492 | emac4xx_miiphy_read, emac4xx_miiphy_write); | |
1493 | #endif | |
ba56f625 WD |
1494 | |
1495 | } /* end for each supported device */ | |
1496 | return (1); | |
1497 | } | |
d6c61aab SR |
1498 | |
1499 | ||
1500 | #if !defined(CONFIG_NET_MULTI) | |
1501 | void eth_halt (void) { | |
1502 | if (emac0_dev) { | |
1503 | ppc_4xx_eth_halt(emac0_dev); | |
1504 | free(emac0_dev); | |
1505 | emac0_dev = NULL; | |
1506 | } | |
1507 | } | |
1508 | ||
1509 | int eth_init (bd_t *bis) | |
1510 | { | |
1511 | ppc_4xx_eth_initialize(bis); | |
4f92ac36 SR |
1512 | if (emac0_dev) { |
1513 | return ppc_4xx_eth_init(emac0_dev, bis); | |
1514 | } else { | |
1515 | printf("ERROR: ethaddr not set!\n"); | |
1516 | return -1; | |
1517 | } | |
d6c61aab SR |
1518 | } |
1519 | ||
1520 | int eth_send(volatile void *packet, int length) | |
1521 | { | |
d6c61aab SR |
1522 | return (ppc_4xx_eth_send(emac0_dev, packet, length)); |
1523 | } | |
1524 | ||
1525 | int eth_rx(void) | |
1526 | { | |
1527 | return (ppc_4xx_eth_rx(emac0_dev)); | |
1528 | } | |
63ff004c MB |
1529 | |
1530 | int emac4xx_miiphy_initialize (bd_t * bis) | |
1531 | { | |
1532 | #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) | |
1533 | miiphy_register ("ppc_4xx_eth0", | |
1534 | emac4xx_miiphy_read, emac4xx_miiphy_write); | |
1535 | #endif | |
1536 | ||
1537 | return 0; | |
1538 | } | |
d6c61aab SR |
1539 | #endif /* !defined(CONFIG_NET_MULTI) */ |
1540 | ||
1541 | #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */ |