[people/ms/u-boot.git] / cpu / ppc4xx / cpu_init.c

/*
 * (C) Copyright 2000-2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <ppc4xx_enet.h>
#include <asm/processor.h>
#include <ppc4xx.h>

#if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
DECLARE_GLOBAL_DATA_PTR;
#endif

#ifdef CFG_INIT_DCACHE_CS
# if (CFG_INIT_DCACHE_CS == 0)
#  define PBxAP pb0ap
#  define PBxCR pb0cr
#  if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#   define PBxAP_VAL CFG_EBC_PB0AP
#   define PBxCR_VAL CFG_EBC_PB0CR
#  endif
# endif
# if (CFG_INIT_DCACHE_CS == 1)
#  define PBxAP pb1ap
#  define PBxCR pb1cr
#  if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
#   define PBxAP_VAL CFG_EBC_PB1AP
#   define PBxCR_VAL CFG_EBC_PB1CR
#  endif
# endif
# if (CFG_INIT_DCACHE_CS == 2)
#  define PBxAP pb2ap
#  define PBxCR pb2cr
#  if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
#   define PBxAP_VAL CFG_EBC_PB2AP
#   define PBxCR_VAL CFG_EBC_PB2CR
#  endif
# endif
# if (CFG_INIT_DCACHE_CS == 3)
#  define PBxAP pb3ap
#  define PBxCR pb3cr
#  if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
#   define PBxAP_VAL CFG_EBC_PB3AP
#   define PBxCR_VAL CFG_EBC_PB3CR
#  endif
# endif
# if (CFG_INIT_DCACHE_CS == 4)
#  define PBxAP pb4ap
#  define PBxCR pb4cr
#  if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
#   define PBxAP_VAL CFG_EBC_PB4AP
#   define PBxCR_VAL CFG_EBC_PB4CR
#  endif
# endif
# if (CFG_INIT_DCACHE_CS == 5)
#  define PBxAP pb5ap
#  define PBxCR pb5cr
#  if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
#   define PBxAP_VAL CFG_EBC_PB5AP
#   define PBxCR_VAL CFG_EBC_PB5CR
#  endif
# endif
# if (CFG_INIT_DCACHE_CS == 6)
#  define PBxAP pb6ap
#  define PBxCR pb6cr
#  if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
#   define PBxAP_VAL CFG_EBC_PB6AP
#   define PBxCR_VAL CFG_EBC_PB6CR
#  endif
# endif
# if (CFG_INIT_DCACHE_CS == 7)
#  define PBxAP pb7ap
#  define PBxCR pb7cr
#  if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
#   define PBxAP_VAL CFG_EBC_PB7AP
#   define PBxCR_VAL CFG_EBC_PB7CR
#  endif
# endif
#endif /* CFG_INIT_DCACHE_CS */

#if defined(CFG_440_GPIO_TABLE)
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;

void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
{
	unsigned char i=0, j=0, reg_offset = 0, gpio_core;
	unsigned long gpio_reg, gpio_core_add;

	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
		j = 0;
		reg_offset = 0;
		/* GPIO config of the GPIOs 0 to 31 */
		for (i=0; i<GPIO_MAX; i++, j++) {
			if (i == GPIO_MAX/2) {
				reg_offset = 4;
				j = i-16;
			}

			gpio_core_add = (*gpio_tab)[gpio_core][i].add;

			if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) ||
			     ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {

				switch ((*gpio_tab)[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					break;

				case GPIO_ALT1:
					gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
					out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
					break;

				case GPIO_ALT2:
					gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
					out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
					break;

				case GPIO_ALT3:
					gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
					out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
					break;
				}
			}

			if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) ||
			     ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {

				switch ((*gpio_tab)[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					if (gpio_core == GPIO0) {
						gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
						out32(GPIO0_TCR, gpio_reg);
					}

					if (gpio_core == GPIO1) {
						gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
						out32(GPIO1_TCR, gpio_reg);
					}

					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
					break;

				case GPIO_ALT1:
					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
					break;

				case GPIO_ALT2:
					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
					break;

				case GPIO_ALT3:
					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
						& ~(GPIO_MASK >> (j*2));
					gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
					break;
				}
			}
		}
	}
}
#endif /* CFG_440_GPIO_TABLE */

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers
 */
void
cpu_init_f (void)
{
#if defined(CONFIG_WATCHDOG)
	unsigned long val;
#endif

#if defined(CONFIG_405EP)
	/*
	 * GPIO0 setup (select GPIO or alternate function)
	 */
#if defined(CFG_GPIO0_OR)
	out32(GPIO0_OR, CFG_GPIO0_OR);		/* set initial state of output pins	*/
#endif
#if defined(CFG_GPIO0_ODR)
	out32(GPIO0_ODR, CFG_GPIO0_ODR);	/* open-drain select			*/
#endif
	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select			*/
	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select				*/
	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select			*/
	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
	out32(GPIO0_TCR, CFG_GPIO0_TCR);	/* enable output driver for outputs	*/

	/*
	 * Set EMAC noise filter bits
	 */
	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
#endif /* CONFIG_405EP */

#if defined(CFG_440_GPIO_TABLE)
	set_chip_gpio_configuration(&gpio_tab);
#endif /* CFG_440_GPIO_TABLE */

	/*
	 * External Bus Controller (EBC) Setup
	 */
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || defined(CONFIG_405))
	/*
	 * Move the next instructions into icache, since these modify the flash
	 * we are running from!
	 */
	asm volatile("	bl	0f"		::: "lr");
	asm volatile("0:	mflr	3"		::: "r3");
	asm volatile("	addi 	4, 0, 14"	::: "r4");
	asm volatile("	mtctr	4"		::: "ctr");
	asm volatile("1:	icbt	0, 3");
	asm volatile("	addi	3, 3, 32"	::: "r3");
	asm volatile("	bdnz	1b"		::: "ctr", "cr0");
	asm volatile("	addis	3, 0, 0x0"	::: "r3");
	asm volatile("	ori	3, 3, 0xA000"	::: "r3");
	asm volatile("	mtctr	3"		::: "ctr");
	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
#endif

	mtebc(pb0ap, CFG_EBC_PB0AP);
	mtebc(pb0cr, CFG_EBC_PB0CR);
#endif

#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
	mtebc(pb1ap, CFG_EBC_PB1AP);
	mtebc(pb1cr, CFG_EBC_PB1CR);
#endif

#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
	mtebc(pb2ap, CFG_EBC_PB2AP);
	mtebc(pb2cr, CFG_EBC_PB2CR);
#endif

#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
	mtebc(pb3ap, CFG_EBC_PB3AP);
	mtebc(pb3cr, CFG_EBC_PB3CR);
#endif

#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
	mtebc(pb4ap, CFG_EBC_PB4AP);
	mtebc(pb4cr, CFG_EBC_PB4CR);
#endif

#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
	mtebc(pb5ap, CFG_EBC_PB5AP);
	mtebc(pb5cr, CFG_EBC_PB5CR);
#endif

#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
	mtebc(pb6ap, CFG_EBC_PB6AP);
	mtebc(pb6cr, CFG_EBC_PB6CR);
#endif

#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
	mtebc(pb7ap, CFG_EBC_PB7AP);
	mtebc(pb7cr, CFG_EBC_PB7CR);
#endif

#if defined (CFG_EBC_CFG)
	mtebc(EBC0_CFG, CFG_EBC_CFG);
#endif

#if defined(CONFIG_WATCHDOG)
	val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
	val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
#else
	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
#endif
#if defined(CFG_4xx_RESET_TYPE)
	val &= ~0x30000000;			/* clear WRC bits */
	val |= CFG_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
#endif
	mtspr(tcr, val);

	val = mfspr(tsr);
	val |= 0x80000000;      /* enable watchdog timer */
	mtspr(tsr, val);

	reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */
}

/*
 * initialize higher level parts of CPU like time base and timers
 */
int cpu_init_r (void)
{
#if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
	bd_t *bd = gd->bd;
	unsigned long reg;
#if defined(CONFIG_405GP)
	uint pvr = get_pvr();
#endif

#ifdef CFG_INIT_DCACHE_CS
	/*
	 * Flush and invalidate dcache, then disable CS for temporary stack.
	 * Afterwards, this CS can be used for other purposes
	 */
	dcache_disable();   /* flush and invalidate dcache */
	mtebc(PBxAP, 0);
	mtebc(PBxCR, 0);    /* disable CS for temporary stack */

#if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
	/*
	 * Write new value into CS register
	 */
	mtebc(PBxAP, PBxAP_VAL);
	mtebc(PBxCR, PBxCR_VAL);
#endif
#endif /* CFG_INIT_DCACHE_CS */

	/*
	 * Write Ethernetaddress into on-chip register
	 */
	reg = 0x00000000;
	reg |= bd->bi_enetaddr[0];           /* set high address */
	reg = reg << 8;
	reg |= bd->bi_enetaddr[1];
	out32 (EMAC_IAH, reg);

	reg = 0x00000000;
	reg |= bd->bi_enetaddr[2];           /* set low address  */
	reg = reg << 8;
	reg |= bd->bi_enetaddr[3];
	reg = reg << 8;
	reg |= bd->bi_enetaddr[4];
	reg = reg << 8;
	reg |= bd->bi_enetaddr[5];
	out32 (EMAC_IAL, reg);

#if defined(CONFIG_405GP)
	/*
	 * Set edge conditioning circuitry on PPC405GPr
	 * for compatibility to existing PPC405GP designs.
	 */
	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
		mtdcr(ecr, 0x60606000);
	}
#endif  /* defined(CONFIG_405GP) */
#endif  /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
	return (0);
}
Commit	Line	Data
4a9cbbe8	1	/*
a4c8d138	2	* (C) Copyright 2000-2006
4a9cbbe8 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <watchdog.h>
d6c61aab	26	#include <ppc4xx_enet.h>
4a9cbbe8 WD	27	#include <asm/processor.h>
	28	#include <ppc4xx.h>
	29
d87080b7 WD	30	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)
	31	DECLARE_GLOBAL_DATA_PTR;
	32	#endif
	33
37208785 SR	34	#ifdef CFG_INIT_DCACHE_CS
	35	# if (CFG_INIT_DCACHE_CS == 0)
	36	# define PBxAP pb0ap
	37	# define PBxCR pb0cr
	38	# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
	39	# define PBxAP_VAL CFG_EBC_PB0AP
	40	# define PBxCR_VAL CFG_EBC_PB0CR
	41	# endif
	42	# endif
	43	# if (CFG_INIT_DCACHE_CS == 1)
	44	# define PBxAP pb1ap
	45	# define PBxCR pb1cr
	46	# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
	47	# define PBxAP_VAL CFG_EBC_PB1AP
	48	# define PBxCR_VAL CFG_EBC_PB1CR
	49	# endif
	50	# endif
	51	# if (CFG_INIT_DCACHE_CS == 2)
	52	# define PBxAP pb2ap
	53	# define PBxCR pb2cr
	54	# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
	55	# define PBxAP_VAL CFG_EBC_PB2AP
	56	# define PBxCR_VAL CFG_EBC_PB2CR
	57	# endif
	58	# endif
	59	# if (CFG_INIT_DCACHE_CS == 3)
	60	# define PBxAP pb3ap
	61	# define PBxCR pb3cr
	62	# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
	63	# define PBxAP_VAL CFG_EBC_PB3AP
	64	# define PBxCR_VAL CFG_EBC_PB3CR
	65	# endif
	66	# endif
	67	# if (CFG_INIT_DCACHE_CS == 4)
	68	# define PBxAP pb4ap
	69	# define PBxCR pb4cr
	70	# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
	71	# define PBxAP_VAL CFG_EBC_PB4AP
	72	# define PBxCR_VAL CFG_EBC_PB4CR
	73	# endif
	74	# endif
	75	# if (CFG_INIT_DCACHE_CS == 5)
	76	# define PBxAP pb5ap
	77	# define PBxCR pb5cr
	78	# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
	79	# define PBxAP_VAL CFG_EBC_PB5AP
	80	# define PBxCR_VAL CFG_EBC_PB5CR
	81	# endif
	82	# endif
	83	# if (CFG_INIT_DCACHE_CS == 6)
	84	# define PBxAP pb6ap
	85	# define PBxCR pb6cr
	86	# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
	87	# define PBxAP_VAL CFG_EBC_PB6AP
	88	# define PBxCR_VAL CFG_EBC_PB6CR
	89	# endif
	90	# endif
	91	# if (CFG_INIT_DCACHE_CS == 7)
	92	# define PBxAP pb7ap
	93	# define PBxCR pb7cr
	94	# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
	95	# define PBxAP_VAL CFG_EBC_PB7AP
	96	# define PBxCR_VAL CFG_EBC_PB7CR
	97	# endif
98	# endif
99	#endif /* CFG_INIT_DCACHE_CS */
100
a4c8d138 SR	101	#if defined(CFG_440_GPIO_TABLE)
	102	gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
	103
	104	void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
	105	{
	106	unsigned char i=0, j=0, reg_offset = 0, gpio_core;
	107	unsigned long gpio_reg, gpio_core_add;
	108
	109	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
	110	j = 0;
	111	reg_offset = 0;
	112	/* GPIO config of the GPIOs 0 to 31 */
	113	for (i=0; i<GPIO_MAX; i++, j++) {
	114	if (i == GPIO_MAX/2) {
	115	reg_offset = 4;
	116	j = i-16;
	117	}
	118
	119	gpio_core_add = (*gpio_tab)[gpio_core][i].add;
	120
	121	if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) \|\|
	122	((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
	123
	124	switch ((*gpio_tab)[gpio_core][i].alt_nb) {
	125	case GPIO_SEL:
	126	break;
	127
	128	case GPIO_ALT1:
	129	gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
	130	& ~(GPIO_MASK >> (j*2));
	131	gpio_reg = gpio_reg \| (GPIO_IN_SEL >> (j*2));
	132	out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
	133	break;
	134
	135	case GPIO_ALT2:
	136	gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
	137	& ~(GPIO_MASK >> (j*2));
	138	gpio_reg = gpio_reg \| (GPIO_IN_SEL >> (j*2));
	139	out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
	140	break;
	141
	142	case GPIO_ALT3:
	143	gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
	144	& ~(GPIO_MASK >> (j*2));
	145	gpio_reg = gpio_reg \| (GPIO_IN_SEL >> (j*2));
	146	out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
	147	break;
	148	}
	149	}
	150
	151	if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) \|\|
	152	((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
	153
	154	switch ((*gpio_tab)[gpio_core][i].alt_nb) {
	155	case GPIO_SEL:
	156	if (gpio_core == GPIO0) {
	157	gpio_reg = in32(GPIO0_TCR) \| (0x80000000 >> (j));
	158	out32(GPIO0_TCR, gpio_reg);
	159	}
	160
	161	if (gpio_core == GPIO1) {
	162	gpio_reg = in32(GPIO1_TCR) \| (0x80000000 >> (j));
	163	out32(GPIO1_TCR, gpio_reg);
	164	}
165
166	gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
167	& ~(GPIO_MASK >> (j*2));
168	out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
169	gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
170	& ~(GPIO_MASK >> (j*2));
171	out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
172	break;
173
174	case GPIO_ALT1:
175	gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
176	& ~(GPIO_MASK >> (j*2));
177	gpio_reg = gpio_reg \| (GPIO_ALT1_SEL >> (j*2));
178	out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
179	gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
180	& ~(GPIO_MASK >> (j*2));
181	gpio_reg = gpio_reg \| (GPIO_ALT1_SEL >> (j*2));
182	out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
183	break;
184
185	case GPIO_ALT2:
186	gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
187	& ~(GPIO_MASK >> (j*2));
188	gpio_reg = gpio_reg \| (GPIO_ALT2_SEL >> (j*2));
189	out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
190	gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
191	& ~(GPIO_MASK >> (j*2));
192	gpio_reg = gpio_reg \| (GPIO_ALT2_SEL >> (j*2));
193	out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
194	break;
195
196	case GPIO_ALT3:
197	gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
198	& ~(GPIO_MASK >> (j*2));
199	gpio_reg = gpio_reg \| (GPIO_ALT3_SEL >> (j*2));
200	out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
201	gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
202	& ~(GPIO_MASK >> (j*2));
203	gpio_reg = gpio_reg \| (GPIO_ALT3_SEL >> (j*2));
204	out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
205	break;
206	}
207	}
208	}
209	}
210	}
211	#endif /* CFG_440_GPIO_TABLE */
4a9cbbe8 WD	212
	213	/*
	214	* Breath some life into the CPU...
	215	*
	216	* Set up the memory map,
	217	* initialize a bunch of registers
	218	*/
	219	void
	220	cpu_init_f (void)
	221	{
f11033e7 WD	222	#if defined(CONFIG_WATCHDOG)
	223	unsigned long val;
	224	#endif
	225
b867d705 SR	226	#if defined(CONFIG_405EP)
	227	/*
	228	* GPIO0 setup (select GPIO or alternate function)
	229	*/
e0a46554 SR	230	#if defined(CFG_GPIO0_OR)
	231	out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
	232	#endif
	233	#if defined(CFG_GPIO0_ODR)
	234	out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
	235	#endif
	236	out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
b867d705	237	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
e0a46554	238	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
b867d705	239	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
e0a46554	240	out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
b867d705	241	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
e0a46554	242	out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
b867d705 SR	243
	244	/*
	245	* Set EMAC noise filter bits
	246	*/
	247	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE \| CPC0_EPRCSR_E1NFE);
	248	#endif /* CONFIG_405EP */
	249
a4c8d138 SR	250	#if defined(CFG_440_GPIO_TABLE)
	251	set_chip_gpio_configuration(&gpio_tab);
	252	#endif /* CFG_440_GPIO_TABLE */
	253
4a9cbbe8 WD	254	/*
	255	* External Bus Controller (EBC) Setup
	256	*/
	257	#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
a4c8d138 SR	258	#if (defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| \
a4c8d138 SR	259	defined(CONFIG_405EP) \|\| defined(CONFIG_405))
4a9cbbe8 WD	260	/*
	261	* Move the next instructions into icache, since these modify the flash
	262	* we are running from!
	263	*/
	264	asm volatile(" bl 0f" ::: "lr");
	265	asm volatile("0: mflr 3" ::: "r3");
	266	asm volatile(" addi 4, 0, 14" ::: "r4");
	267	asm volatile(" mtctr 4" ::: "ctr");
	268	asm volatile("1: icbt 0, 3");
	269	asm volatile(" addi 3, 3, 32" ::: "r3");
	270	asm volatile(" bdnz 1b" ::: "ctr", "cr0");
	271	asm volatile(" addis 3, 0, 0x0" ::: "r3");
	272	asm volatile(" ori 3, 3, 0xA000" ::: "r3");
	273	asm volatile(" mtctr 3" ::: "ctr");
	274	asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
a4c8d138	275	#endif
4a9cbbe8 WD	276
	277	mtebc(pb0ap, CFG_EBC_PB0AP);
	278	mtebc(pb0cr, CFG_EBC_PB0CR);
	279	#endif
	280
37208785	281	#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
4a9cbbe8 WD	282	mtebc(pb1ap, CFG_EBC_PB1AP);
	283	mtebc(pb1cr, CFG_EBC_PB1CR);
	284	#endif
	285
37208785	286	#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
4a9cbbe8 WD	287	mtebc(pb2ap, CFG_EBC_PB2AP);
	288	mtebc(pb2cr, CFG_EBC_PB2CR);
	289	#endif
	290
37208785	291	#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
4a9cbbe8 WD	292	mtebc(pb3ap, CFG_EBC_PB3AP);
	293	mtebc(pb3cr, CFG_EBC_PB3CR);
	294	#endif
	295
37208785	296	#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
4a9cbbe8 WD	297	mtebc(pb4ap, CFG_EBC_PB4AP);
	298	mtebc(pb4cr, CFG_EBC_PB4CR);
	299	#endif
	300
37208785	301	#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
4a9cbbe8 WD	302	mtebc(pb5ap, CFG_EBC_PB5AP);
	303	mtebc(pb5cr, CFG_EBC_PB5CR);
	304	#endif
	305
37208785	306	#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
4a9cbbe8 WD	307	mtebc(pb6ap, CFG_EBC_PB6AP);
	308	mtebc(pb6cr, CFG_EBC_PB6CR);
	309	#endif
	310
37208785	311	#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
4a9cbbe8 WD	312	mtebc(pb7ap, CFG_EBC_PB7AP);
	313	mtebc(pb7cr, CFG_EBC_PB7CR);
	314	#endif
	315
cb482072	316	#if defined (CFG_EBC_CFG)
4745acaa	317	mtebc(EBC0_CFG, CFG_EBC_CFG);
ca43ba18	318	#endif
4a9cbbe8	319
f11033e7	320	#if defined(CONFIG_WATCHDOG)
4a9cbbe8	321	val = mfspr(tcr);
846b0dd2	322	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
c157d8e2 SR	323	val \|= 0xb8000000; /* generate system reset after 1.34 seconds */
c157d8e2 SR	324	#else
4a9cbbe8	325	val \|= 0xf0000000; /* generate system reset after 2.684 seconds */
1c2ce226 SR	326	#endif
	327	#if defined(CFG_4xx_RESET_TYPE)
	328	val &= ~0x30000000; /* clear WRC bits */
	329	val \|= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
c157d8e2	330	#endif
4a9cbbe8 WD	331	mtspr(tcr, val);
	332
	333	val = mfspr(tsr);
	334	val \|= 0x80000000; /* enable watchdog timer */
	335	mtspr(tsr, val);
	336
	337	reset_4xx_watchdog();
	338	#endif /* CONFIG_WATCHDOG */
	339	}
	340
	341	/*
	342	* initialize higher level parts of CPU like time base and timers
	343	*/
	344	int cpu_init_r (void)
	345	{
b867d705	346	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)
4a9cbbe8 WD	347	bd_t *bd = gd->bd;
4a9cbbe8 WD	348	unsigned long reg;
b867d705	349	#if defined(CONFIG_405GP)
38daa27d	350	uint pvr = get_pvr();
b867d705	351	#endif
4a9cbbe8	352
37208785 SR	353	#ifdef CFG_INIT_DCACHE_CS
	354	/*
	355	* Flush and invalidate dcache, then disable CS for temporary stack.
	356	* Afterwards, this CS can be used for other purposes
	357	*/
	358	dcache_disable(); /* flush and invalidate dcache */
	359	mtebc(PBxAP, 0);
	360	mtebc(PBxCR, 0); /* disable CS for temporary stack */
	361
	362	#if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
	363	/*
	364	* Write new value into CS register
	365	*/
	366	mtebc(PBxAP, PBxAP_VAL);
	367	mtebc(PBxCR, PBxCR_VAL);
	368	#endif
	369	#endif /* CFG_INIT_DCACHE_CS */
	370
4a9cbbe8 WD	371	/*
	372	* Write Ethernetaddress into on-chip register
	373	*/
	374	reg = 0x00000000;
	375	reg \|= bd->bi_enetaddr[0]; /* set high address */
	376	reg = reg << 8;
	377	reg \|= bd->bi_enetaddr[1];
	378	out32 (EMAC_IAH, reg);
	379
	380	reg = 0x00000000;
	381	reg \|= bd->bi_enetaddr[2]; /* set low address */
	382	reg = reg << 8;
	383	reg \|= bd->bi_enetaddr[3];
	384	reg = reg << 8;
	385	reg \|= bd->bi_enetaddr[4];
	386	reg = reg << 8;
	387	reg \|= bd->bi_enetaddr[5];
	388	out32 (EMAC_IAL, reg);
38daa27d	389
b867d705	390	#if defined(CONFIG_405GP)
38daa27d SR	391	/*
	392	* Set edge conditioning circuitry on PPC405GPr
	393	* for compatibility to existing PPC405GP designs.
	394	*/
baa3d528	395	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
38daa27d SR	396	mtdcr(ecr, 0x60606000);
38daa27d SR	397	}
b867d705 SR	398	#endif /* defined(CONFIG_405GP) */
b867d705 SR	399	#endif /* defined(CONFIG_405GP) \|\| defined(CONFIG_405EP) */
4a9cbbe8 WD	400	return (0);
4a9cbbe8 WD	401	}