[people/ms/u-boot.git] / cpu / ppc4xx / gpio.c

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>

#if defined(CFG_440_GPIO_TABLE)
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
#endif

#if defined(GPIO0_OSRL)
/* Only some 4xx variants support alternate funtions on the GPIO's */
void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
{
	u32 mask;
	u32 mask2;
	u32 val;
	u32 offs = 0;
	u32 offs2 = 0;
	int pin2 = pin << 1;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	if (pin >= GPIO_MAX/2) {
		offs2 = 0x100;
		pin2 = (pin - GPIO_MAX/2) << 1;
	}

	mask = 0x80000000 >> pin;
	mask2 = 0xc0000000 >> (pin2 << 1);

	/* first set TCR to 0 */
	out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask);

	if (in_out == GPIO_OUT) {
		val = in32(GPIO0_OSRL + offs + offs2) & ~mask2;
		switch (gpio_alt) {
		case GPIO_ALT1:
			val |= GPIO_ALT1_SEL >> pin2;
			break;
		case GPIO_ALT2:
			val |= GPIO_ALT2_SEL >> pin2;
			break;
		case GPIO_ALT3:
			val |= GPIO_ALT3_SEL >> pin2;
			break;
		}
		out32(GPIO0_OSRL + offs + offs2, val);

		/* setup requested output value */
		if (out_val == GPIO_OUT_0)
			out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask);
		else if (out_val == GPIO_OUT_1)
			out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask);

		/* now configure TCR to drive output if selected */
		out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask);
	} else {
		val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2;
		val |= GPIO_IN_SEL >> pin2;
		out32(GPIO0_ISR1L + offs + offs2, val);
	}
}
#endif /* GPIO_OSRL */

void gpio_write_bit(int pin, int val)
{
	u32 offs = 0;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	if (val)
		out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin));
	else
		out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
}

#if defined(CFG_440_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
	unsigned char i=0, j=0, offs=0, gpio_core;
	unsigned long reg, core_add;

	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
		j = 0;
		offs = 0;
		/* GPIO config of the GPIOs 0 to 31 */
		for (i=0; i<GPIO_MAX; i++, j++) {
			if (i == GPIO_MAX/2) {
				offs = 4;
				j = i-16;
			}

			core_add = gpio_tab[gpio_core][i].add;

			if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
			    (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {

				switch (gpio_tab[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					break;

				case GPIO_ALT1:
					reg = in32(GPIO_IS1(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out32(GPIO_IS1(core_add+offs), reg);
					break;

				case GPIO_ALT2:
					reg = in32(GPIO_IS2(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out32(GPIO_IS2(core_add+offs), reg);
					break;

				case GPIO_ALT3:
					reg = in32(GPIO_IS3(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out32(GPIO_IS3(core_add+offs), reg);
					break;
				}
			}

			if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
			    (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {

				switch (gpio_tab[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					if (gpio_core == GPIO0) {
						reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
						out32(GPIO0_TCR, reg);
					}

					if (gpio_core == GPIO1) {
						reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
						out32(GPIO1_TCR, reg);
					}

					reg = in32(GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					out32(GPIO_OS(core_add+offs), reg);
					reg = in32(GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					out32(GPIO_TS(core_add+offs), reg);
					break;

				case GPIO_ALT1:
					reg = in32(GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT1_SEL >> (j*2));
					out32(GPIO_OS(core_add+offs), reg);
					reg = in32(GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT1_SEL >> (j*2));
					out32(GPIO_TS(core_add+offs), reg);
					break;

				case GPIO_ALT2:
					reg = in32(GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT2_SEL >> (j*2));
					out32(GPIO_OS(core_add+offs), reg);
					reg = in32(GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT2_SEL >> (j*2));
					out32(GPIO_TS(core_add+offs), reg);
					break;

				case GPIO_ALT3:
					reg = in32(GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT3_SEL >> (j*2));
					out32(GPIO_OS(core_add+offs), reg);
					reg = in32(GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT3_SEL >> (j*2));
					out32(GPIO_TS(core_add+offs), reg);
					break;
				}
			}
		}
	}
}
#endif /* CFG_440_GPIO_TABLE */
Commit	Line	Data
3cb86f3e SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <asm/io.h>
	27	#include <asm/gpio.h>
	28
	29	#if defined(CFG_440_GPIO_TABLE)
	30	gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
	31	#endif
	32
	33	#if defined(GPIO0_OSRL)
	34	/* Only some 4xx variants support alternate funtions on the GPIO's */
	35	void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
	36	{
	37	u32 mask;
	38	u32 mask2;
	39	u32 val;
	40	u32 offs = 0;
	41	u32 offs2 = 0;
	42	int pin2 = pin << 1;
	43
	44	if (pin >= GPIO_MAX) {
	45	offs = 0x100;
	46	pin -= GPIO_MAX;
	47	}
	48
	49	if (pin >= GPIO_MAX/2) {
	50	offs2 = 0x100;
	51	pin2 = (pin - GPIO_MAX/2) << 1;
	52	}
	53
	54	mask = 0x80000000 >> pin;
	55	mask2 = 0xc0000000 >> (pin2 << 1);
	56
	57	/* first set TCR to 0 */
	58	out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask);
	59
	60	if (in_out == GPIO_OUT) {
	61	val = in32(GPIO0_OSRL + offs + offs2) & ~mask2;
	62	switch (gpio_alt) {
	63	case GPIO_ALT1:
	64	val \|= GPIO_ALT1_SEL >> pin2;
65	break;
66	case GPIO_ALT2:
67	val \|= GPIO_ALT2_SEL >> pin2;
68	break;
69	case GPIO_ALT3:
70	val \|= GPIO_ALT3_SEL >> pin2;
71	break;
72	}
73	out32(GPIO0_OSRL + offs + offs2, val);
74
75	/* setup requested output value */
76	if (out_val == GPIO_OUT_0)
77	out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask);
78	else if (out_val == GPIO_OUT_1)
79	out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) \| mask);
80
81	/* now configure TCR to drive output if selected */
82	out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) \| mask);
83	} else {
84	val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2;
85	val \|= GPIO_IN_SEL >> pin2;
86	out32(GPIO0_ISR1L + offs + offs2, val);
87	}
88	}
89	#endif /* GPIO_OSRL */
90
91	void gpio_write_bit(int pin, int val)
92	{
93	u32 offs = 0;
94
95	if (pin >= GPIO_MAX) {
96	offs = 0x100;
97	pin -= GPIO_MAX;
98	}
99
100	if (val)
101	out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) \| GPIO_VAL(pin));
102	else
103	out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
104	}
105
106	#if defined(CFG_440_GPIO_TABLE)
107	void gpio_set_chip_configuration(void)
108	{
109	unsigned char i=0, j=0, offs=0, gpio_core;
110	unsigned long reg, core_add;
111
112	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
113	j = 0;
114	offs = 0;
115	/* GPIO config of the GPIOs 0 to 31 */
116	for (i=0; i<GPIO_MAX; i++, j++) {
117	if (i == GPIO_MAX/2) {
118	offs = 4;
119	j = i-16;
120	}
121
122	core_add = gpio_tab[gpio_core][i].add;
123
124	if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) \|\|
125	(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
126
127	switch (gpio_tab[gpio_core][i].alt_nb) {
128	case GPIO_SEL:
129	break;
130
131	case GPIO_ALT1:
132	reg = in32(GPIO_IS1(core_add+offs))
133	& ~(GPIO_MASK >> (j*2));
134	reg = reg \| (GPIO_IN_SEL >> (j*2));
135	out32(GPIO_IS1(core_add+offs), reg);
136	break;
137
138	case GPIO_ALT2:
139	reg = in32(GPIO_IS2(core_add+offs))
140	& ~(GPIO_MASK >> (j*2));
141	reg = reg \| (GPIO_IN_SEL >> (j*2));
142	out32(GPIO_IS2(core_add+offs), reg);
143	break;
144
145	case GPIO_ALT3:
146	reg = in32(GPIO_IS3(core_add+offs))
147	& ~(GPIO_MASK >> (j*2));
148	reg = reg \| (GPIO_IN_SEL >> (j*2));
149	out32(GPIO_IS3(core_add+offs), reg);
150	break;
151	}
152	}
153
154	if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) \|\|
155	(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
156
157	switch (gpio_tab[gpio_core][i].alt_nb) {
158	case GPIO_SEL:
159	if (gpio_core == GPIO0) {
160	reg = in32(GPIO0_TCR) \| (0x80000000 >> (j));
161	out32(GPIO0_TCR, reg);
162	}
163
164	if (gpio_core == GPIO1) {
165	reg = in32(GPIO1_TCR) \| (0x80000000 >> (j));
166	out32(GPIO1_TCR, reg);
167	}
168
169	reg = in32(GPIO_OS(core_add+offs))
170	& ~(GPIO_MASK >> (j*2));
171	out32(GPIO_OS(core_add+offs), reg);
172	reg = in32(GPIO_TS(core_add+offs))
173	& ~(GPIO_MASK >> (j*2));
174	out32(GPIO_TS(core_add+offs), reg);
175	break;
176
177	case GPIO_ALT1:
178	reg = in32(GPIO_OS(core_add+offs))
179	& ~(GPIO_MASK >> (j*2));
180	reg = reg \| (GPIO_ALT1_SEL >> (j*2));
181	out32(GPIO_OS(core_add+offs), reg);
182	reg = in32(GPIO_TS(core_add+offs))
183	& ~(GPIO_MASK >> (j*2));
184	reg = reg \| (GPIO_ALT1_SEL >> (j*2));
185	out32(GPIO_TS(core_add+offs), reg);
186	break;
187
188	case GPIO_ALT2:
189	reg = in32(GPIO_OS(core_add+offs))
190	& ~(GPIO_MASK >> (j*2));
191	reg = reg \| (GPIO_ALT2_SEL >> (j*2));
192	out32(GPIO_OS(core_add+offs), reg);
193	reg = in32(GPIO_TS(core_add+offs))
194	& ~(GPIO_MASK >> (j*2));
195	reg = reg \| (GPIO_ALT2_SEL >> (j*2));
196	out32(GPIO_TS(core_add+offs), reg);
197	break;
198
199	case GPIO_ALT3:
200	reg = in32(GPIO_OS(core_add+offs))
201	& ~(GPIO_MASK >> (j*2));
202	reg = reg \| (GPIO_ALT3_SEL >> (j*2));
203	out32(GPIO_OS(core_add+offs), reg);
204	reg = in32(GPIO_TS(core_add+offs))
205	& ~(GPIO_MASK >> (j*2));
206	reg = reg \| (GPIO_ALT3_SEL >> (j*2));
207	out32(GPIO_TS(core_add+offs), reg);
208	break;
209	}
210	}
211	}
212	}
213	}
214	#endif /* CFG_440_GPIO_TABLE */