[people/ms/u-boot.git] / cpu / ppc4xx / gpio.c

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>

#if defined(CFG_440_GPIO_TABLE)
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
#endif

#if defined(GPIO0_OSRL)
/* Only some 4xx variants support alternate funtions on the GPIO's */
void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
{
	u32 mask;
	u32 mask2;
	u32 val;
	u32 offs = 0;
	u32 offs2 = 0;
	int pin2 = pin << 1;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	if (pin >= GPIO_MAX/2) {
		offs2 = 0x100;
		pin2 = (pin - GPIO_MAX/2) << 1;
	}

	mask = 0x80000000 >> pin;
	mask2 = 0xc0000000 >> (pin2 << 1);

	/* first set TCR to 0 */
	out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask);

	if (in_out == GPIO_OUT) {
		val = in32(GPIO0_OSRL + offs + offs2) & ~mask2;
		switch (gpio_alt) {
		case GPIO_ALT1:
			val |= GPIO_ALT1_SEL >> pin2;
			break;
		case GPIO_ALT2:
			val |= GPIO_ALT2_SEL >> pin2;
			break;
		case GPIO_ALT3:
			val |= GPIO_ALT3_SEL >> pin2;
			break;
		}
		out32(GPIO0_OSRL + offs + offs2, val);

		/* setup requested output value */
		if (out_val == GPIO_OUT_0)
			out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask);
		else if (out_val == GPIO_OUT_1)
			out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask);

		/* now configure TCR to drive output if selected */
		out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask);
	} else {
		val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2;
		val |= GPIO_IN_SEL >> pin2;
		out32(GPIO0_ISR1L + offs + offs2, val);
	}
}
#endif /* GPIO_OSRL */

void gpio_write_bit(int pin, int val)
{
	u32 offs = 0;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	if (val)
		out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin));
	else
		out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
}

int gpio_read_out_bit(int pin)
{
	u32 offs = 0;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
}

#if defined(CFG_440_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
	unsigned char i=0, j=0, offs=0, gpio_core;
	unsigned long reg, core_add;

	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
		j = 0;
		offs = 0;
		/* GPIO config of the GPIOs 0 to 31 */
		for (i=0; i<GPIO_MAX; i++, j++) {
			if (i == GPIO_MAX/2) {
				offs = 4;
				j = i-16;
			}

			core_add = gpio_tab[gpio_core][i].add;

			if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
			    (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {

				switch (gpio_tab[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					break;

				case GPIO_ALT1:
					reg = in32(GPIO_IS1(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out32(GPIO_IS1(core_add+offs), reg);
					break;

				case GPIO_ALT2:
					reg = in32(GPIO_IS2(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out32(GPIO_IS2(core_add+offs), reg);
					break;

				case GPIO_ALT3:
					reg = in32(GPIO_IS3(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out32(GPIO_IS3(core_add+offs), reg);
					break;
				}
			}

			if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
			    (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {

				switch (gpio_tab[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					if (gpio_core == GPIO0) {
						/*
						 * Setup output value
						 * 1 -> high level
						 * 0 -> low level
						 * else -> don't touch
						 */
						reg = in32(GPIO0_OR);
						if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
							reg |= (0x80000000 >> (i));
						else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
							reg &= ~(0x80000000 >> (i));
						out32(GPIO0_OR, reg);

						reg = in32(GPIO0_TCR) | (0x80000000 >> (i));
						out32(GPIO0_TCR, reg);
					}

#ifdef GPIO1
					if (gpio_core == GPIO1) {
						/*
						 * Setup output value
						 * 1 -> high level
						 * 0 -> low level
						 * else -> don't touch
						 */
						reg = in32(GPIO1_OR);
						if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
							reg |= (0x80000000 >> (i));
						else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
							reg &= ~(0x80000000 >> (i));
						out32(GPIO1_OR, reg);

						reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
						out32(GPIO1_TCR, reg);
					}
#endif /* GPIO1 */

					reg = in32(GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					out32(GPIO_OS(core_add+offs), reg);
					reg = in32(GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					out32(GPIO_TS(core_add+offs), reg);
					break;

				case GPIO_ALT1:
					reg = in32(GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT1_SEL >> (j*2));
					out32(GPIO_OS(core_add+offs), reg);
					reg = in32(GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT1_SEL >> (j*2));
					out32(GPIO_TS(core_add+offs), reg);
					break;

				case GPIO_ALT2:
					reg = in32(GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT2_SEL >> (j*2));
					out32(GPIO_OS(core_add+offs), reg);
					reg = in32(GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT2_SEL >> (j*2));
					out32(GPIO_TS(core_add+offs), reg);
					break;

				case GPIO_ALT3:
					reg = in32(GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT3_SEL >> (j*2));
					out32(GPIO_OS(core_add+offs), reg);
					reg = in32(GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_ALT3_SEL >> (j*2));
					out32(GPIO_TS(core_add+offs), reg);
					break;
				}
			}
		}
	}
}
#endif /* CFG_440_GPIO_TABLE */
Commit	Line	Data
3cb86f3e SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <asm/io.h>
	27	#include <asm/gpio.h>
	28
	29	#if defined(CFG_440_GPIO_TABLE)
	30	gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
	31	#endif
	32
	33	#if defined(GPIO0_OSRL)
	34	/* Only some 4xx variants support alternate funtions on the GPIO's */
	35	void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
	36	{
	37	u32 mask;
	38	u32 mask2;
	39	u32 val;
	40	u32 offs = 0;
	41	u32 offs2 = 0;
	42	int pin2 = pin << 1;
	43
	44	if (pin >= GPIO_MAX) {
	45	offs = 0x100;
	46	pin -= GPIO_MAX;
	47	}
	48
	49	if (pin >= GPIO_MAX/2) {
	50	offs2 = 0x100;
	51	pin2 = (pin - GPIO_MAX/2) << 1;
	52	}
	53
	54	mask = 0x80000000 >> pin;
	55	mask2 = 0xc0000000 >> (pin2 << 1);
	56
	57	/* first set TCR to 0 */
	58	out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask);
	59
	60	if (in_out == GPIO_OUT) {
	61	val = in32(GPIO0_OSRL + offs + offs2) & ~mask2;
	62	switch (gpio_alt) {
	63	case GPIO_ALT1:
	64	val \|= GPIO_ALT1_SEL >> pin2;
65	break;
66	case GPIO_ALT2:
67	val \|= GPIO_ALT2_SEL >> pin2;
68	break;
69	case GPIO_ALT3:
70	val \|= GPIO_ALT3_SEL >> pin2;
71	break;
72	}
73	out32(GPIO0_OSRL + offs + offs2, val);
74
75	/* setup requested output value */
76	if (out_val == GPIO_OUT_0)
77	out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask);
78	else if (out_val == GPIO_OUT_1)
79	out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) \| mask);
80
81	/* now configure TCR to drive output if selected */
82	out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) \| mask);
83	} else {
84	val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2;
85	val \|= GPIO_IN_SEL >> pin2;
86	out32(GPIO0_ISR1L + offs + offs2, val);
87	}
88	}
89	#endif /* GPIO_OSRL */
90
91	void gpio_write_bit(int pin, int val)
92	{
93	u32 offs = 0;
94
95	if (pin >= GPIO_MAX) {
96	offs = 0x100;
97	pin -= GPIO_MAX;
98	}
99
100	if (val)
101	out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) \| GPIO_VAL(pin));
102	else
103	out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
104	}
105
85f73737 SR	106	int gpio_read_out_bit(int pin)
	107	{
	108	u32 offs = 0;
	109
	110	if (pin >= GPIO_MAX) {
	111	offs = 0x100;
	112	pin -= GPIO_MAX;
	113	}
	114
	115	return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
	116	}
	117
3cb86f3e SR	118	#if defined(CFG_440_GPIO_TABLE)
	119	void gpio_set_chip_configuration(void)
	120	{
	121	unsigned char i=0, j=0, offs=0, gpio_core;
	122	unsigned long reg, core_add;
	123
	124	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
	125	j = 0;
	126	offs = 0;
	127	/* GPIO config of the GPIOs 0 to 31 */
	128	for (i=0; i<GPIO_MAX; i++, j++) {
	129	if (i == GPIO_MAX/2) {
	130	offs = 4;
	131	j = i-16;
	132	}
	133
	134	core_add = gpio_tab[gpio_core][i].add;
	135
	136	if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) \|\|
	137	(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
	138
	139	switch (gpio_tab[gpio_core][i].alt_nb) {
	140	case GPIO_SEL:
	141	break;
	142
	143	case GPIO_ALT1:
	144	reg = in32(GPIO_IS1(core_add+offs))
	145	& ~(GPIO_MASK >> (j*2));
	146	reg = reg \| (GPIO_IN_SEL >> (j*2));
	147	out32(GPIO_IS1(core_add+offs), reg);
	148	break;
	149
	150	case GPIO_ALT2:
	151	reg = in32(GPIO_IS2(core_add+offs))
	152	& ~(GPIO_MASK >> (j*2));
	153	reg = reg \| (GPIO_IN_SEL >> (j*2));
	154	out32(GPIO_IS2(core_add+offs), reg);
	155	break;
	156
	157	case GPIO_ALT3:
	158	reg = in32(GPIO_IS3(core_add+offs))
	159	& ~(GPIO_MASK >> (j*2));
	160	reg = reg \| (GPIO_IN_SEL >> (j*2));
	161	out32(GPIO_IS3(core_add+offs), reg);
	162	break;
	163	}
	164	}
	165
	166	if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) \|\|
	167	(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
	168
	169	switch (gpio_tab[gpio_core][i].alt_nb) {
	170	case GPIO_SEL:
	171	if (gpio_core == GPIO0) {
85f73737 SR	172	/*
	173	* Setup output value
	174	* 1 -> high level
	175	* 0 -> low level
	176	* else -> don't touch
	177	*/
	178	reg = in32(GPIO0_OR);
	179	if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
	180	reg \|= (0x80000000 >> (i));
	181	else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
	182	reg &= ~(0x80000000 >> (i));
	183	out32(GPIO0_OR, reg);
	184
fba3fb04	185	reg = in32(GPIO0_TCR) \| (0x80000000 >> (i));
3cb86f3e SR	186	out32(GPIO0_TCR, reg);
	187	}
	188
d4024bb7	189	#ifdef GPIO1
3cb86f3e	190	if (gpio_core == GPIO1) {
85f73737 SR	191	/*
	192	* Setup output value
	193	* 1 -> high level
	194	* 0 -> low level
	195	* else -> don't touch
	196	*/
a71d96ea	197	reg = in32(GPIO1_OR);
85f73737 SR	198	if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
	199	reg \|= (0x80000000 >> (i));
	200	else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
	201	reg &= ~(0x80000000 >> (i));
a71d96ea	202	out32(GPIO1_OR, reg);
85f73737	203
fba3fb04	204	reg = in32(GPIO1_TCR) \| (0x80000000 >> (i));
3cb86f3e SR	205	out32(GPIO1_TCR, reg);
3cb86f3e SR	206	}
d4024bb7	207	#endif /* GPIO1 */
3cb86f3e SR	208
	209	reg = in32(GPIO_OS(core_add+offs))
	210	& ~(GPIO_MASK >> (j*2));
	211	out32(GPIO_OS(core_add+offs), reg);
	212	reg = in32(GPIO_TS(core_add+offs))
	213	& ~(GPIO_MASK >> (j*2));
	214	out32(GPIO_TS(core_add+offs), reg);
	215	break;
	216
	217	case GPIO_ALT1:
	218	reg = in32(GPIO_OS(core_add+offs))
	219	& ~(GPIO_MASK >> (j*2));
	220	reg = reg \| (GPIO_ALT1_SEL >> (j*2));
	221	out32(GPIO_OS(core_add+offs), reg);
	222	reg = in32(GPIO_TS(core_add+offs))
	223	& ~(GPIO_MASK >> (j*2));
	224	reg = reg \| (GPIO_ALT1_SEL >> (j*2));
	225	out32(GPIO_TS(core_add+offs), reg);
	226	break;
	227
	228	case GPIO_ALT2:
	229	reg = in32(GPIO_OS(core_add+offs))
	230	& ~(GPIO_MASK >> (j*2));
	231	reg = reg \| (GPIO_ALT2_SEL >> (j*2));
	232	out32(GPIO_OS(core_add+offs), reg);
	233	reg = in32(GPIO_TS(core_add+offs))
	234	& ~(GPIO_MASK >> (j*2));
	235	reg = reg \| (GPIO_ALT2_SEL >> (j*2));
	236	out32(GPIO_TS(core_add+offs), reg);
	237	break;
	238
	239	case GPIO_ALT3:
	240	reg = in32(GPIO_OS(core_add+offs))
	241	& ~(GPIO_MASK >> (j*2));
	242	reg = reg \| (GPIO_ALT3_SEL >> (j*2));
	243	out32(GPIO_OS(core_add+offs), reg);
	244	reg = in32(GPIO_TS(core_add+offs))
	245	& ~(GPIO_MASK >> (j*2));
	246	reg = reg \| (GPIO_ALT3_SEL >> (j*2));
	247	out32(GPIO_TS(core_add+offs), reg);
	248	break;
	249	}
	250	}
	251	}
	252	}
	253	}
	254	#endif /* CFG_440_GPIO_TABLE */