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Add support for AMCC Sequoia PPC440EPx eval board
[people/ms/u-boot.git] / cpu / ppc4xx / serial.c
CommitLineData
fe8c2806 1/*
b9365a26 2 * (C) Copyright 2000-2006
fe8c2806
WD		 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23/*------------------------------------------------------------------------------+ */
24/*
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
31 *
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
35 *
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
39 *
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
42 */
43/*------------------------------------------------------------------------------- */
ff36fd85
WD		 44/*
45 * Travis Sawyer 15 September 2004
46 * Added CONFIG_SERIAL_MULTI support
47 */
fe8c2806
WD		 48#include <common.h>
49#include <commproc.h>
50#include <asm/processor.h>
51#include <watchdog.h>
52#include "vecnum.h"
53
ff36fd85
WD		 54#ifdef CONFIG_SERIAL_MULTI
55#include <serial.h>
56#endif
57
42dfe7a1 58#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 59#include <malloc.h>
60#endif
61
d87080b7
WD		 62DECLARE_GLOBAL_DATA_PTR;
63
fe8c2806
WD		 64/*****************************************************************************/
65#ifdef CONFIG_IOP480
66
67#define SPU_BASE 0x40000000
68
69#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
70#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
71#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
72#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
73#define spu_BRateDivh 0x10 /* Baud rate divisor high */
74#define spu_BRateDivl 0x14 /* Baud rate divisor low */
75#define spu_CtlReg 0x18 /* Control Register */
76#define spu_RxCmd 0x1c /* Rx Command Register */
77#define spu_TxCmd 0x20 /* Tx Command Register */
78#define spu_RxBuff 0x24 /* Rx data buffer */
79#define spu_TxBuff 0x24 /* Tx data buffer */
80
81/*-----------------------------------------------------------------------------+
82 | Line Status Register.
83 +-----------------------------------------------------------------------------*/
84#define asyncLSRport1 0x40000000
85#define asyncLSRport1set 0x40000004
86#define asyncLSRDataReady 0x80
87#define asyncLSRFramingError 0x40
88#define asyncLSROverrunError 0x20
89#define asyncLSRParityError 0x10
90#define asyncLSRBreakInterrupt 0x08
91#define asyncLSRTxHoldEmpty 0x04
92#define asyncLSRTxShiftEmpty 0x02
93
94/*-----------------------------------------------------------------------------+
95 | Handshake Status Register.
96 +-----------------------------------------------------------------------------*/
97#define asyncHSRport1 0x40000008
98#define asyncHSRport1set 0x4000000c
99#define asyncHSRDsr 0x80
100#define asyncLSRCts 0x40
101
102/*-----------------------------------------------------------------------------+
103 | Control Register.
104 +-----------------------------------------------------------------------------*/
105#define asyncCRport1 0x40000018
106#define asyncCRNormal 0x00
107#define asyncCRLoopback 0x40
108#define asyncCRAutoEcho 0x80
109#define asyncCRDtr 0x20
110#define asyncCRRts 0x10
111#define asyncCRWordLength7 0x00
112#define asyncCRWordLength8 0x08
113#define asyncCRParityDisable 0x00
114#define asyncCRParityEnable 0x04
115#define asyncCREvenParity 0x00
116#define asyncCROddParity 0x02
117#define asyncCRStopBitsOne 0x00
118#define asyncCRStopBitsTwo 0x01
119#define asyncCRDisableDtrRts 0x00
120
121/*-----------------------------------------------------------------------------+
122 | Receiver Command Register.
123 +-----------------------------------------------------------------------------*/
124#define asyncRCRport1 0x4000001c
125#define asyncRCRDisable 0x00
126#define asyncRCREnable 0x80
127#define asyncRCRIntDisable 0x00
128#define asyncRCRIntEnabled 0x20
129#define asyncRCRDMACh2 0x40
130#define asyncRCRDMACh3 0x60
131#define asyncRCRErrorInt 0x10
132#define asyncRCRPauseEnable 0x08
133
134/*-----------------------------------------------------------------------------+
135 | Transmitter Command Register.
136 +-----------------------------------------------------------------------------*/
137#define asyncTCRport1 0x40000020
138#define asyncTCRDisable 0x00
139#define asyncTCREnable 0x80
140#define asyncTCRIntDisable 0x00
141#define asyncTCRIntEnabled 0x20
142#define asyncTCRDMACh2 0x40
143#define asyncTCRDMACh3 0x60
144#define asyncTCRTxEmpty 0x10
145#define asyncTCRErrorInt 0x08
146#define asyncTCRStopPause 0x04
147#define asyncTCRBreakGen 0x02
148
149/*-----------------------------------------------------------------------------+
150 | Miscellanies defines.
151 +-----------------------------------------------------------------------------*/
152#define asyncTxBufferport1 0x40000024
153#define asyncRxBufferport1 0x40000024
154#define asyncDLABLsbport1 0x40000014
155#define asyncDLABMsbport1 0x40000010
156#define asyncXOFFchar 0x13
157#define asyncXONchar 0x11
158
fe8c2806
WD		 159/*
160 * Minimal serial functions needed to use one of the SMC ports
161 * as serial console interface.
162 */
163
164int serial_init (void)
165{
fe8c2806
WD		 166 volatile char val;
167 unsigned short br_reg;
168
169 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
170
171 /*
172 * Init onboard UART
173 */
174 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
175 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
176 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
177 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
178 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
179 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
180 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
181 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
182
183 return (0);
184}
185
fe8c2806
WD		 186void serial_setbrg (void)
187{
fe8c2806
WD		 188 unsigned short br_reg;
189
190 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
191
192 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
193 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
194}
195
fe8c2806
WD		 196void serial_putc (const char c)
197{
198 if (c == '\n')
199 serial_putc ('\r');
200
201 /* load status from handshake register */
202 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
203 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
204
205 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
206
207 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
208 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
209 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
210 }
211}
212
fe8c2806
WD		 213void serial_puts (const char *s)
214{
215 while (*s) {
216 serial_putc (*s++);
217 }
218}
219
fe8c2806
WD		 220int serial_getc ()
221{
222 unsigned char status = 0;
223
224 while (1) {
225 status = in8 (asyncLSRport1);
226 if ((status & asyncLSRDataReady) != 0x0) {
227 break;
228 }
229 if ((status & ( asyncLSRFramingError |
230 asyncLSROverrunError |
231 asyncLSRParityError |
232 asyncLSRBreakInterrupt )) != 0) {
233 (void) out8 (asyncLSRport1,
234 asyncLSRFramingError |
235 asyncLSROverrunError |
236 asyncLSRParityError |
237 asyncLSRBreakInterrupt );
238 }
239 }
240 return (0x000000ff & (int) in8 (asyncRxBufferport1));
241}
242
fe8c2806
WD		 243int serial_tstc ()
244{
245 unsigned char status;
246
247 status = in8 (asyncLSRport1);
248 if ((status & asyncLSRDataReady) != 0x0) {
249 return (1);
250 }
251 if ((status & ( asyncLSRFramingError |
252 asyncLSROverrunError |
253 asyncLSRParityError |
254 asyncLSRBreakInterrupt )) != 0) {
255 (void) out8 (asyncLSRport1,
256 asyncLSRFramingError |
257 asyncLSROverrunError |
258 asyncLSRParityError |
259 asyncLSRBreakInterrupt);
260 }
261 return 0;
262}
263
264#endif /* CONFIG_IOP480 */
265
fe8c2806 266/*****************************************************************************/
887e2ec9
SR		 267#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
268 defined(CONFIG_440)
fe8c2806
WD		 269
270#if defined(CONFIG_440)
887e2ec9
SR		 271#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
272 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
c157d8e2
SR		 273#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
274#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
275#else
fe8c2806
WD		 276#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
277#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
c157d8e2 278#endif
6e7fb6ea 279
6c5879f3 280#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
6e7fb6ea
SR		 281#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
282#endif
283
887e2ec9 284#if defined(CONFIG_440GP)
fe8c2806
WD		 285#define CR0_MASK 0x3fff0000
286#define CR0_EXTCLK_ENA 0x00600000
287#define CR0_UDIV_POS 16
887e2ec9
SR		 288#define UDIV_SUBTRACT 1
289#define UART0_SDR cntrl0
290#define MFREG(a, d) d = mfdcr(a)
291#define MTREG(a, d) mtdcr(a, d)
292#else /* #if defined(CONFIG_440GP) */
293/* all other 440 PPC's access clock divider via sdr register */
294#define CR0_MASK 0xdfffffff
295#define CR0_EXTCLK_ENA 0x00800000
296#define CR0_UDIV_POS 0
297#define UDIV_SUBTRACT 0
298#define UART0_SDR sdr_uart0
299#define UART1_SDR sdr_uart1
300#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
301 defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
302 defined(CONFIG_440SP) || defined(CONFIG_440SPe)
303#define UART2_SDR sdr_uart2
304#endif
305#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
306 defined(CONFIG_440GR) || defined(CONFIG_440GRx)
307#define UART3_SDR sdr_uart3
308#endif
309#define MFREG(a, d) mfsdr(a, d)
310#define MTREG(a, d) mtsdr(a, d)
311#endif /* #if defined(CONFIG_440GP) */
8749cfb4
SR		 312#elif defined(CONFIG_405EP)
313#define UART0_BASE 0xef600300
314#define UART1_BASE 0xef600400
315#define UCR0_MASK 0x0000007f
316#define UCR1_MASK 0x00007f00
317#define UCR0_UDIV_POS 0
318#define UCR1_UDIV_POS 8
319#define UDIV_MAX 127
320#else /* CONFIG_405GP || CONFIG_405CR */
fe8c2806
WD		 321#define UART0_BASE 0xef600300
322#define UART1_BASE 0xef600400
323#define CR0_MASK 0x00001fff
d7787c6e 324#define CR0_EXTCLK_ENA 0x000000c0
fe8c2806 325#define CR0_UDIV_POS 1
8749cfb4
SR		 326#define UDIV_MAX 32
327#endif
328
329/* using serial port 0 or 1 as U-Boot console ? */
330#if defined(CONFIG_UART1_CONSOLE)
331#define ACTING_UART0_BASE UART1_BASE
332#define ACTING_UART1_BASE UART0_BASE
333#else
334#define ACTING_UART0_BASE UART0_BASE
335#define ACTING_UART1_BASE UART1_BASE
887e2ec9
SR		 336#endif
337
338#if defined(CONFIG_SERIAL_MULTI)
339#define UART_BASE dev_base
340#else
341#define UART_BASE ACTING_UART0_BASE
8749cfb4
SR		 342#endif
343
344#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
0c8721a4 345#error "External serial clock not supported on AMCC PPC405EP!"
fe8c2806
WD		 346#endif
347
348#define UART_RBR 0x00
349#define UART_THR 0x00
350#define UART_IER 0x01
351#define UART_IIR 0x02
352#define UART_FCR 0x02
353#define UART_LCR 0x03
354#define UART_MCR 0x04
355#define UART_LSR 0x05
356#define UART_MSR 0x06
357#define UART_SCR 0x07
358#define UART_DLL 0x00
359#define UART_DLM 0x01
360
361/*-----------------------------------------------------------------------------+
362 | Line Status Register.
363 +-----------------------------------------------------------------------------*/
8749cfb4 364/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
fe8c2806
WD		 365#define asyncLSRDataReady1 0x01
366#define asyncLSROverrunError1 0x02
367#define asyncLSRParityError1 0x04
368#define asyncLSRFramingError1 0x08
369#define asyncLSRBreakInterrupt1 0x10
370#define asyncLSRTxHoldEmpty1 0x20
371#define asyncLSRTxShiftEmpty1 0x40
372#define asyncLSRRxFifoError1 0x80
373
374/*-----------------------------------------------------------------------------+
375 | Miscellanies defines.
376 +-----------------------------------------------------------------------------*/
8749cfb4
SR		 377/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
378/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
fe8c2806 379
42dfe7a1 380#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 381/*-----------------------------------------------------------------------------+
382 | Fifo
383 +-----------------------------------------------------------------------------*/
384typedef struct {
385 char *rx_buffer;
386 ulong rx_put;
387 ulong rx_get;
388} serial_buffer_t;
389
390volatile static serial_buffer_t buf_info;
391#endif
392
fe8c2806
WD		 393#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
394static void serial_divs (int baudrate, unsigned long *pudiv,
395 unsigned short *pbdiv )
396{
397 sys_info_t sysinfo;
398 unsigned long div; /* total divisor udiv * bdiv */
399 unsigned long umin; /* minimum udiv */
400 unsigned short diff; /* smallest diff */
401 unsigned long udiv; /* best udiv */
402
403 unsigned short idiff; /* current diff */
404 unsigned short ibdiv; /* current bdiv */
405 unsigned long i;
406 unsigned long est; /* current estimate */
407
408 get_sys_info( &sysinfo );
409
410 udiv = 32; /* Assume lowest possible serial clk */
411 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
412 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
413 diff = 32; /* highest possible */
414
415 /* i is the test udiv value -- start with the largest
416 * possible (32) to minimize serial clock and constrain
417 * search to umin.
418 */
419 for( i = 32; i > umin; i-- ){
420 ibdiv = div/i;
421 est = i * ibdiv;
422 idiff = (est > div) ? (est-div) : (div-est);
423 if( idiff == 0 ){
424 udiv = i;
425 break; /* can't do better */
426 }
427 else if( idiff < diff ){
428 udiv = i; /* best so far */
429 diff = idiff; /* update lowest diff*/
430 }
431 }
432
433 *pudiv = udiv;
434 *pbdiv = div/udiv;
435
436}
887e2ec9 437#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
fe8c2806 438
fe8c2806
WD		 439/*
440 * Minimal serial functions needed to use one of the SMC ports
441 * as serial console interface.
442 */
443
444#if defined(CONFIG_440)
ff36fd85
WD		 445#if defined(CONFIG_SERIAL_MULTI)
446int serial_init_dev (unsigned long dev_base)
447#else
448int serial_init(void)
449#endif
fe8c2806 450{
fe8c2806
WD		 451 unsigned long reg;
452 unsigned long udiv;
453 unsigned short bdiv;
454 volatile char val;
455#ifdef CFG_EXT_SERIAL_CLOCK
456 unsigned long tmp;
457#endif
458
887e2ec9 459 MFREG(UART0_SDR, reg);
ba56f625 460 reg &= ~CR0_MASK;
887e2ec9 461
fe8c2806
WD		 462#ifdef CFG_EXT_SERIAL_CLOCK
463 reg |= CR0_EXTCLK_ENA;
464 udiv = 1;
465 tmp = gd->baudrate * 16;
466 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
467#else
468 /* For 440, the cpu clock is on divider chain A, UART on divider
469 * chain B ... so cpu clock is irrelevant. Get the "optimized"
470 * values that are subject to the 1/2 opb clock constraint
471 */
472 serial_divs (gd->baudrate, &udiv, &bdiv);
473#endif
474
887e2ec9
SR		 475 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
476
477 /*
478 * Configure input clock to baudrate generator for all
479 * available serial ports here
480 */
481 MTREG(UART0_SDR, reg);
482#if defined(UART1_SDR)
483 MTREG(UART1_SDR, reg);
ff36fd85 484#endif
887e2ec9
SR		 485#if defined(UART2_SDR)
486 MTREG(UART2_SDR, reg);
ba56f625 487#endif
887e2ec9
SR		 488#if defined(UART3_SDR)
489 MTREG(UART3_SDR, reg);
ff36fd85 490#endif
887e2ec9
SR		 491
492 out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
493 out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
494 out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
495 out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
496 out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
497 out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
498 val = in8(UART_BASE + UART_LSR); /* clear line status */
499 val = in8(UART_BASE + UART_RBR); /* read receive buffer */
500 out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
501 out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
502
fe8c2806
WD		 503 return (0);
504}
505
506#else /* !defined(CONFIG_440) */
507
ff36fd85
WD		 508#if defined(CONFIG_SERIAL_MULTI)
509int serial_init_dev (unsigned long dev_base)
510#else
fe8c2806 511int serial_init (void)
ff36fd85 512#endif
fe8c2806 513{
fe8c2806
WD		 514 unsigned long reg;
515 unsigned long tmp;
516 unsigned long clk;
517 unsigned long udiv;
518 unsigned short bdiv;
519 volatile char val;
520
8749cfb4
SR		 521#ifdef CONFIG_405EP
522 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
523 clk = gd->cpu_clk;
524 tmp = CFG_BASE_BAUD * 16;
525 udiv = (clk + tmp / 2) / tmp;
526 if (udiv > UDIV_MAX) /* max. n bits for udiv */
527 udiv = UDIV_MAX;
528 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
529 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
530 mtdcr (cpc0_ucr, reg);
531#else /* CONFIG_405EP */
fe8c2806
WD		 532 reg = mfdcr(cntrl0) & ~CR0_MASK;
533#ifdef CFG_EXT_SERIAL_CLOCK
534 clk = CFG_EXT_SERIAL_CLOCK;
535 udiv = 1;
536 reg |= CR0_EXTCLK_ENA;
537#else
538 clk = gd->cpu_clk;
539#ifdef CFG_405_UART_ERRATA_59
540 udiv = 31; /* Errata 59: stuck at 31 */
541#else
542 tmp = CFG_BASE_BAUD * 16;
543 udiv = (clk + tmp / 2) / tmp;
8749cfb4
SR		 544 if (udiv > UDIV_MAX) /* max. n bits for udiv */
545 udiv = UDIV_MAX;
fe8c2806
WD		 546#endif
547#endif
fe8c2806
WD		 548 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
549 mtdcr (cntrl0, reg);
8749cfb4 550#endif /* CONFIG_405EP */
fe8c2806
WD		 551
552 tmp = gd->baudrate * udiv * 16;
553 bdiv = (clk + tmp / 2) / tmp;
554
887e2ec9
SR		 555 out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
556 out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
557 out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
558 out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
559 out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
560 out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
561 val = in8(UART_BASE + UART_LSR); /* clear line status */
562 val = in8(UART_BASE + UART_RBR); /* read receive buffer */
563 out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
564 out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
565
fe8c2806
WD		 566 return (0);
567}
568
569#endif /* if defined(CONFIG_440) */
570
ff36fd85
WD		 571#if defined(CONFIG_SERIAL_MULTI)
572void serial_setbrg_dev (unsigned long dev_base)
573#else
fe8c2806 574void serial_setbrg (void)
ff36fd85 575#endif
fe8c2806 576{
ff36fd85 577#if defined(CONFIG_SERIAL_MULTI)
887e2ec9 578 serial_init_dev(dev_base);
ff36fd85 579#else
887e2ec9 580 serial_init();
ff36fd85 581#endif
fe8c2806
WD		 582}
583
ff36fd85
WD		 584#if defined(CONFIG_SERIAL_MULTI)
585void serial_putc_dev (unsigned long dev_base, const char c)
586#else
fe8c2806 587void serial_putc (const char c)
ff36fd85 588#endif
fe8c2806
WD		 589{
590 int i;
591
592 if (c == '\n')
ff36fd85
WD		 593#if defined(CONFIG_SERIAL_MULTI)
594 serial_putc_dev (dev_base, '\r');
595#else
fe8c2806 596 serial_putc ('\r');
ff36fd85 597#endif
fe8c2806
WD		 598
599 /* check THRE bit, wait for transmiter available */
600 for (i = 1; i < 3500; i++) {
887e2ec9 601 if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20)
fe8c2806
WD		 602 break;
603 udelay (100);
604 }
887e2ec9 605 out8 (UART_BASE + UART_THR, c); /* put character out */
fe8c2806
WD		 606}
607
ff36fd85
WD		 608#if defined(CONFIG_SERIAL_MULTI)
609void serial_puts_dev (unsigned long dev_base, const char *s)
610#else
fe8c2806 611void serial_puts (const char *s)
ff36fd85 612#endif
fe8c2806
WD		 613{
614 while (*s) {
ff36fd85
WD		 615#if defined(CONFIG_SERIAL_MULTI)
616 serial_putc_dev (dev_base, *s++);
617#else
fe8c2806 618 serial_putc (*s++);
ff36fd85 619#endif
fe8c2806
WD		 620 }
621}
622
ff36fd85
WD		 623#if defined(CONFIG_SERIAL_MULTI)
624int serial_getc_dev (unsigned long dev_base)
625#else
626int serial_getc (void)
627#endif
fe8c2806
WD		 628{
629 unsigned char status = 0;
630
631 while (1) {
632#if defined(CONFIG_HW_WATCHDOG)
633 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
634#endif /* CONFIG_HW_WATCHDOG */
887e2ec9 635 status = in8 (UART_BASE + UART_LSR);
fe8c2806
WD		 636 if ((status & asyncLSRDataReady1) != 0x0) {
637 break;
638 }
639 if ((status & ( asyncLSRFramingError1 |
640 asyncLSROverrunError1 |
641 asyncLSRParityError1 |
642 asyncLSRBreakInterrupt1 )) != 0) {
887e2ec9 643 out8 (UART_BASE + UART_LSR,
fe8c2806
WD		 644 asyncLSRFramingError1 |
645 asyncLSROverrunError1 |
646 asyncLSRParityError1 |
647 asyncLSRBreakInterrupt1);
648 }
649 }
887e2ec9 650 return (0x000000ff & (int) in8 (UART_BASE));
fe8c2806
WD		 651}
652
ff36fd85
WD		 653#if defined(CONFIG_SERIAL_MULTI)
654int serial_tstc_dev (unsigned long dev_base)
655#else
656int serial_tstc (void)
657#endif
fe8c2806
WD		 658{
659 unsigned char status;
660
887e2ec9 661 status = in8 (UART_BASE + UART_LSR);
fe8c2806
WD		 662 if ((status & asyncLSRDataReady1) != 0x0) {
663 return (1);
664 }
665 if ((status & ( asyncLSRFramingError1 |
666 asyncLSROverrunError1 |
667 asyncLSRParityError1 |
668 asyncLSRBreakInterrupt1 )) != 0) {
887e2ec9 669 out8 (UART_BASE + UART_LSR,
fe8c2806
WD		 670 asyncLSRFramingError1 |
671 asyncLSROverrunError1 |
672 asyncLSRParityError1 |
673 asyncLSRBreakInterrupt1);
674 }
675 return 0;
676}
677
42dfe7a1 678#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 679
680void serial_isr (void *arg)
681{
682 int space;
683 int c;
684 const int rx_get = buf_info.rx_get;
685 int rx_put = buf_info.rx_put;
686
687 if (rx_get <= rx_put) {
688 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
689 } else {
690 space = rx_get - rx_put;
691 }
ff36fd85
WD		 692 while (serial_tstc_dev (ACTING_UART0_BASE)) {
693 c = serial_getc_dev (ACTING_UART0_BASE);
fe8c2806
WD		 694 if (space) {
695 buf_info.rx_buffer[rx_put++] = c;
696 space--;
697 }
698 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
699 rx_put = 0;
700 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
701 /* Stop flow by setting RTS inactive */
8749cfb4
SR		 702 out8 (ACTING_UART0_BASE + UART_MCR,
703 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
fe8c2806
WD		 704 }
705 }
706 buf_info.rx_put = rx_put;
707}
708
709void serial_buffered_init (void)
710{
711 serial_puts ("Switching to interrupt driven serial input mode.\n");
712 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
713 buf_info.rx_put = 0;
714 buf_info.rx_get = 0;
715
8749cfb4 716 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
fe8c2806
WD		 717 serial_puts ("Check CTS signal present on serial port: OK.\n");
718 } else {
719 serial_puts ("WARNING: CTS signal not present on serial port.\n");
720 }
721
722 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
723 serial_isr /*interrupt_handler_t *handler */ ,
724 (void *) &buf_info /*void *arg */ );
725
726 /* Enable "RX Data Available" Interrupt on UART */
8749cfb4
SR		 727 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
728 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
fe8c2806 729 /* Set DTR active */
8749cfb4 730 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
fe8c2806 731 /* Start flow by setting RTS active */
8749cfb4 732 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806 733 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
8749cfb4 734 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
fe8c2806
WD		 735}
736
737void serial_buffered_putc (const char c)
738{
739 /* Wait for CTS */
740#if defined(CONFIG_HW_WATCHDOG)
8749cfb4 741 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
fe8c2806
WD		 742 WATCHDOG_RESET ();
743#else
8749cfb4 744 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
fe8c2806
WD		 745#endif
746 serial_putc (c);
747}
748
749void serial_buffered_puts (const char *s)
750{
751 serial_puts (s);
752}
753
754int serial_buffered_getc (void)
755{
756 int space;
757 int c;
758 int rx_get = buf_info.rx_get;
759 int rx_put;
760
761#if defined(CONFIG_HW_WATCHDOG)
762 while (rx_get == buf_info.rx_put)
763 WATCHDOG_RESET ();
764#else
765 while (rx_get == buf_info.rx_put);
766#endif
767 c = buf_info.rx_buffer[rx_get++];
768 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
769 rx_get = 0;
770 buf_info.rx_get = rx_get;
771
772 rx_put = buf_info.rx_put;
773 if (rx_get <= rx_put) {
774 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
775 } else {
776 space = rx_get - rx_put;
777 }
778 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
779 /* Start flow by setting RTS active */
8749cfb4 780 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806
WD		 781 }
782
783 return c;
784}
785
786int serial_buffered_tstc (void)
787{
788 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
789}
790
791#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
792
fe8c2806
WD		 793#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
794/*
795 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
796 number 0 or number 1
797 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
798 configuration has been already done
799 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
800 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
801*/
802#if (CONFIG_KGDB_SER_INDEX & 2)
803void kgdb_serial_init (void)
804{
fe8c2806
WD		 805 volatile char val;
806 unsigned short br_reg;
807
808 get_clocks ();
809 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
810 5) / 10;
811 /*
812 * Init onboard 16550 UART
813 */
8749cfb4
SR		 814 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
815 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
816 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
817 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
818 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
819 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
820 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
821 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
822 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
823 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
fe8c2806
WD		 824}
825
fe8c2806
WD		 826void putDebugChar (const char c)
827{
828 if (c == '\n')
829 serial_putc ('\r');
830
8749cfb4 831 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
fe8c2806
WD		 832
833 /* check THRE bit, wait for transfer done */
8749cfb4 834 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
fe8c2806
WD		 835}
836
fe8c2806
WD		 837void putDebugStr (const char *s)
838{
839 while (*s) {
840 serial_putc (*s++);
841 }
842}
843
fe8c2806
WD		 844int getDebugChar (void)
845{
846 unsigned char status = 0;
847
848 while (1) {
8749cfb4 849 status = in8 (ACTING_UART1_BASE + UART_LSR);
fe8c2806
WD		 850 if ((status & asyncLSRDataReady1) != 0x0) {
851 break;
852 }
853 if ((status & ( asyncLSRFramingError1 |
854 asyncLSROverrunError1 |
855 asyncLSRParityError1 |
856 asyncLSRBreakInterrupt1 )) != 0) {
8749cfb4 857 out8 (ACTING_UART1_BASE + UART_LSR,
fe8c2806
WD		 858 asyncLSRFramingError1 |
859 asyncLSROverrunError1 |
860 asyncLSRParityError1 |
861 asyncLSRBreakInterrupt1);
862 }
863 }
8749cfb4 864 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
fe8c2806
WD		 865}
866
fe8c2806
WD		 867void kgdb_interruptible (int yes)
868{
869 return;
870}
871
872#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
873
874void kgdb_serial_init (void)
875{
876 serial_printf ("[on serial] ");
877}
878
879void putDebugChar (int c)
880{
881 serial_putc (c);
882}
883
884void putDebugStr (const char *str)
885{
886 serial_puts (str);
887}
888
889int getDebugChar (void)
890{
891 return serial_getc ();
892}
893
894void kgdb_interruptible (int yes)
895{
896 return;
897}
898#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
899#endif /* CFG_CMD_KGDB */
900
ff36fd85
WD		 901
902#if defined(CONFIG_SERIAL_MULTI)
903int serial0_init(void)
904{
905 return (serial_init_dev(UART0_BASE));
906}
907
908int serial1_init(void)
909{
910 return (serial_init_dev(UART1_BASE));
911}
912void serial0_setbrg (void)
913{
914 serial_setbrg_dev(UART0_BASE);
915}
916void serial1_setbrg (void)
917{
918 serial_setbrg_dev(UART1_BASE);
919}
920
921void serial0_putc(const char c)
922{
923 serial_putc_dev(UART0_BASE,c);
924}
925
926void serial1_putc(const char c)
927{
928 serial_putc_dev(UART1_BASE, c);
929}
930void serial0_puts(const char *s)
931{
932 serial_puts_dev(UART0_BASE, s);
933}
934
935void serial1_puts(const char *s)
936{
937 serial_puts_dev(UART1_BASE, s);
938}
939
940int serial0_getc(void)
941{
942 return(serial_getc_dev(UART0_BASE));
943}
944
945int serial1_getc(void)
946{
947 return(serial_getc_dev(UART1_BASE));
948}
949int serial0_tstc(void)
950{
951 return (serial_tstc_dev(UART0_BASE));
952}
953
954int serial1_tstc(void)
955{
956 return (serial_tstc_dev(UART1_BASE));
957}
958
959struct serial_device serial0_device =
960{
961 "serial0",
962 "UART0",
963 serial0_init,
964 serial0_setbrg,
965 serial0_getc,
966 serial0_tstc,
967 serial0_putc,
968 serial0_puts,
969};
970
971struct serial_device serial1_device =
972{
973 "serial1",
974 "UART1",
975 serial1_init,
976 serial1_setbrg,
977 serial1_getc,
978 serial1_tstc,
979 serial1_putc,
980 serial1_puts,
981};
982#endif /* CONFIG_SERIAL_MULTI */
983
fe8c2806 984#endif /* CONFIG_405GP || CONFIG_405CR */
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