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0442ed86 WD |
1 | /* |
2 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> | |
3 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> | |
4 | * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> | |
3cb86f3e | 5 | * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering |
c821b5f1 GE |
6 | * Copyright (c) 2008 Nuovation System Designs, LLC |
7 | * Grant Erickson <gerickson@nuovations.com> | |
0442ed86 WD |
8 | * |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
83b4cfa3 WD |
27 | /*------------------------------------------------------------------------------+ |
28 | * | |
29 | * This source code has been made available to you by IBM on an AS-IS | |
30 | * basis. Anyone receiving this source is licensed under IBM | |
31 | * copyrights to use it in any way he or she deems fit, including | |
32 | * copying it, modifying it, compiling it, and redistributing it either | |
33 | * with or without modifications. No license under IBM patents or | |
34 | * patent applications is to be implied by the copyright license. | |
35 | * | |
36 | * Any user of this software should understand that IBM cannot provide | |
37 | * technical support for this software and will not be responsible for | |
38 | * any consequences resulting from the use of this software. | |
39 | * | |
40 | * Any person who transfers this source code or any derivative work | |
41 | * must include the IBM copyright notice, this paragraph, and the | |
42 | * preceding two paragraphs in the transferred software. | |
43 | * | |
44 | * COPYRIGHT I B M CORPORATION 1995 | |
45 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
46 | *------------------------------------------------------------------------------- | |
47 | */ | |
0442ed86 | 48 | |
0c8721a4 | 49 | /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards |
0442ed86 WD |
50 | * |
51 | * | |
52 | * The processor starts at 0xfffffffc and the code is executed | |
53 | * from flash/rom. | |
54 | * in memory, but as long we don't jump around before relocating. | |
55 | * board_init lies at a quite high address and when the cpu has | |
56 | * jumped there, everything is ok. | |
57 | * This works because the cpu gives the FLASH (CS0) the whole | |
58 | * address space at startup, and board_init lies as a echo of | |
59 | * the flash somewhere up there in the memorymap. | |
60 | * | |
61 | * board_init will change CS0 to be positioned at the correct | |
62 | * address and (s)dram will be positioned at address 0 | |
63 | */ | |
64 | #include <config.h> | |
0442ed86 WD |
65 | #include <ppc4xx.h> |
66 | #include <version.h> | |
67 | ||
68 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
69 | ||
70 | #include <ppc_asm.tmpl> | |
71 | #include <ppc_defs.h> | |
72 | ||
73 | #include <asm/cache.h> | |
74 | #include <asm/mmu.h> | |
75 | ||
76 | #ifndef CONFIG_IDENT_STRING | |
77 | #define CONFIG_IDENT_STRING "" | |
78 | #endif | |
79 | ||
6d0f6bcf JCPV |
80 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
81 | # if (CONFIG_SYS_INIT_DCACHE_CS == 0) | |
0442ed86 WD |
82 | # define PBxAP pb0ap |
83 | # define PBxCR pb0cr | |
6d0f6bcf JCPV |
84 | # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) |
85 | # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP | |
86 | # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR | |
c821b5f1 | 87 | # endif |
0442ed86 | 88 | # endif |
6d0f6bcf | 89 | # if (CONFIG_SYS_INIT_DCACHE_CS == 1) |
0442ed86 WD |
90 | # define PBxAP pb1ap |
91 | # define PBxCR pb1cr | |
6d0f6bcf JCPV |
92 | # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) |
93 | # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP | |
94 | # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR | |
c821b5f1 | 95 | # endif |
0442ed86 | 96 | # endif |
6d0f6bcf | 97 | # if (CONFIG_SYS_INIT_DCACHE_CS == 2) |
0442ed86 WD |
98 | # define PBxAP pb2ap |
99 | # define PBxCR pb2cr | |
6d0f6bcf JCPV |
100 | # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) |
101 | # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP | |
102 | # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR | |
c821b5f1 | 103 | # endif |
0442ed86 | 104 | # endif |
6d0f6bcf | 105 | # if (CONFIG_SYS_INIT_DCACHE_CS == 3) |
0442ed86 WD |
106 | # define PBxAP pb3ap |
107 | # define PBxCR pb3cr | |
6d0f6bcf JCPV |
108 | # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) |
109 | # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP | |
110 | # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR | |
c821b5f1 | 111 | # endif |
0442ed86 | 112 | # endif |
6d0f6bcf | 113 | # if (CONFIG_SYS_INIT_DCACHE_CS == 4) |
0442ed86 WD |
114 | # define PBxAP pb4ap |
115 | # define PBxCR pb4cr | |
6d0f6bcf JCPV |
116 | # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) |
117 | # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP | |
118 | # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR | |
c821b5f1 | 119 | # endif |
0442ed86 | 120 | # endif |
6d0f6bcf | 121 | # if (CONFIG_SYS_INIT_DCACHE_CS == 5) |
0442ed86 WD |
122 | # define PBxAP pb5ap |
123 | # define PBxCR pb5cr | |
6d0f6bcf JCPV |
124 | # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) |
125 | # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP | |
126 | # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR | |
c821b5f1 | 127 | # endif |
0442ed86 | 128 | # endif |
6d0f6bcf | 129 | # if (CONFIG_SYS_INIT_DCACHE_CS == 6) |
0442ed86 WD |
130 | # define PBxAP pb6ap |
131 | # define PBxCR pb6cr | |
6d0f6bcf JCPV |
132 | # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) |
133 | # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP | |
134 | # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR | |
c821b5f1 | 135 | # endif |
0442ed86 | 136 | # endif |
6d0f6bcf | 137 | # if (CONFIG_SYS_INIT_DCACHE_CS == 7) |
0442ed86 WD |
138 | # define PBxAP pb7ap |
139 | # define PBxCR pb7cr | |
6d0f6bcf JCPV |
140 | # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) |
141 | # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP | |
142 | # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR | |
c821b5f1 GE |
143 | # endif |
144 | # endif | |
145 | # ifndef PBxAP_VAL | |
146 | # define PBxAP_VAL 0 | |
147 | # endif | |
148 | # ifndef PBxCR_VAL | |
149 | # define PBxCR_VAL 0 | |
150 | # endif | |
151 | /* | |
6d0f6bcf | 152 | * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB |
c821b5f1 GE |
153 | * used as temporary stack pointer for the primordial stack |
154 | */ | |
6d0f6bcf JCPV |
155 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR |
156 | # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ | |
c821b5f1 GE |
157 | EBC_BXAP_TWT_ENCODE(7) | \ |
158 | EBC_BXAP_BCE_DISABLE | \ | |
159 | EBC_BXAP_BCT_2TRANS | \ | |
160 | EBC_BXAP_CSN_ENCODE(0) | \ | |
161 | EBC_BXAP_OEN_ENCODE(0) | \ | |
162 | EBC_BXAP_WBN_ENCODE(0) | \ | |
163 | EBC_BXAP_WBF_ENCODE(0) | \ | |
164 | EBC_BXAP_TH_ENCODE(2) | \ | |
165 | EBC_BXAP_RE_DISABLED | \ | |
166 | EBC_BXAP_SOR_NONDELAYED | \ | |
167 | EBC_BXAP_BEM_WRITEONLY | \ | |
168 | EBC_BXAP_PEN_DISABLED) | |
6d0f6bcf JCPV |
169 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ |
170 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR | |
171 | # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ | |
c821b5f1 GE |
172 | EBC_BXCR_BS_64MB | \ |
173 | EBC_BXCR_BU_RW | \ | |
174 | EBC_BXCR_BW_16BIT) | |
6d0f6bcf JCPV |
175 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ |
176 | # ifndef CONFIG_SYS_INIT_RAM_PATTERN | |
177 | # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD | |
0442ed86 | 178 | # endif |
6d0f6bcf | 179 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 180 | |
6d0f6bcf JCPV |
181 | #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10))) |
182 | #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END! | |
28d77d96 SR |
183 | #endif |
184 | ||
c821b5f1 GE |
185 | /* |
186 | * Unless otherwise overriden, enable two 128MB cachable instruction regions | |
6d0f6bcf JCPV |
187 | * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering |
188 | * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. | |
c821b5f1 | 189 | */ |
6d0f6bcf | 190 | #if !defined(CONFIG_SYS_FLASH_BASE) |
64852d09 | 191 | /* If not already defined, set it to the "last" 128MByte region */ |
6d0f6bcf | 192 | # define CONFIG_SYS_FLASH_BASE 0xf8000000 |
64852d09 | 193 | #endif |
6d0f6bcf JCPV |
194 | #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) |
195 | # define CONFIG_SYS_ICACHE_SACR_VALUE \ | |
196 | (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ | |
197 | PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ | |
198 | PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) | |
199 | #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ | |
200 | ||
201 | #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) | |
202 | # define CONFIG_SYS_DCACHE_SACR_VALUE \ | |
c821b5f1 | 203 | (0x00000000) |
6d0f6bcf | 204 | #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ |
c821b5f1 | 205 | |
83b4cfa3 | 206 | #define function_prolog(func_name) .text; \ |
cf959c7d SR |
207 | .align 2; \ |
208 | .globl func_name; \ | |
209 | func_name: | |
83b4cfa3 | 210 | #define function_epilog(func_name) .type func_name,@function; \ |
cf959c7d SR |
211 | .size func_name,.-func_name |
212 | ||
0442ed86 WD |
213 | /* We don't want the MMU yet. |
214 | */ | |
215 | #undef MSR_KERNEL | |
216 | #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ | |
217 | ||
218 | ||
219 | .extern ext_bus_cntlr_init | |
887e2ec9 SR |
220 | #ifdef CONFIG_NAND_U_BOOT |
221 | .extern reconfig_tlb0 | |
222 | #endif | |
0442ed86 WD |
223 | |
224 | /* | |
225 | * Set up GOT: Global Offset Table | |
226 | * | |
227 | * Use r14 to access the GOT | |
228 | */ | |
887e2ec9 | 229 | #if !defined(CONFIG_NAND_SPL) |
0442ed86 WD |
230 | START_GOT |
231 | GOT_ENTRY(_GOT2_TABLE_) | |
232 | GOT_ENTRY(_FIXUP_TABLE_) | |
233 | ||
234 | GOT_ENTRY(_start) | |
235 | GOT_ENTRY(_start_of_vectors) | |
236 | GOT_ENTRY(_end_of_vectors) | |
237 | GOT_ENTRY(transfer_to_handler) | |
238 | ||
3b57fe0a | 239 | GOT_ENTRY(__init_end) |
0442ed86 | 240 | GOT_ENTRY(_end) |
5d232d0e | 241 | GOT_ENTRY(__bss_start) |
0442ed86 | 242 | END_GOT |
887e2ec9 SR |
243 | #endif /* CONFIG_NAND_SPL */ |
244 | ||
245 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
246 | /* | |
247 | * NAND U-Boot image is started from offset 0 | |
248 | */ | |
249 | .text | |
c440bfe6 | 250 | #if defined(CONFIG_440) |
887e2ec9 | 251 | bl reconfig_tlb0 |
c440bfe6 | 252 | #endif |
887e2ec9 SR |
253 | GET_GOT |
254 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ | |
255 | bl board_init_f | |
256 | #endif | |
0442ed86 WD |
257 | |
258 | /* | |
259 | * 440 Startup -- on reset only the top 4k of the effective | |
260 | * address space is mapped in by an entry in the instruction | |
261 | * and data shadow TLB. The .bootpg section is located in the | |
262 | * top 4k & does only what's necessary to map in the the rest | |
263 | * of the boot rom. Once the boot rom is mapped in we can | |
264 | * proceed with normal startup. | |
265 | * | |
266 | * NOTE: CS0 only covers the top 2MB of the effective address | |
267 | * space after reset. | |
268 | */ | |
269 | ||
270 | #if defined(CONFIG_440) | |
887e2ec9 | 271 | #if !defined(CONFIG_NAND_SPL) |
0442ed86 | 272 | .section .bootpg,"ax" |
887e2ec9 | 273 | #endif |
0442ed86 WD |
274 | .globl _start_440 |
275 | ||
276 | /**************************************************************************/ | |
277 | _start_440: | |
511d0c72 WD |
278 | /*--------------------------------------------------------------------+ |
279 | | 440EPX BUP Change - Hardware team request | |
280 | +--------------------------------------------------------------------*/ | |
887e2ec9 SR |
281 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
282 | sync | |
283 | nop | |
284 | nop | |
285 | #endif | |
6c5879f3 MB |
286 | /*----------------------------------------------------------------+ |
287 | | Core bug fix. Clear the esr | |
288 | +-----------------------------------------------------------------*/ | |
edd6cf20 | 289 | li r0,0 |
b87dfd28 | 290 | mtspr esr,r0 |
0442ed86 WD |
291 | /*----------------------------------------------------------------*/ |
292 | /* Clear and set up some registers. */ | |
293 | /*----------------------------------------------------------------*/ | |
f901a83b WD |
294 | iccci r0,r0 /* NOTE: operands not used for 440 */ |
295 | dccci r0,r0 /* NOTE: operands not used for 440 */ | |
0442ed86 WD |
296 | sync |
297 | li r0,0 | |
298 | mtspr srr0,r0 | |
299 | mtspr srr1,r0 | |
300 | mtspr csrr0,r0 | |
301 | mtspr csrr1,r0 | |
887e2ec9 SR |
302 | /* NOTE: 440GX adds machine check status regs */ |
303 | #if defined(CONFIG_440) && !defined(CONFIG_440GP) | |
f901a83b WD |
304 | mtspr mcsrr0,r0 |
305 | mtspr mcsrr1,r0 | |
887e2ec9 | 306 | mfspr r1,mcsr |
f901a83b | 307 | mtspr mcsr,r1 |
ba56f625 | 308 | #endif |
20532833 SR |
309 | |
310 | /*----------------------------------------------------------------*/ | |
311 | /* CCR0 init */ | |
312 | /*----------------------------------------------------------------*/ | |
313 | /* Disable store gathering & broadcast, guarantee inst/data | |
314 | * cache block touch, force load/store alignment | |
315 | * (see errata 1.12: 440_33) | |
316 | */ | |
317 | lis r1,0x0030 /* store gathering & broadcast disable */ | |
318 | ori r1,r1,0x6000 /* cache touch */ | |
319 | mtspr ccr0,r1 | |
320 | ||
0442ed86 WD |
321 | /*----------------------------------------------------------------*/ |
322 | /* Initialize debug */ | |
323 | /*----------------------------------------------------------------*/ | |
887e2ec9 SR |
324 | mfspr r1,dbcr0 |
325 | andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ | |
326 | bne skip_debug_init /* if set, don't clear debug register */ | |
0442ed86 WD |
327 | mtspr dbcr0,r0 |
328 | mtspr dbcr1,r0 | |
329 | mtspr dbcr2,r0 | |
330 | mtspr iac1,r0 | |
331 | mtspr iac2,r0 | |
332 | mtspr iac3,r0 | |
333 | mtspr dac1,r0 | |
334 | mtspr dac2,r0 | |
335 | mtspr dvc1,r0 | |
336 | mtspr dvc2,r0 | |
337 | ||
338 | mfspr r1,dbsr | |
339 | mtspr dbsr,r1 /* Clear all valid bits */ | |
887e2ec9 | 340 | skip_debug_init: |
0442ed86 | 341 | |
6c5879f3 MB |
342 | #if defined (CONFIG_440SPE) |
343 | /*----------------------------------------------------------------+ | |
344 | | Initialize Core Configuration Reg1. | |
345 | | a. ICDPEI: Record even parity. Normal operation. | |
346 | | b. ICTPEI: Record even parity. Normal operation. | |
347 | | c. DCTPEI: Record even parity. Normal operation. | |
348 | | d. DCDPEI: Record even parity. Normal operation. | |
349 | | e. DCUPEI: Record even parity. Normal operation. | |
350 | | f. DCMPEI: Record even parity. Normal operation. | |
351 | | g. FCOM: Normal operation | |
352 | | h. MMUPEI: Record even parity. Normal operation. | |
353 | | i. FFF: Flush only as much data as necessary. | |
edd6cf20 | 354 | | j. TCS: Timebase increments from CPU clock. |
6c5879f3 | 355 | +-----------------------------------------------------------------*/ |
edd6cf20 | 356 | li r0,0 |
6c5879f3 MB |
357 | mtspr ccr1, r0 |
358 | ||
359 | /*----------------------------------------------------------------+ | |
360 | | Reset the timebase. | |
361 | | The previous write to CCR1 sets the timebase source. | |
362 | +-----------------------------------------------------------------*/ | |
6c5879f3 MB |
363 | mtspr tbl, r0 |
364 | mtspr tbu, r0 | |
365 | #endif | |
366 | ||
0442ed86 WD |
367 | /*----------------------------------------------------------------*/ |
368 | /* Setup interrupt vectors */ | |
369 | /*----------------------------------------------------------------*/ | |
370 | mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */ | |
f901a83b | 371 | li r1,0x0100 |
0442ed86 | 372 | mtspr ivor0,r1 /* Critical input */ |
f901a83b | 373 | li r1,0x0200 |
0442ed86 | 374 | mtspr ivor1,r1 /* Machine check */ |
f901a83b | 375 | li r1,0x0300 |
0442ed86 | 376 | mtspr ivor2,r1 /* Data storage */ |
f901a83b | 377 | li r1,0x0400 |
0442ed86 WD |
378 | mtspr ivor3,r1 /* Instruction storage */ |
379 | li r1,0x0500 | |
380 | mtspr ivor4,r1 /* External interrupt */ | |
381 | li r1,0x0600 | |
382 | mtspr ivor5,r1 /* Alignment */ | |
383 | li r1,0x0700 | |
384 | mtspr ivor6,r1 /* Program check */ | |
385 | li r1,0x0800 | |
386 | mtspr ivor7,r1 /* Floating point unavailable */ | |
387 | li r1,0x0c00 | |
388 | mtspr ivor8,r1 /* System call */ | |
efa35cf1 | 389 | li r1,0x0a00 |
83b4cfa3 | 390 | mtspr ivor9,r1 /* Auxiliary Processor unavailable */ |
efa35cf1 GB |
391 | li r1,0x0900 |
392 | mtspr ivor10,r1 /* Decrementer */ | |
0442ed86 | 393 | li r1,0x1300 |
efa35cf1 GB |
394 | mtspr ivor13,r1 /* Data TLB error */ |
395 | li r1,0x1400 | |
0442ed86 WD |
396 | mtspr ivor14,r1 /* Instr TLB error */ |
397 | li r1,0x2000 | |
398 | mtspr ivor15,r1 /* Debug */ | |
399 | ||
400 | /*----------------------------------------------------------------*/ | |
401 | /* Configure cache regions */ | |
402 | /*----------------------------------------------------------------*/ | |
403 | mtspr inv0,r0 | |
404 | mtspr inv1,r0 | |
405 | mtspr inv2,r0 | |
406 | mtspr inv3,r0 | |
407 | mtspr dnv0,r0 | |
408 | mtspr dnv1,r0 | |
409 | mtspr dnv2,r0 | |
410 | mtspr dnv3,r0 | |
411 | mtspr itv0,r0 | |
412 | mtspr itv1,r0 | |
413 | mtspr itv2,r0 | |
414 | mtspr itv3,r0 | |
415 | mtspr dtv0,r0 | |
416 | mtspr dtv1,r0 | |
417 | mtspr dtv2,r0 | |
418 | mtspr dtv3,r0 | |
419 | ||
420 | /*----------------------------------------------------------------*/ | |
421 | /* Cache victim limits */ | |
422 | /*----------------------------------------------------------------*/ | |
423 | /* floors 0, ceiling max to use the entire cache -- nothing locked | |
424 | */ | |
425 | lis r1,0x0001 | |
426 | ori r1,r1,0xf800 | |
427 | mtspr ivlim,r1 | |
428 | mtspr dvlim,r1 | |
429 | ||
6c5879f3 MB |
430 | /*----------------------------------------------------------------+ |
431 | |Initialize MMUCR[STID] = 0. | |
432 | +-----------------------------------------------------------------*/ | |
433 | mfspr r0,mmucr | |
434 | addis r1,0,0xFFFF | |
435 | ori r1,r1,0xFF00 | |
436 | and r0,r0,r1 | |
437 | mtspr mmucr,r0 | |
438 | ||
0442ed86 WD |
439 | /*----------------------------------------------------------------*/ |
440 | /* Clear all TLB entries -- TID = 0, TS = 0 */ | |
441 | /*----------------------------------------------------------------*/ | |
6c5879f3 | 442 | addis r0,0,0x0000 |
0442ed86 WD |
443 | li r1,0x003f /* 64 TLB entries */ |
444 | mtctr r1 | |
6c5879f3 MB |
445 | rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ |
446 | tlbwe r0,r1,0x0001 | |
447 | tlbwe r0,r1,0x0002 | |
0442ed86 | 448 | subi r1,r1,0x0001 |
6c5879f3 | 449 | bdnz rsttlb |
0442ed86 WD |
450 | |
451 | /*----------------------------------------------------------------*/ | |
452 | /* TLB entry setup -- step thru tlbtab */ | |
453 | /*----------------------------------------------------------------*/ | |
692519b1 RJ |
454 | #if defined(CONFIG_440SPE) |
455 | /*----------------------------------------------------------------*/ | |
456 | /* We have different TLB tables for revA and rev B of 440SPe */ | |
457 | /*----------------------------------------------------------------*/ | |
458 | mfspr r1, PVR | |
459 | lis r0,0x5342 | |
460 | ori r0,r0,0x1891 | |
461 | cmpw r7,r1,r0 | |
462 | bne r7,..revA | |
463 | bl tlbtabB | |
464 | b ..goon | |
465 | ..revA: | |
466 | bl tlbtabA | |
467 | ..goon: | |
468 | #else | |
0442ed86 | 469 | bl tlbtab /* Get tlbtab pointer */ |
692519b1 | 470 | #endif |
0442ed86 WD |
471 | mr r5,r0 |
472 | li r1,0x003f /* 64 TLB entries max */ | |
473 | mtctr r1 | |
474 | li r4,0 /* TLB # */ | |
475 | ||
476 | addi r5,r5,-4 | |
477 | 1: lwzu r0,4(r5) | |
478 | cmpwi r0,0 | |
479 | beq 2f /* 0 marks end */ | |
480 | lwzu r1,4(r5) | |
481 | lwzu r2,4(r5) | |
482 | tlbwe r0,r4,0 /* TLB Word 0 */ | |
483 | tlbwe r1,r4,1 /* TLB Word 1 */ | |
484 | tlbwe r2,r4,2 /* TLB Word 2 */ | |
485 | addi r4,r4,1 /* Next TLB */ | |
486 | bdnz 1b | |
487 | ||
488 | /*----------------------------------------------------------------*/ | |
489 | /* Continue from 'normal' start */ | |
490 | /*----------------------------------------------------------------*/ | |
887e2ec9 | 491 | 2: |
887e2ec9 | 492 | bl 3f |
0442ed86 WD |
493 | b _start |
494 | ||
495 | 3: li r0,0 | |
496 | mtspr srr1,r0 /* Keep things disabled for now */ | |
497 | mflr r1 | |
498 | mtspr srr0,r1 | |
499 | rfi | |
b867d705 | 500 | #endif /* CONFIG_440 */ |
0442ed86 WD |
501 | |
502 | /* | |
503 | * r3 - 1st arg to board_init(): IMMP pointer | |
504 | * r4 - 2nd arg to board_init(): boot flag | |
505 | */ | |
887e2ec9 | 506 | #ifndef CONFIG_NAND_SPL |
0442ed86 WD |
507 | .text |
508 | .long 0x27051956 /* U-Boot Magic Number */ | |
509 | .globl version_string | |
510 | version_string: | |
511 | .ascii U_BOOT_VERSION | |
512 | .ascii " (", __DATE__, " - ", __TIME__, ")" | |
513 | .ascii CONFIG_IDENT_STRING, "\0" | |
514 | ||
0442ed86 | 515 | . = EXC_OFF_SYS_RESET |
efa35cf1 GB |
516 | .globl _start_of_vectors |
517 | _start_of_vectors: | |
518 | ||
519 | /* Critical input. */ | |
520 | CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) | |
521 | ||
522 | #ifdef CONFIG_440 | |
523 | /* Machine check */ | |
83b4cfa3 | 524 | MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 | 525 | #else |
83b4cfa3 | 526 | CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 GB |
527 | #endif /* CONFIG_440 */ |
528 | ||
529 | /* Data Storage exception. */ | |
530 | STD_EXCEPTION(0x300, DataStorage, UnknownException) | |
531 | ||
532 | /* Instruction Storage exception. */ | |
533 | STD_EXCEPTION(0x400, InstStorage, UnknownException) | |
534 | ||
535 | /* External Interrupt exception. */ | |
536 | STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) | |
537 | ||
538 | /* Alignment exception. */ | |
539 | . = 0x600 | |
540 | Alignment: | |
541 | EXCEPTION_PROLOG(SRR0, SRR1) | |
542 | mfspr r4,DAR | |
543 | stw r4,_DAR(r21) | |
544 | mfspr r5,DSISR | |
545 | stw r5,_DSISR(r21) | |
546 | addi r3,r1,STACK_FRAME_OVERHEAD | |
547 | li r20,MSR_KERNEL | |
548 | rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ | |
549 | lwz r6,GOT(transfer_to_handler) | |
550 | mtlr r6 | |
551 | blrl | |
552 | .L_Alignment: | |
553 | .long AlignmentException - _start + _START_OFFSET | |
554 | .long int_return - _start + _START_OFFSET | |
555 | ||
556 | /* Program check exception */ | |
557 | . = 0x700 | |
558 | ProgramCheck: | |
559 | EXCEPTION_PROLOG(SRR0, SRR1) | |
560 | addi r3,r1,STACK_FRAME_OVERHEAD | |
561 | li r20,MSR_KERNEL | |
562 | rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ | |
563 | lwz r6,GOT(transfer_to_handler) | |
564 | mtlr r6 | |
565 | blrl | |
566 | .L_ProgramCheck: | |
567 | .long ProgramCheckException - _start + _START_OFFSET | |
568 | .long int_return - _start + _START_OFFSET | |
569 | ||
570 | #ifdef CONFIG_440 | |
571 | STD_EXCEPTION(0x800, FPUnavailable, UnknownException) | |
572 | STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) | |
573 | STD_EXCEPTION(0xa00, APU, UnknownException) | |
df8a24cd | 574 | #endif |
efa35cf1 GB |
575 | STD_EXCEPTION(0xc00, SystemCall, UnknownException) |
576 | ||
577 | #ifdef CONFIG_440 | |
578 | STD_EXCEPTION(0x1300, DataTLBError, UnknownException) | |
579 | STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) | |
580 | #else | |
581 | STD_EXCEPTION(0x1000, PIT, DecrementerPITException) | |
582 | STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) | |
583 | STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) | |
584 | #endif | |
585 | CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) | |
586 | ||
587 | .globl _end_of_vectors | |
588 | _end_of_vectors: | |
589 | . = _START_OFFSET | |
887e2ec9 | 590 | #endif |
0442ed86 WD |
591 | .globl _start |
592 | _start: | |
593 | ||
594 | /*****************************************************************************/ | |
595 | #if defined(CONFIG_440) | |
596 | ||
597 | /*----------------------------------------------------------------*/ | |
598 | /* Clear and set up some registers. */ | |
599 | /*----------------------------------------------------------------*/ | |
600 | li r0,0x0000 | |
601 | lis r1,0xffff | |
602 | mtspr dec,r0 /* prevent dec exceptions */ | |
603 | mtspr tbl,r0 /* prevent fit & wdt exceptions */ | |
604 | mtspr tbu,r0 | |
605 | mtspr tsr,r1 /* clear all timer exception status */ | |
606 | mtspr tcr,r0 /* disable all */ | |
607 | mtspr esr,r0 /* clear exception syndrome register */ | |
608 | mtxer r0 /* clear integer exception register */ | |
0442ed86 WD |
609 | |
610 | /*----------------------------------------------------------------*/ | |
611 | /* Debug setup -- some (not very good) ice's need an event*/ | |
6d0f6bcf | 612 | /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ |
0442ed86 WD |
613 | /* value you need in this case 0x8cff 0000 should do the trick */ |
614 | /*----------------------------------------------------------------*/ | |
6d0f6bcf | 615 | #if defined(CONFIG_SYS_INIT_DBCR) |
0442ed86 WD |
616 | lis r1,0xffff |
617 | ori r1,r1,0xffff | |
618 | mtspr dbsr,r1 /* Clear all status bits */ | |
6d0f6bcf JCPV |
619 | lis r0,CONFIG_SYS_INIT_DBCR@h |
620 | ori r0,r0,CONFIG_SYS_INIT_DBCR@l | |
0442ed86 WD |
621 | mtspr dbcr0,r0 |
622 | isync | |
623 | #endif | |
624 | ||
625 | /*----------------------------------------------------------------*/ | |
626 | /* Setup the internal SRAM */ | |
627 | /*----------------------------------------------------------------*/ | |
628 | li r0,0 | |
887e2ec9 | 629 | |
6d0f6bcf | 630 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
c157d8e2 | 631 | /* Clear Dcache to use as RAM */ |
6d0f6bcf JCPV |
632 | addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h |
633 | ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l | |
634 | addis r4,r0,CONFIG_SYS_INIT_RAM_END@h | |
635 | ori r4,r4,CONFIG_SYS_INIT_RAM_END@l | |
c157d8e2 | 636 | rlwinm. r5,r4,0,27,31 |
f901a83b WD |
637 | rlwinm r5,r4,27,5,31 |
638 | beq ..d_ran | |
639 | addi r5,r5,0x0001 | |
c157d8e2 | 640 | ..d_ran: |
f901a83b | 641 | mtctr r5 |
c157d8e2 | 642 | ..d_ag: |
f901a83b WD |
643 | dcbz r0,r3 |
644 | addi r3,r3,32 | |
645 | bdnz ..d_ag | |
e02c521d SR |
646 | |
647 | /* | |
648 | * Lock the init-ram/stack in d-cache, so that other regions | |
649 | * may use d-cache as well | |
650 | * Note, that this current implementation locks exactly 4k | |
651 | * of d-cache, so please make sure that you don't define a | |
652 | * bigger init-ram area. Take a look at the lwmon5 440EPx | |
653 | * implementation as a reference. | |
654 | */ | |
655 | msync | |
656 | isync | |
657 | /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ | |
658 | lis r1,0x0201 | |
659 | ori r1,r1,0xf808 | |
660 | mtspr dvlim,r1 | |
661 | lis r1,0x0808 | |
662 | ori r1,r1,0x0808 | |
663 | mtspr dnv0,r1 | |
664 | mtspr dnv1,r1 | |
665 | mtspr dnv2,r1 | |
666 | mtspr dnv3,r1 | |
667 | mtspr dtv0,r1 | |
668 | mtspr dtv1,r1 | |
669 | mtspr dtv2,r1 | |
670 | mtspr dtv3,r1 | |
671 | msync | |
672 | isync | |
6d0f6bcf | 673 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
887e2ec9 SR |
674 | |
675 | /* 440EP & 440GR are only 440er PPC's without internal SRAM */ | |
676 | #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) | |
677 | /* not all PPC's have internal SRAM usable as L2-cache */ | |
2801b2d2 SR |
678 | #if defined(CONFIG_440GX) || \ |
679 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ | |
7d307936 FK |
680 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
681 | defined(CONFIG_460SX) | |
f901a83b | 682 | mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ |
ba56f625 | 683 | #endif |
0442ed86 | 684 | |
887e2ec9 | 685 | lis r2,0x7fff |
0442ed86 WD |
686 | ori r2,r2,0xffff |
687 | mfdcr r1,isram0_dpc | |
688 | and r1,r1,r2 /* Disable parity check */ | |
689 | mtdcr isram0_dpc,r1 | |
690 | mfdcr r1,isram0_pmeg | |
887e2ec9 | 691 | and r1,r1,r2 /* Disable pwr mgmt */ |
0442ed86 WD |
692 | mtdcr isram0_pmeg,r1 |
693 | ||
694 | lis r1,0x8000 /* BAS = 8000_0000 */ | |
6e7fb6ea | 695 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) |
ba56f625 | 696 | ori r1,r1,0x0980 /* first 64k */ |
f901a83b | 697 | mtdcr isram0_sb0cr,r1 |
ba56f625 WD |
698 | lis r1,0x8001 |
699 | ori r1,r1,0x0980 /* second 64k */ | |
f901a83b | 700 | mtdcr isram0_sb1cr,r1 |
ba56f625 WD |
701 | lis r1, 0x8002 |
702 | ori r1,r1, 0x0980 /* third 64k */ | |
f901a83b | 703 | mtdcr isram0_sb2cr,r1 |
ba56f625 WD |
704 | lis r1, 0x8003 |
705 | ori r1,r1, 0x0980 /* fourth 64k */ | |
f901a83b | 706 | mtdcr isram0_sb3cr,r1 |
6c5879f3 MB |
707 | #elif defined(CONFIG_440SPE) |
708 | lis r1,0x0000 /* BAS = 0000_0000 */ | |
709 | ori r1,r1,0x0984 /* first 64k */ | |
710 | mtdcr isram0_sb0cr,r1 | |
711 | lis r1,0x0001 | |
712 | ori r1,r1,0x0984 /* second 64k */ | |
713 | mtdcr isram0_sb1cr,r1 | |
714 | lis r1, 0x0002 | |
715 | ori r1,r1, 0x0984 /* third 64k */ | |
716 | mtdcr isram0_sb2cr,r1 | |
717 | lis r1, 0x0003 | |
718 | ori r1,r1, 0x0984 /* fourth 64k */ | |
719 | mtdcr isram0_sb3cr,r1 | |
2801b2d2 SR |
720 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) |
721 | lis r1,0x4000 /* BAS = 8000_0000 */ | |
722 | ori r1,r1,0x4580 /* 16k */ | |
723 | mtdcr isram0_sb0cr,r1 | |
7d307936 FK |
724 | #elif defined(CONFIG_460SX) |
725 | lis r1,0x0000 /* BAS = 0000_0000 */ | |
726 | ori r1,r1,0x0B84 /* first 128k */ | |
727 | mtdcr isram0_sb0cr,r1 | |
728 | lis r1,0x0001 | |
729 | ori r1,r1,0x0B84 /* second 128k */ | |
730 | mtdcr isram0_sb1cr,r1 | |
731 | lis r1, 0x0002 | |
732 | ori r1,r1, 0x0B84 /* third 128k */ | |
733 | mtdcr isram0_sb2cr,r1 | |
734 | lis r1, 0x0003 | |
735 | ori r1,r1, 0x0B84 /* fourth 128k */ | |
736 | mtdcr isram0_sb3cr,r1 | |
887e2ec9 | 737 | #elif defined(CONFIG_440GP) |
0442ed86 WD |
738 | ori r1,r1,0x0380 /* 8k rw */ |
739 | mtdcr isram0_sb0cr,r1 | |
887e2ec9 | 740 | mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ |
c157d8e2 | 741 | #endif |
887e2ec9 | 742 | #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ |
0442ed86 WD |
743 | |
744 | /*----------------------------------------------------------------*/ | |
745 | /* Setup the stack in internal SRAM */ | |
746 | /*----------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
747 | lis r1,CONFIG_SYS_INIT_RAM_ADDR@h |
748 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l | |
0442ed86 WD |
749 | li r0,0 |
750 | stwu r0,-4(r1) | |
751 | stwu r0,-4(r1) /* Terminate call chain */ | |
752 | ||
753 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
754 | lis r0,RESET_VECTOR@h /* Address of reset vector */ | |
755 | ori r0,r0, RESET_VECTOR@l | |
756 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
757 | stw r0,+12(r1) /* Save return addr (underflow vect) */ | |
758 | ||
887e2ec9 | 759 | #ifdef CONFIG_NAND_SPL |
64852d09 | 760 | bl nand_boot_common /* will not return */ |
887e2ec9 | 761 | #else |
0442ed86 | 762 | GET_GOT |
5568e613 SR |
763 | |
764 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ | |
0442ed86 | 765 | bl board_init_f |
887e2ec9 | 766 | #endif |
0442ed86 WD |
767 | |
768 | #endif /* CONFIG_440 */ | |
769 | ||
770 | /*****************************************************************************/ | |
771 | #ifdef CONFIG_IOP480 | |
772 | /*----------------------------------------------------------------------- */ | |
773 | /* Set up some machine state registers. */ | |
774 | /*----------------------------------------------------------------------- */ | |
775 | addi r0,r0,0x0000 /* initialize r0 to zero */ | |
776 | mtspr esr,r0 /* clear Exception Syndrome Reg */ | |
777 | mttcr r0 /* timer control register */ | |
778 | mtexier r0 /* disable all interrupts */ | |
0442ed86 WD |
779 | addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ |
780 | ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ | |
781 | mtdbsr r4 /* clear/reset the dbsr */ | |
782 | mtexisr r4 /* clear all pending interrupts */ | |
783 | addis r4,r0,0x8000 | |
784 | mtexier r4 /* enable critical exceptions */ | |
785 | addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ | |
786 | ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ | |
787 | mtiocr r4 /* since bit not used) & DRC to latch */ | |
788 | /* data bus on rising edge of CAS */ | |
789 | /*----------------------------------------------------------------------- */ | |
790 | /* Clear XER. */ | |
791 | /*----------------------------------------------------------------------- */ | |
792 | mtxer r0 | |
793 | /*----------------------------------------------------------------------- */ | |
794 | /* Invalidate i-cache and d-cache TAG arrays. */ | |
795 | /*----------------------------------------------------------------------- */ | |
796 | addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ | |
797 | addi r4,0,1024 /* 1/4 of I-cache */ | |
798 | ..cloop: | |
799 | iccci 0,r3 | |
800 | iccci r4,r3 | |
801 | dccci 0,r3 | |
802 | addic. r3,r3,-16 /* move back one cache line */ | |
803 | bne ..cloop /* loop back to do rest until r3 = 0 */ | |
804 | ||
805 | /* */ | |
806 | /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ | |
807 | /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ | |
808 | /* */ | |
809 | ||
810 | /* first copy IOP480 register base address into r3 */ | |
811 | addis r3,0,0x5000 /* IOP480 register base address hi */ | |
812 | /* ori r3,r3,0x0000 / IOP480 register base address lo */ | |
813 | ||
814 | #ifdef CONFIG_ADCIOP | |
815 | /* use r4 as the working variable */ | |
816 | /* turn on CS3 (LOCCTL.7) */ | |
817 | lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
818 | andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ | |
819 | stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
820 | #endif | |
821 | ||
822 | #ifdef CONFIG_DASA_SIM | |
823 | /* use r4 as the working variable */ | |
824 | /* turn on MA17 (LOCCTL.7) */ | |
825 | lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
826 | ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ | |
827 | stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
828 | #endif | |
829 | ||
830 | /* turn on MA16..13 (LCS0BRD.12 = 0) */ | |
831 | lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ | |
832 | andi. r4,r4,0xefff /* make bit 12 = 0 */ | |
833 | stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ | |
834 | ||
835 | /* make sure above stores all comlete before going on */ | |
836 | sync | |
837 | ||
838 | /* last thing, set local init status done bit (DEVINIT.31) */ | |
839 | lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ | |
840 | oris r4,r4,0x8000 /* make bit 31 = 1 */ | |
841 | stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ | |
842 | ||
843 | /* clear all pending interrupts and disable all interrupts */ | |
844 | li r4,-1 /* set p1 to 0xffffffff */ | |
845 | stw r4,0x1b0(r3) /* clear all pending interrupts */ | |
846 | stw r4,0x1b8(r3) /* clear all pending interrupts */ | |
847 | li r4,0 /* set r4 to 0 */ | |
848 | stw r4,0x1b4(r3) /* disable all interrupts */ | |
849 | stw r4,0x1bc(r3) /* disable all interrupts */ | |
850 | ||
851 | /* make sure above stores all comlete before going on */ | |
852 | sync | |
853 | ||
c821b5f1 | 854 | /* Set-up icache cacheability. */ |
6d0f6bcf JCPV |
855 | lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h |
856 | ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l | |
c821b5f1 GE |
857 | mticcr r1 |
858 | isync | |
0442ed86 | 859 | |
c821b5f1 | 860 | /* Set-up dcache cacheability. */ |
6d0f6bcf JCPV |
861 | lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h |
862 | ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l | |
c821b5f1 | 863 | mtdccr r1 |
0442ed86 | 864 | |
6d0f6bcf JCPV |
865 | addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h |
866 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ | |
0442ed86 WD |
867 | li r0, 0 /* Make room for stack frame header and */ |
868 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
869 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
870 | ||
871 | GET_GOT /* initialize GOT access */ | |
872 | ||
873 | bl board_init_f /* run first part of init code (from Flash) */ | |
874 | ||
875 | #endif /* CONFIG_IOP480 */ | |
876 | ||
877 | /*****************************************************************************/ | |
e01bd218 SR |
878 | #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ |
879 | defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ | |
dbbd1257 | 880 | defined(CONFIG_405EX) || defined(CONFIG_405) |
0442ed86 WD |
881 | /*----------------------------------------------------------------------- */ |
882 | /* Clear and set up some registers. */ | |
883 | /*----------------------------------------------------------------------- */ | |
884 | addi r4,r0,0x0000 | |
dbbd1257 | 885 | #if !defined(CONFIG_405EX) |
0442ed86 | 886 | mtspr sgr,r4 |
dbbd1257 SR |
887 | #else |
888 | /* | |
889 | * On 405EX, completely clearing the SGR leads to PPC hangup | |
890 | * upon PCIe configuration access. The PCIe memory regions | |
891 | * need to be guarded! | |
892 | */ | |
893 | lis r3,0x0000 | |
894 | ori r3,r3,0x7FFC | |
895 | mtspr sgr,r3 | |
896 | #endif | |
0442ed86 WD |
897 | mtspr dcwr,r4 |
898 | mtesr r4 /* clear Exception Syndrome Reg */ | |
899 | mttcr r4 /* clear Timer Control Reg */ | |
900 | mtxer r4 /* clear Fixed-Point Exception Reg */ | |
901 | mtevpr r4 /* clear Exception Vector Prefix Reg */ | |
0442ed86 WD |
902 | addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ |
903 | /* dbsr is cleared by setting bits to 1) */ | |
904 | mtdbsr r4 /* clear/reset the dbsr */ | |
905 | ||
c821b5f1 | 906 | /* Invalidate the i- and d-caches. */ |
0442ed86 WD |
907 | bl invalidate_icache |
908 | bl invalidate_dcache | |
909 | ||
c821b5f1 | 910 | /* Set-up icache cacheability. */ |
6d0f6bcf JCPV |
911 | lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h |
912 | ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l | |
c821b5f1 | 913 | mticcr r4 |
0442ed86 WD |
914 | isync |
915 | ||
c821b5f1 | 916 | /* Set-up dcache cacheability. */ |
6d0f6bcf JCPV |
917 | lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h |
918 | ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l | |
c821b5f1 | 919 | mtdccr r4 |
0442ed86 | 920 | |
6d0f6bcf | 921 | #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) |
0442ed86 WD |
922 | /*----------------------------------------------------------------------- */ |
923 | /* Tune the speed and size for flash CS0 */ | |
924 | /*----------------------------------------------------------------------- */ | |
925 | bl ext_bus_cntlr_init | |
926 | #endif | |
64852d09 | 927 | |
6d0f6bcf | 928 | #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) |
dbbd1257 | 929 | /* |
c821b5f1 GE |
930 | * For boards that don't have OCM and can't use the data cache |
931 | * for their primordial stack, setup stack here directly after the | |
932 | * SDRAM is initialized in ext_bus_cntlr_init. | |
dbbd1257 | 933 | */ |
6d0f6bcf JCPV |
934 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
935 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ | |
dbbd1257 SR |
936 | |
937 | li r0, 0 /* Make room for stack frame header and */ | |
938 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
939 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
940 | /* | |
941 | * Set up a dummy frame to store reset vector as return address. | |
942 | * this causes stack underflow to reset board. | |
943 | */ | |
944 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
945 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
946 | ori r0, r0, RESET_VECTOR@l | |
947 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
948 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 949 | #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ |
0442ed86 | 950 | |
b867d705 SR |
951 | #if defined(CONFIG_405EP) |
952 | /*----------------------------------------------------------------------- */ | |
953 | /* DMA Status, clear to come up clean */ | |
954 | /*----------------------------------------------------------------------- */ | |
53677ef1 | 955 | addis r3,r0, 0xFFFF /* Clear all existing DMA status */ |
f901a83b WD |
956 | ori r3,r3, 0xFFFF |
957 | mtdcr dmasr, r3 | |
b867d705 | 958 | |
53677ef1 | 959 | bl ppc405ep_init /* do ppc405ep specific init */ |
b867d705 SR |
960 | #endif /* CONFIG_405EP */ |
961 | ||
6d0f6bcf | 962 | #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) |
e01bd218 SR |
963 | #if defined(CONFIG_405EZ) |
964 | /******************************************************************** | |
965 | * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 | |
966 | *******************************************************************/ | |
967 | /* | |
968 | * We can map the OCM on the PLB3, so map it at | |
6d0f6bcf | 969 | * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 |
e01bd218 | 970 | */ |
6d0f6bcf JCPV |
971 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
972 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
df8a24cd | 973 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
e01bd218 SR |
974 | mtdcr ocmplb3cr1,r3 /* Set PLB Access */ |
975 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ | |
976 | mtdcr ocmplb3cr2,r3 /* Set PLB Access */ | |
977 | isync | |
978 | ||
6d0f6bcf JCPV |
979 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
980 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
83b4cfa3 WD |
981 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
982 | mtdcr ocmdscr1, r3 /* Set Data Side */ | |
983 | mtdcr ocmiscr1, r3 /* Set Instruction Side */ | |
e01bd218 | 984 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ |
83b4cfa3 WD |
985 | mtdcr ocmdscr2, r3 /* Set Data Side */ |
986 | mtdcr ocmiscr2, r3 /* Set Instruction Side */ | |
987 | addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ | |
d7568947 | 988 | mtdcr ocmdsisdpc,r3 |
e01bd218 SR |
989 | |
990 | isync | |
3cb86f3e | 991 | #else /* CONFIG_405EZ */ |
0442ed86 WD |
992 | /******************************************************************** |
993 | * Setup OCM - On Chip Memory | |
994 | *******************************************************************/ | |
995 | /* Setup OCM */ | |
8bde7f77 WD |
996 | lis r0, 0x7FFF |
997 | ori r0, r0, 0xFFFF | |
f901a83b | 998 | mfdcr r3, ocmiscntl /* get instr-side IRAM config */ |
3cb86f3e SR |
999 | mfdcr r4, ocmdscntl /* get data-side IRAM config */ |
1000 | and r3, r3, r0 /* disable data-side IRAM */ | |
1001 | and r4, r4, r0 /* disable data-side IRAM */ | |
1002 | mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ | |
1003 | mtdcr ocmdscntl, r4 /* set data-side IRAM config */ | |
8bde7f77 | 1004 | isync |
0442ed86 | 1005 | |
6d0f6bcf JCPV |
1006 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
1007 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
0442ed86 WD |
1008 | mtdcr ocmdsarc, r3 |
1009 | addis r4, 0, 0xC000 /* OCM data area enabled */ | |
1010 | mtdcr ocmdscntl, r4 | |
8bde7f77 | 1011 | isync |
e01bd218 | 1012 | #endif /* CONFIG_405EZ */ |
0442ed86 WD |
1013 | #endif |
1014 | ||
1015 | /*----------------------------------------------------------------------- */ | |
1016 | /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ | |
1017 | /*----------------------------------------------------------------------- */ | |
6d0f6bcf | 1018 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
c821b5f1 GE |
1019 | li r4, PBxAP |
1020 | mtdcr ebccfga, r4 | |
6d0f6bcf JCPV |
1021 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h |
1022 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l | |
c821b5f1 GE |
1023 | mtdcr ebccfgd, r4 |
1024 | ||
1025 | addi r4, 0, PBxCR | |
1026 | mtdcr ebccfga, r4 | |
6d0f6bcf JCPV |
1027 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h |
1028 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l | |
c821b5f1 GE |
1029 | mtdcr ebccfgd, r4 |
1030 | ||
1031 | /* | |
1032 | * Enable the data cache for the 128MB storage access control region | |
6d0f6bcf | 1033 | * at CONFIG_SYS_INIT_RAM_ADDR. |
c821b5f1 GE |
1034 | */ |
1035 | mfdccr r4 | |
6d0f6bcf JCPV |
1036 | oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
1037 | ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
0442ed86 WD |
1038 | mtdccr r4 |
1039 | ||
c821b5f1 GE |
1040 | /* |
1041 | * Preallocate data cache lines to be used to avoid a subsequent | |
1042 | * cache miss and an ensuing machine check exception when exceptions | |
1043 | * are enabled. | |
1044 | */ | |
1045 | li r0, 0 | |
0442ed86 | 1046 | |
6d0f6bcf JCPV |
1047 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
1048 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
0442ed86 | 1049 | |
6d0f6bcf JCPV |
1050 | lis r4, CONFIG_SYS_INIT_RAM_END@h |
1051 | ori r4, r4, CONFIG_SYS_INIT_RAM_END@l | |
c821b5f1 GE |
1052 | |
1053 | /* | |
1054 | * Convert the size, in bytes, to the number of cache lines/blocks | |
1055 | * to preallocate. | |
1056 | */ | |
1057 | clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) | |
1058 | srwi r5, r4, L1_CACHE_SHIFT | |
1059 | beq ..load_counter | |
1060 | addi r5, r5, 0x0001 | |
1061 | ..load_counter: | |
1062 | mtctr r5 | |
1063 | ||
1064 | /* Preallocate the computed number of cache blocks. */ | |
1065 | ..alloc_dcache_block: | |
1066 | dcba r0, r3 | |
1067 | addi r3, r3, L1_CACHE_BYTES | |
1068 | bdnz ..alloc_dcache_block | |
1069 | sync | |
1070 | ||
1071 | /* | |
1072 | * Load the initial stack pointer and data area and convert the size, | |
1073 | * in bytes, to the number of words to initialize to a known value. | |
1074 | */ | |
6d0f6bcf JCPV |
1075 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
1076 | ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l | |
c821b5f1 | 1077 | |
6d0f6bcf JCPV |
1078 | lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h |
1079 | ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l | |
0442ed86 WD |
1080 | mtctr r4 |
1081 | ||
6d0f6bcf JCPV |
1082 | lis r2, CONFIG_SYS_INIT_RAM_ADDR@h |
1083 | ori r2, r2, CONFIG_SYS_INIT_RAM_END@l | |
0442ed86 | 1084 | |
6d0f6bcf JCPV |
1085 | lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h |
1086 | ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l | |
0442ed86 WD |
1087 | |
1088 | ..stackloop: | |
c821b5f1 | 1089 | stwu r4, -4(r2) |
0442ed86 WD |
1090 | bdnz ..stackloop |
1091 | ||
c821b5f1 GE |
1092 | /* |
1093 | * Make room for stack frame header and clear final stack frame so | |
1094 | * that stack backtraces terminate cleanly. | |
1095 | */ | |
1096 | stwu r0, -4(r1) | |
1097 | stwu r0, -4(r1) | |
1098 | ||
0442ed86 WD |
1099 | /* |
1100 | * Set up a dummy frame to store reset vector as return address. | |
1101 | * this causes stack underflow to reset board. | |
1102 | */ | |
1103 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1104 | addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ | |
1105 | ori r0, r0, RESET_VECTOR@l | |
1106 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1107 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
1108 | ||
6d0f6bcf JCPV |
1109 | #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ |
1110 | (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) | |
0442ed86 WD |
1111 | /* |
1112 | * Stack in OCM. | |
1113 | */ | |
1114 | ||
1115 | /* Set up Stack at top of OCM */ | |
6d0f6bcf JCPV |
1116 | lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h |
1117 | ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l | |
0442ed86 WD |
1118 | |
1119 | /* Set up a zeroized stack frame so that backtrace works right */ | |
1120 | li r0, 0 | |
1121 | stwu r0, -4(r1) | |
1122 | stwu r0, -4(r1) | |
1123 | ||
1124 | /* | |
1125 | * Set up a dummy frame to store reset vector as return address. | |
1126 | * this causes stack underflow to reset board. | |
1127 | */ | |
1128 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1129 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
1130 | ori r0, r0, RESET_VECTOR@l | |
1131 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1132 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 1133 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 1134 | |
c440bfe6 | 1135 | #ifdef CONFIG_NAND_SPL |
64852d09 | 1136 | bl nand_boot_common /* will not return */ |
c440bfe6 | 1137 | #else |
0442ed86 WD |
1138 | GET_GOT /* initialize GOT access */ |
1139 | ||
f901a83b | 1140 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ |
0442ed86 WD |
1141 | |
1142 | /* NEVER RETURNS! */ | |
1143 | bl board_init_f /* run first part of init code (from Flash) */ | |
c440bfe6 | 1144 | #endif /* CONFIG_NAND_SPL */ |
0442ed86 | 1145 | |
12f34241 WD |
1146 | #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ |
1147 | /*----------------------------------------------------------------------- */ | |
0442ed86 WD |
1148 | |
1149 | ||
887e2ec9 | 1150 | #ifndef CONFIG_NAND_SPL |
0442ed86 WD |
1151 | /* |
1152 | * This code finishes saving the registers to the exception frame | |
1153 | * and jumps to the appropriate handler for the exception. | |
1154 | * Register r21 is pointer into trap frame, r1 has new stack pointer. | |
1155 | */ | |
1156 | .globl transfer_to_handler | |
1157 | transfer_to_handler: | |
1158 | stw r22,_NIP(r21) | |
1159 | lis r22,MSR_POW@h | |
1160 | andc r23,r23,r22 | |
1161 | stw r23,_MSR(r21) | |
1162 | SAVE_GPR(7, r21) | |
1163 | SAVE_4GPRS(8, r21) | |
1164 | SAVE_8GPRS(12, r21) | |
1165 | SAVE_8GPRS(24, r21) | |
0442ed86 WD |
1166 | mflr r23 |
1167 | andi. r24,r23,0x3f00 /* get vector offset */ | |
1168 | stw r24,TRAP(r21) | |
1169 | li r22,0 | |
1170 | stw r22,RESULT(r21) | |
1171 | mtspr SPRG2,r22 /* r1 is now kernel sp */ | |
0442ed86 WD |
1172 | lwz r24,0(r23) /* virtual address of handler */ |
1173 | lwz r23,4(r23) /* where to go when done */ | |
1174 | mtspr SRR0,r24 | |
1175 | mtspr SRR1,r20 | |
1176 | mtlr r23 | |
1177 | SYNC | |
1178 | rfi /* jump to handler, enable MMU */ | |
1179 | ||
1180 | int_return: | |
1181 | mfmsr r28 /* Disable interrupts */ | |
1182 | li r4,0 | |
1183 | ori r4,r4,MSR_EE | |
1184 | andc r28,r28,r4 | |
1185 | SYNC /* Some chip revs need this... */ | |
1186 | mtmsr r28 | |
1187 | SYNC | |
1188 | lwz r2,_CTR(r1) | |
1189 | lwz r0,_LINK(r1) | |
1190 | mtctr r2 | |
1191 | mtlr r0 | |
1192 | lwz r2,_XER(r1) | |
1193 | lwz r0,_CCR(r1) | |
1194 | mtspr XER,r2 | |
1195 | mtcrf 0xFF,r0 | |
1196 | REST_10GPRS(3, r1) | |
1197 | REST_10GPRS(13, r1) | |
1198 | REST_8GPRS(23, r1) | |
1199 | REST_GPR(31, r1) | |
1200 | lwz r2,_NIP(r1) /* Restore environment */ | |
1201 | lwz r0,_MSR(r1) | |
1202 | mtspr SRR0,r2 | |
1203 | mtspr SRR1,r0 | |
1204 | lwz r0,GPR0(r1) | |
1205 | lwz r2,GPR2(r1) | |
1206 | lwz r1,GPR1(r1) | |
1207 | SYNC | |
1208 | rfi | |
1209 | ||
1210 | crit_return: | |
1211 | mfmsr r28 /* Disable interrupts */ | |
1212 | li r4,0 | |
1213 | ori r4,r4,MSR_EE | |
1214 | andc r28,r28,r4 | |
1215 | SYNC /* Some chip revs need this... */ | |
1216 | mtmsr r28 | |
1217 | SYNC | |
1218 | lwz r2,_CTR(r1) | |
1219 | lwz r0,_LINK(r1) | |
1220 | mtctr r2 | |
1221 | mtlr r0 | |
1222 | lwz r2,_XER(r1) | |
1223 | lwz r0,_CCR(r1) | |
1224 | mtspr XER,r2 | |
1225 | mtcrf 0xFF,r0 | |
1226 | REST_10GPRS(3, r1) | |
1227 | REST_10GPRS(13, r1) | |
1228 | REST_8GPRS(23, r1) | |
1229 | REST_GPR(31, r1) | |
1230 | lwz r2,_NIP(r1) /* Restore environment */ | |
1231 | lwz r0,_MSR(r1) | |
83b4cfa3 WD |
1232 | mtspr csrr0,r2 |
1233 | mtspr csrr1,r0 | |
0442ed86 WD |
1234 | lwz r0,GPR0(r1) |
1235 | lwz r2,GPR2(r1) | |
1236 | lwz r1,GPR1(r1) | |
1237 | SYNC | |
1238 | rfci | |
1239 | ||
efa35cf1 GB |
1240 | #ifdef CONFIG_440 |
1241 | mck_return: | |
83b4cfa3 WD |
1242 | mfmsr r28 /* Disable interrupts */ |
1243 | li r4,0 | |
1244 | ori r4,r4,MSR_EE | |
1245 | andc r28,r28,r4 | |
1246 | SYNC /* Some chip revs need this... */ | |
1247 | mtmsr r28 | |
1248 | SYNC | |
1249 | lwz r2,_CTR(r1) | |
1250 | lwz r0,_LINK(r1) | |
1251 | mtctr r2 | |
1252 | mtlr r0 | |
1253 | lwz r2,_XER(r1) | |
1254 | lwz r0,_CCR(r1) | |
1255 | mtspr XER,r2 | |
1256 | mtcrf 0xFF,r0 | |
1257 | REST_10GPRS(3, r1) | |
1258 | REST_10GPRS(13, r1) | |
1259 | REST_8GPRS(23, r1) | |
1260 | REST_GPR(31, r1) | |
1261 | lwz r2,_NIP(r1) /* Restore environment */ | |
1262 | lwz r0,_MSR(r1) | |
1263 | mtspr mcsrr0,r2 | |
1264 | mtspr mcsrr1,r0 | |
1265 | lwz r0,GPR0(r1) | |
1266 | lwz r2,GPR2(r1) | |
1267 | lwz r1,GPR1(r1) | |
1268 | SYNC | |
1269 | rfmci | |
efa35cf1 GB |
1270 | #endif /* CONFIG_440 */ |
1271 | ||
1272 | ||
0442ed86 WD |
1273 | .globl get_pvr |
1274 | get_pvr: | |
1275 | mfspr r3, PVR | |
1276 | blr | |
1277 | ||
0442ed86 WD |
1278 | /*------------------------------------------------------------------------------- */ |
1279 | /* Function: out16 */ | |
1280 | /* Description: Output 16 bits */ | |
1281 | /*------------------------------------------------------------------------------- */ | |
1282 | .globl out16 | |
1283 | out16: | |
1284 | sth r4,0x0000(r3) | |
1285 | blr | |
1286 | ||
1287 | /*------------------------------------------------------------------------------- */ | |
1288 | /* Function: out16r */ | |
1289 | /* Description: Byte reverse and output 16 bits */ | |
1290 | /*------------------------------------------------------------------------------- */ | |
1291 | .globl out16r | |
1292 | out16r: | |
1293 | sthbrx r4,r0,r3 | |
1294 | blr | |
1295 | ||
0442ed86 WD |
1296 | /*------------------------------------------------------------------------------- */ |
1297 | /* Function: out32r */ | |
1298 | /* Description: Byte reverse and output 32 bits */ | |
1299 | /*------------------------------------------------------------------------------- */ | |
1300 | .globl out32r | |
1301 | out32r: | |
1302 | stwbrx r4,r0,r3 | |
1303 | blr | |
1304 | ||
1305 | /*------------------------------------------------------------------------------- */ | |
1306 | /* Function: in16 */ | |
1307 | /* Description: Input 16 bits */ | |
1308 | /*------------------------------------------------------------------------------- */ | |
1309 | .globl in16 | |
1310 | in16: | |
1311 | lhz r3,0x0000(r3) | |
1312 | blr | |
1313 | ||
1314 | /*------------------------------------------------------------------------------- */ | |
1315 | /* Function: in16r */ | |
1316 | /* Description: Input 16 bits and byte reverse */ | |
1317 | /*------------------------------------------------------------------------------- */ | |
1318 | .globl in16r | |
1319 | in16r: | |
1320 | lhbrx r3,r0,r3 | |
1321 | blr | |
1322 | ||
0442ed86 WD |
1323 | /*------------------------------------------------------------------------------- */ |
1324 | /* Function: in32r */ | |
1325 | /* Description: Input 32 bits and byte reverse */ | |
1326 | /*------------------------------------------------------------------------------- */ | |
1327 | .globl in32r | |
1328 | in32r: | |
1329 | lwbrx r3,r0,r3 | |
1330 | blr | |
1331 | ||
0442ed86 WD |
1332 | /* |
1333 | * void relocate_code (addr_sp, gd, addr_moni) | |
1334 | * | |
1335 | * This "function" does not return, instead it continues in RAM | |
1336 | * after relocating the monitor code. | |
1337 | * | |
c821b5f1 GE |
1338 | * r3 = Relocated stack pointer |
1339 | * r4 = Relocated global data pointer | |
1340 | * r5 = Relocated text pointer | |
0442ed86 WD |
1341 | */ |
1342 | .globl relocate_code | |
1343 | relocate_code: | |
6d0f6bcf | 1344 | #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) |
9b94ac61 | 1345 | /* |
c821b5f1 GE |
1346 | * We need to flush the initial global data (gd_t) before the dcache |
1347 | * will be invalidated. | |
9b94ac61 SR |
1348 | */ |
1349 | ||
c821b5f1 GE |
1350 | /* Save registers */ |
1351 | mr r9, r3 | |
1352 | mr r10, r4 | |
1353 | mr r11, r5 | |
9b94ac61 | 1354 | |
c821b5f1 GE |
1355 | /* Flush initial global data range */ |
1356 | mr r3, r4 | |
6d0f6bcf | 1357 | addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l |
9b94ac61 SR |
1358 | bl flush_dcache_range |
1359 | ||
6d0f6bcf | 1360 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) |
c821b5f1 GE |
1361 | /* |
1362 | * Undo the earlier data cache set-up for the primordial stack and | |
1363 | * data area. First, invalidate the data cache and then disable data | |
1364 | * cacheability for that area. Finally, restore the EBC values, if | |
1365 | * any. | |
1366 | */ | |
1367 | ||
1368 | /* Invalidate the primordial stack and data area in cache */ | |
6d0f6bcf JCPV |
1369 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
1370 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
c821b5f1 | 1371 | |
6d0f6bcf JCPV |
1372 | lis r4, CONFIG_SYS_INIT_RAM_END@h |
1373 | ori r4, r4, CONFIG_SYS_INIT_RAM_END@l | |
c821b5f1 GE |
1374 | add r4, r4, r3 |
1375 | ||
1376 | bl invalidate_dcache_range | |
1377 | ||
1378 | /* Disable cacheability for the region */ | |
1379 | mfdccr r3 | |
6d0f6bcf JCPV |
1380 | lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
1381 | ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
c821b5f1 GE |
1382 | and r3, r3, r4 |
1383 | mtdccr r3 | |
1384 | ||
1385 | /* Restore the EBC parameters */ | |
1386 | li r3, PBxAP | |
1387 | mtdcr ebccfga, r3 | |
1388 | lis r3, PBxAP_VAL@h | |
1389 | ori r3, r3, PBxAP_VAL@l | |
1390 | mtdcr ebccfgd, r3 | |
1391 | ||
1392 | li r3, PBxCR | |
1393 | mtdcr ebccfga, r3 | |
1394 | lis r3, PBxCR_VAL@h | |
1395 | ori r3, r3, PBxCR_VAL@l | |
1396 | mtdcr ebccfgd, r3 | |
6d0f6bcf | 1397 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
c821b5f1 GE |
1398 | |
1399 | /* Restore registers */ | |
1400 | mr r3, r9 | |
1401 | mr r4, r10 | |
1402 | mr r5, r11 | |
6d0f6bcf | 1403 | #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
e02c521d | 1404 | |
6d0f6bcf | 1405 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
e02c521d SR |
1406 | /* |
1407 | * Unlock the previously locked d-cache | |
1408 | */ | |
1409 | msync | |
1410 | isync | |
1411 | /* set TFLOOR/NFLOOR to 0 again */ | |
1412 | lis r6,0x0001 | |
1413 | ori r6,r6,0xf800 | |
1414 | mtspr dvlim,r6 | |
1415 | lis r6,0x0000 | |
1416 | ori r6,r6,0x0000 | |
1417 | mtspr dnv0,r6 | |
1418 | mtspr dnv1,r6 | |
1419 | mtspr dnv2,r6 | |
1420 | mtspr dnv3,r6 | |
1421 | mtspr dtv0,r6 | |
1422 | mtspr dtv1,r6 | |
1423 | mtspr dtv2,r6 | |
1424 | mtspr dtv3,r6 | |
1425 | msync | |
1426 | isync | |
6d0f6bcf | 1427 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
e02c521d | 1428 | |
887e2ec9 SR |
1429 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
1430 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
2801b2d2 | 1431 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
7d307936 FK |
1432 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
1433 | defined(CONFIG_460SX) | |
a4c8d138 SR |
1434 | /* |
1435 | * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) | |
1436 | * to speed up the boot process. Now this cache needs to be disabled. | |
1437 | */ | |
1438 | iccci 0,0 /* Invalidate inst cache */ | |
1439 | dccci 0,0 /* Invalidate data cache, now no longer our stack */ | |
c157d8e2 | 1440 | sync |
a4c8d138 | 1441 | isync |
6d0f6bcf JCPV |
1442 | #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH |
1443 | addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ | |
85dc2a7f NG |
1444 | #else |
1445 | addi r1,r0,0x0000 /* Default TLB entry is #0 */ | |
6d0f6bcf | 1446 | #endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */ |
c157d8e2 | 1447 | tlbre r0,r1,0x0002 /* Read contents */ |
6e7fb6ea | 1448 | ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ |
f901a83b | 1449 | tlbwe r0,r1,0x0002 /* Save it out */ |
a4c8d138 | 1450 | sync |
c157d8e2 | 1451 | isync |
c821b5f1 | 1452 | #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ |
0442ed86 WD |
1453 | mr r1, r3 /* Set new stack pointer */ |
1454 | mr r9, r4 /* Save copy of Init Data pointer */ | |
1455 | mr r10, r5 /* Save copy of Destination Address */ | |
1456 | ||
1457 | mr r3, r5 /* Destination Address */ | |
6d0f6bcf JCPV |
1458 | lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ |
1459 | ori r4, r4, CONFIG_SYS_MONITOR_BASE@l | |
3b57fe0a WD |
1460 | lwz r5, GOT(__init_end) |
1461 | sub r5, r5, r4 | |
9b94ac61 | 1462 | li r6, L1_CACHE_BYTES /* Cache Line Size */ |
0442ed86 WD |
1463 | |
1464 | /* | |
1465 | * Fix GOT pointer: | |
1466 | * | |
6d0f6bcf | 1467 | * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address |
0442ed86 WD |
1468 | * |
1469 | * Offset: | |
1470 | */ | |
1471 | sub r15, r10, r4 | |
1472 | ||
1473 | /* First our own GOT */ | |
1474 | add r14, r14, r15 | |
c821b5f1 | 1475 | /* then the one used by the C code */ |
0442ed86 WD |
1476 | add r30, r30, r15 |
1477 | ||
1478 | /* | |
1479 | * Now relocate code | |
1480 | */ | |
1481 | ||
1482 | cmplw cr1,r3,r4 | |
1483 | addi r0,r5,3 | |
1484 | srwi. r0,r0,2 | |
1485 | beq cr1,4f /* In place copy is not necessary */ | |
1486 | beq 7f /* Protect against 0 count */ | |
1487 | mtctr r0 | |
1488 | bge cr1,2f | |
1489 | ||
1490 | la r8,-4(r4) | |
1491 | la r7,-4(r3) | |
1492 | 1: lwzu r0,4(r8) | |
1493 | stwu r0,4(r7) | |
1494 | bdnz 1b | |
1495 | b 4f | |
1496 | ||
1497 | 2: slwi r0,r0,2 | |
1498 | add r8,r4,r0 | |
1499 | add r7,r3,r0 | |
1500 | 3: lwzu r0,-4(r8) | |
1501 | stwu r0,-4(r7) | |
1502 | bdnz 3b | |
1503 | ||
1504 | /* | |
1505 | * Now flush the cache: note that we must start from a cache aligned | |
1506 | * address. Otherwise we might miss one cache line. | |
1507 | */ | |
1508 | 4: cmpwi r6,0 | |
1509 | add r5,r3,r5 | |
1510 | beq 7f /* Always flush prefetch queue in any case */ | |
1511 | subi r0,r6,1 | |
1512 | andc r3,r3,r0 | |
1513 | mr r4,r3 | |
1514 | 5: dcbst 0,r4 | |
1515 | add r4,r4,r6 | |
1516 | cmplw r4,r5 | |
1517 | blt 5b | |
1518 | sync /* Wait for all dcbst to complete on bus */ | |
1519 | mr r4,r3 | |
1520 | 6: icbi 0,r4 | |
1521 | add r4,r4,r6 | |
1522 | cmplw r4,r5 | |
1523 | blt 6b | |
1524 | 7: sync /* Wait for all icbi to complete on bus */ | |
1525 | isync | |
1526 | ||
1527 | /* | |
1528 | * We are done. Do not return, instead branch to second part of board | |
1529 | * initialization, now running from RAM. | |
1530 | */ | |
1531 | ||
efa35cf1 | 1532 | addi r0, r10, in_ram - _start + _START_OFFSET |
0442ed86 WD |
1533 | mtlr r0 |
1534 | blr /* NEVER RETURNS! */ | |
1535 | ||
1536 | in_ram: | |
1537 | ||
1538 | /* | |
1539 | * Relocation Function, r14 point to got2+0x8000 | |
1540 | * | |
1541 | * Adjust got2 pointers, no need to check for 0, this code | |
1542 | * already puts a few entries in the table. | |
1543 | */ | |
1544 | li r0,__got2_entries@sectoff@l | |
1545 | la r3,GOT(_GOT2_TABLE_) | |
1546 | lwz r11,GOT(_GOT2_TABLE_) | |
1547 | mtctr r0 | |
1548 | sub r11,r3,r11 | |
1549 | addi r3,r3,-4 | |
1550 | 1: lwzu r0,4(r3) | |
1551 | add r0,r0,r11 | |
1552 | stw r0,0(r3) | |
1553 | bdnz 1b | |
1554 | ||
1555 | /* | |
1556 | * Now adjust the fixups and the pointers to the fixups | |
1557 | * in case we need to move ourselves again. | |
1558 | */ | |
1559 | 2: li r0,__fixup_entries@sectoff@l | |
1560 | lwz r3,GOT(_FIXUP_TABLE_) | |
1561 | cmpwi r0,0 | |
1562 | mtctr r0 | |
1563 | addi r3,r3,-4 | |
1564 | beq 4f | |
1565 | 3: lwzu r4,4(r3) | |
1566 | lwzux r0,r4,r11 | |
1567 | add r0,r0,r11 | |
1568 | stw r10,0(r3) | |
1569 | stw r0,0(r4) | |
1570 | bdnz 3b | |
1571 | 4: | |
1572 | clear_bss: | |
1573 | /* | |
1574 | * Now clear BSS segment | |
1575 | */ | |
5d232d0e | 1576 | lwz r3,GOT(__bss_start) |
0442ed86 WD |
1577 | lwz r4,GOT(_end) |
1578 | ||
1579 | cmplw 0, r3, r4 | |
42ed33ff | 1580 | beq 7f |
0442ed86 WD |
1581 | |
1582 | li r0, 0 | |
42ed33ff AG |
1583 | |
1584 | andi. r5, r4, 3 | |
1585 | beq 6f | |
1586 | sub r4, r4, r5 | |
1587 | mtctr r5 | |
1588 | mr r5, r4 | |
1589 | 5: stb r0, 0(r5) | |
1590 | addi r5, r5, 1 | |
1591 | bdnz 5b | |
1592 | 6: | |
0442ed86 WD |
1593 | stw r0, 0(r3) |
1594 | addi r3, r3, 4 | |
1595 | cmplw 0, r3, r4 | |
42ed33ff | 1596 | bne 6b |
0442ed86 | 1597 | |
42ed33ff | 1598 | 7: |
0442ed86 WD |
1599 | mr r3, r9 /* Init Data pointer */ |
1600 | mr r4, r10 /* Destination Address */ | |
1601 | bl board_init_r | |
1602 | ||
0442ed86 WD |
1603 | /* |
1604 | * Copy exception vector code to low memory | |
1605 | * | |
1606 | * r3: dest_addr | |
1607 | * r7: source address, r8: end address, r9: target address | |
1608 | */ | |
1609 | .globl trap_init | |
1610 | trap_init: | |
efa35cf1 | 1611 | lwz r7, GOT(_start_of_vectors) |
0442ed86 WD |
1612 | lwz r8, GOT(_end_of_vectors) |
1613 | ||
682011ff | 1614 | li r9, 0x100 /* reset vector always at 0x100 */ |
0442ed86 WD |
1615 | |
1616 | cmplw 0, r7, r8 | |
1617 | bgelr /* return if r7>=r8 - just in case */ | |
1618 | ||
1619 | mflr r4 /* save link register */ | |
1620 | 1: | |
1621 | lwz r0, 0(r7) | |
1622 | stw r0, 0(r9) | |
1623 | addi r7, r7, 4 | |
1624 | addi r9, r9, 4 | |
1625 | cmplw 0, r7, r8 | |
1626 | bne 1b | |
1627 | ||
1628 | /* | |
1629 | * relocate `hdlr' and `int_return' entries | |
1630 | */ | |
efa35cf1 GB |
1631 | li r7, .L_MachineCheck - _start + _START_OFFSET |
1632 | li r8, Alignment - _start + _START_OFFSET | |
0442ed86 WD |
1633 | 2: |
1634 | bl trap_reloc | |
efa35cf1 | 1635 | addi r7, r7, 0x100 /* next exception vector */ |
0442ed86 WD |
1636 | cmplw 0, r7, r8 |
1637 | blt 2b | |
1638 | ||
efa35cf1 | 1639 | li r7, .L_Alignment - _start + _START_OFFSET |
0442ed86 WD |
1640 | bl trap_reloc |
1641 | ||
efa35cf1 | 1642 | li r7, .L_ProgramCheck - _start + _START_OFFSET |
0442ed86 WD |
1643 | bl trap_reloc |
1644 | ||
efa35cf1 GB |
1645 | #ifdef CONFIG_440 |
1646 | li r7, .L_FPUnavailable - _start + _START_OFFSET | |
83b4cfa3 | 1647 | bl trap_reloc |
0442ed86 | 1648 | |
efa35cf1 | 1649 | li r7, .L_Decrementer - _start + _START_OFFSET |
83b4cfa3 | 1650 | bl trap_reloc |
efa35cf1 GB |
1651 | |
1652 | li r7, .L_APU - _start + _START_OFFSET | |
83b4cfa3 | 1653 | bl trap_reloc |
df8a24cd | 1654 | |
83b4cfa3 WD |
1655 | li r7, .L_InstructionTLBError - _start + _START_OFFSET |
1656 | bl trap_reloc | |
efa35cf1 | 1657 | |
83b4cfa3 WD |
1658 | li r7, .L_DataTLBError - _start + _START_OFFSET |
1659 | bl trap_reloc | |
efa35cf1 GB |
1660 | #else /* CONFIG_440 */ |
1661 | li r7, .L_PIT - _start + _START_OFFSET | |
83b4cfa3 | 1662 | bl trap_reloc |
efa35cf1 GB |
1663 | |
1664 | li r7, .L_InstructionTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1665 | bl trap_reloc |
efa35cf1 GB |
1666 | |
1667 | li r7, .L_DataTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1668 | bl trap_reloc |
efa35cf1 GB |
1669 | #endif /* CONFIG_440 */ |
1670 | ||
83b4cfa3 WD |
1671 | li r7, .L_DebugBreakpoint - _start + _START_OFFSET |
1672 | bl trap_reloc | |
0442ed86 | 1673 | |
887e2ec9 | 1674 | #if !defined(CONFIG_440) |
9a7b408c SR |
1675 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1676 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
1677 | mtmsr r7 /* change MSR */ | |
1678 | #else | |
887e2ec9 SR |
1679 | bl __440_msr_set |
1680 | b __440_msr_continue | |
9a7b408c | 1681 | |
887e2ec9 | 1682 | __440_msr_set: |
9a7b408c SR |
1683 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1684 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
1685 | mtspr srr1,r7 | |
1686 | mflr r7 | |
1687 | mtspr srr0,r7 | |
1688 | rfi | |
887e2ec9 | 1689 | __440_msr_continue: |
9a7b408c SR |
1690 | #endif |
1691 | ||
0442ed86 WD |
1692 | mtlr r4 /* restore link register */ |
1693 | blr | |
1694 | ||
1695 | /* | |
1696 | * Function: relocate entries for one exception vector | |
1697 | */ | |
1698 | trap_reloc: | |
1699 | lwz r0, 0(r7) /* hdlr ... */ | |
1700 | add r0, r0, r3 /* ... += dest_addr */ | |
1701 | stw r0, 0(r7) | |
1702 | ||
1703 | lwz r0, 4(r7) /* int_return ... */ | |
1704 | add r0, r0, r3 /* ... += dest_addr */ | |
1705 | stw r0, 4(r7) | |
1706 | ||
1707 | blr | |
cf959c7d SR |
1708 | |
1709 | #if defined(CONFIG_440) | |
1710 | /*----------------------------------------------------------------------------+ | |
1711 | | dcbz_area. | |
1712 | +----------------------------------------------------------------------------*/ | |
1713 | function_prolog(dcbz_area) | |
1714 | rlwinm. r5,r4,0,27,31 | |
83b4cfa3 WD |
1715 | rlwinm r5,r4,27,5,31 |
1716 | beq ..d_ra2 | |
1717 | addi r5,r5,0x0001 | |
1718 | ..d_ra2:mtctr r5 | |
1719 | ..d_ag2:dcbz r0,r3 | |
1720 | addi r3,r3,32 | |
1721 | bdnz ..d_ag2 | |
cf959c7d SR |
1722 | sync |
1723 | blr | |
1724 | function_epilog(dcbz_area) | |
cf959c7d | 1725 | #endif /* CONFIG_440 */ |
887e2ec9 | 1726 | #endif /* CONFIG_NAND_SPL */ |
b867d705 | 1727 | |
cf959c7d SR |
1728 | /*------------------------------------------------------------------------------- */ |
1729 | /* Function: in8 */ | |
1730 | /* Description: Input 8 bits */ | |
1731 | /*------------------------------------------------------------------------------- */ | |
1732 | .globl in8 | |
1733 | in8: | |
1734 | lbz r3,0x0000(r3) | |
1735 | blr | |
1736 | ||
1737 | /*------------------------------------------------------------------------------- */ | |
1738 | /* Function: out8 */ | |
1739 | /* Description: Output 8 bits */ | |
1740 | /*------------------------------------------------------------------------------- */ | |
1741 | .globl out8 | |
1742 | out8: | |
1743 | stb r4,0x0000(r3) | |
1744 | blr | |
1745 | ||
1746 | /*------------------------------------------------------------------------------- */ | |
1747 | /* Function: out32 */ | |
1748 | /* Description: Output 32 bits */ | |
1749 | /*------------------------------------------------------------------------------- */ | |
1750 | .globl out32 | |
1751 | out32: | |
1752 | stw r4,0x0000(r3) | |
1753 | blr | |
1754 | ||
1755 | /*------------------------------------------------------------------------------- */ | |
1756 | /* Function: in32 */ | |
1757 | /* Description: Input 32 bits */ | |
1758 | /*------------------------------------------------------------------------------- */ | |
1759 | .globl in32 | |
1760 | in32: | |
1761 | lwz 3,0x0000(3) | |
1762 | blr | |
b867d705 SR |
1763 | |
1764 | /**************************************************************************/ | |
f901a83b | 1765 | /* PPC405EP specific stuff */ |
b867d705 SR |
1766 | /**************************************************************************/ |
1767 | #ifdef CONFIG_405EP | |
1768 | ppc405ep_init: | |
b828dda6 | 1769 | |
c157d8e2 | 1770 | #ifdef CONFIG_BUBINGA |
b828dda6 SR |
1771 | /* |
1772 | * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate | |
1773 | * function) to support FPGA and NVRAM accesses below. | |
1774 | */ | |
1775 | ||
1776 | lis r3,GPIO0_OSRH@h /* config GPIO output select */ | |
1777 | ori r3,r3,GPIO0_OSRH@l | |
6d0f6bcf JCPV |
1778 | lis r4,CONFIG_SYS_GPIO0_OSRH@h |
1779 | ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l | |
b828dda6 SR |
1780 | stw r4,0(r3) |
1781 | lis r3,GPIO0_OSRL@h | |
1782 | ori r3,r3,GPIO0_OSRL@l | |
6d0f6bcf JCPV |
1783 | lis r4,CONFIG_SYS_GPIO0_OSRL@h |
1784 | ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l | |
b828dda6 SR |
1785 | stw r4,0(r3) |
1786 | ||
1787 | lis r3,GPIO0_ISR1H@h /* config GPIO input select */ | |
1788 | ori r3,r3,GPIO0_ISR1H@l | |
6d0f6bcf JCPV |
1789 | lis r4,CONFIG_SYS_GPIO0_ISR1H@h |
1790 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l | |
b828dda6 SR |
1791 | stw r4,0(r3) |
1792 | lis r3,GPIO0_ISR1L@h | |
1793 | ori r3,r3,GPIO0_ISR1L@l | |
6d0f6bcf JCPV |
1794 | lis r4,CONFIG_SYS_GPIO0_ISR1L@h |
1795 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l | |
b828dda6 SR |
1796 | stw r4,0(r3) |
1797 | ||
1798 | lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ | |
1799 | ori r3,r3,GPIO0_TSRH@l | |
6d0f6bcf JCPV |
1800 | lis r4,CONFIG_SYS_GPIO0_TSRH@h |
1801 | ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l | |
b828dda6 SR |
1802 | stw r4,0(r3) |
1803 | lis r3,GPIO0_TSRL@h | |
1804 | ori r3,r3,GPIO0_TSRL@l | |
6d0f6bcf JCPV |
1805 | lis r4,CONFIG_SYS_GPIO0_TSRL@h |
1806 | ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l | |
b828dda6 SR |
1807 | stw r4,0(r3) |
1808 | ||
1809 | lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ | |
1810 | ori r3,r3,GPIO0_TCR@l | |
6d0f6bcf JCPV |
1811 | lis r4,CONFIG_SYS_GPIO0_TCR@h |
1812 | ori r4,r4,CONFIG_SYS_GPIO0_TCR@l | |
b828dda6 SR |
1813 | stw r4,0(r3) |
1814 | ||
1815 | li r3,pb1ap /* program EBC bank 1 for RTC access */ | |
1816 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1817 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1818 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
b828dda6 SR |
1819 | mtdcr ebccfgd,r3 |
1820 | li r3,pb1cr | |
1821 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1822 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1823 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
b828dda6 SR |
1824 | mtdcr ebccfgd,r3 |
1825 | ||
1826 | li r3,pb1ap /* program EBC bank 1 for RTC access */ | |
1827 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1828 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1829 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
b828dda6 SR |
1830 | mtdcr ebccfgd,r3 |
1831 | li r3,pb1cr | |
1832 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1833 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1834 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
b828dda6 SR |
1835 | mtdcr ebccfgd,r3 |
1836 | ||
1837 | li r3,pb4ap /* program EBC bank 4 for FPGA access */ | |
1838 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1839 | lis r3,CONFIG_SYS_EBC_PB4AP@h |
1840 | ori r3,r3,CONFIG_SYS_EBC_PB4AP@l | |
b828dda6 SR |
1841 | mtdcr ebccfgd,r3 |
1842 | li r3,pb4cr | |
1843 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1844 | lis r3,CONFIG_SYS_EBC_PB4CR@h |
1845 | ori r3,r3,CONFIG_SYS_EBC_PB4CR@l | |
b828dda6 SR |
1846 | mtdcr ebccfgd,r3 |
1847 | #endif | |
8bde7f77 WD |
1848 | |
1849 | /* | |
1850 | !----------------------------------------------------------------------- | |
1851 | ! Check to see if chip is in bypass mode. | |
1852 | ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a | |
1853 | ! CPU reset Otherwise, skip this step and keep going. | |
f901a83b WD |
1854 | ! Note: Running BIOS in bypass mode is not supported since PLB speed |
1855 | ! will not be fast enough for the SDRAM (min 66MHz) | |
8bde7f77 | 1856 | !----------------------------------------------------------------------- |
b867d705 | 1857 | */ |
f901a83b | 1858 | mfdcr r5, CPC0_PLLMR1 |
53677ef1 | 1859 | rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ |
f901a83b | 1860 | cmpi cr0,0,r4,0x1 |
b867d705 | 1861 | |
53677ef1 WD |
1862 | beq pll_done /* if SSCS =b'1' then PLL has */ |
1863 | /* already been set */ | |
1864 | /* and CPU has been reset */ | |
1865 | /* so skip to next section */ | |
b867d705 | 1866 | |
c157d8e2 | 1867 | #ifdef CONFIG_BUBINGA |
b867d705 | 1868 | /* |
8bde7f77 WD |
1869 | !----------------------------------------------------------------------- |
1870 | ! Read NVRAM to get value to write in PLLMR. | |
1871 | ! If value has not been correctly saved, write default value | |
1872 | ! Default config values (assuming on-board 33MHz SYS_CLK) are above. | |
1873 | ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. | |
1874 | ! | |
1875 | ! WARNING: This code assumes the first three words in the nvram_t | |
f901a83b WD |
1876 | ! structure in openbios.h. Changing the beginning of |
1877 | ! the structure will break this code. | |
8bde7f77 WD |
1878 | ! |
1879 | !----------------------------------------------------------------------- | |
b867d705 | 1880 | */ |
f901a83b WD |
1881 | addis r3,0,NVRAM_BASE@h |
1882 | addi r3,r3,NVRAM_BASE@l | |
1883 | ||
1884 | lwz r4, 0(r3) | |
1885 | addis r5,0,NVRVFY1@h | |
1886 | addi r5,r5,NVRVFY1@l | |
53677ef1 | 1887 | cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ |
f901a83b WD |
1888 | bne ..no_pllset |
1889 | addi r3,r3,4 | |
1890 | lwz r4, 0(r3) | |
1891 | addis r5,0,NVRVFY2@h | |
1892 | addi r5,r5,NVRVFY2@l | |
53677ef1 | 1893 | cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ |
f901a83b WD |
1894 | bne ..no_pllset |
1895 | addi r3,r3,8 /* Skip over conf_size */ | |
1896 | lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ | |
1897 | lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ | |
1898 | rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ | |
1899 | cmpi cr0,0,r5,1 /* See if PLL is locked */ | |
1900 | beq pll_write | |
b867d705 | 1901 | ..no_pllset: |
c157d8e2 | 1902 | #endif /* CONFIG_BUBINGA */ |
b867d705 | 1903 | |
d4024bb7 JO |
1904 | #ifdef CONFIG_TAIHU |
1905 | mfdcr r4, CPC0_BOOT | |
1906 | andi. r5, r4, CPC0_BOOT_SEP@l | |
1907 | bne strap_1 /* serial eeprom present */ | |
1908 | addis r5,0,CPLD_REG0_ADDR@h | |
1909 | ori r5,r5,CPLD_REG0_ADDR@l | |
1910 | andi. r5, r5, 0x10 | |
1911 | bne _pci_66mhz | |
1912 | #endif /* CONFIG_TAIHU */ | |
1913 | ||
779e9751 SR |
1914 | #if defined(CONFIG_ZEUS) |
1915 | mfdcr r4, CPC0_BOOT | |
1916 | andi. r5, r4, CPC0_BOOT_SEP@l | |
53677ef1 | 1917 | bne strap_1 /* serial eeprom present */ |
779e9751 SR |
1918 | lis r3,0x0000 |
1919 | addi r3,r3,0x3030 | |
1920 | lis r4,0x8042 | |
1921 | addi r4,r4,0x223e | |
1922 | b 1f | |
1923 | strap_1: | |
1924 | mfdcr r3, CPC0_PLLMR0 | |
1925 | mfdcr r4, CPC0_PLLMR1 | |
1926 | b 1f | |
1927 | #endif | |
1928 | ||
53677ef1 WD |
1929 | addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ |
1930 | ori r3,r3,PLLMR0_DEFAULT@l /* */ | |
1931 | addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ | |
1932 | ori r4,r4,PLLMR1_DEFAULT@l /* */ | |
b867d705 | 1933 | |
d4024bb7 JO |
1934 | #ifdef CONFIG_TAIHU |
1935 | b 1f | |
1936 | _pci_66mhz: | |
1937 | addis r3,0,PLLMR0_DEFAULT_PCI66@h | |
1938 | ori r3,r3,PLLMR0_DEFAULT_PCI66@l | |
1939 | addis r4,0,PLLMR1_DEFAULT_PCI66@h | |
1940 | ori r4,r4,PLLMR1_DEFAULT_PCI66@l | |
1941 | b 1f | |
1942 | strap_1: | |
1943 | mfdcr r3, CPC0_PLLMR0 | |
1944 | mfdcr r4, CPC0_PLLMR1 | |
d4024bb7 JO |
1945 | #endif /* CONFIG_TAIHU */ |
1946 | ||
779e9751 | 1947 | 1: |
53677ef1 | 1948 | b pll_write /* Write the CPC0_PLLMR with new value */ |
b867d705 SR |
1949 | |
1950 | pll_done: | |
8bde7f77 WD |
1951 | /* |
1952 | !----------------------------------------------------------------------- | |
1953 | ! Clear Soft Reset Register | |
1954 | ! This is needed to enable PCI if not booting from serial EPROM | |
1955 | !----------------------------------------------------------------------- | |
b867d705 | 1956 | */ |
f901a83b WD |
1957 | addi r3, 0, 0x0 |
1958 | mtdcr CPC0_SRR, r3 | |
b867d705 | 1959 | |
f901a83b WD |
1960 | addis r3,0,0x0010 |
1961 | mtctr r3 | |
b867d705 | 1962 | pci_wait: |
f901a83b | 1963 | bdnz pci_wait |
b867d705 | 1964 | |
53677ef1 | 1965 | blr /* return to main code */ |
b867d705 SR |
1966 | |
1967 | /* | |
1968 | !----------------------------------------------------------------------------- | |
f901a83b WD |
1969 | ! Function: pll_write |
1970 | ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation | |
1971 | ! That is: | |
1972 | ! 1. Pll is first disabled (de-activated by putting in bypass mode) | |
1973 | ! 2. PLL is reset | |
1974 | ! 3. Clock dividers are set while PLL is held in reset and bypassed | |
1975 | ! 4. PLL Reset is cleared | |
1976 | ! 5. Wait 100us for PLL to lock | |
1977 | ! 6. A core reset is performed | |
b867d705 SR |
1978 | ! Input: r3 = Value to write to CPC0_PLLMR0 |
1979 | ! Input: r4 = Value to write to CPC0_PLLMR1 | |
1980 | ! Output r3 = none | |
1981 | !----------------------------------------------------------------------------- | |
1982 | */ | |
1983 | pll_write: | |
8bde7f77 WD |
1984 | mfdcr r5, CPC0_UCR |
1985 | andis. r5,r5,0xFFFF | |
53677ef1 WD |
1986 | ori r5,r5,0x0101 /* Stop the UART clocks */ |
1987 | mtdcr CPC0_UCR,r5 /* Before changing PLL */ | |
8bde7f77 WD |
1988 | |
1989 | mfdcr r5, CPC0_PLLMR1 | |
53677ef1 | 1990 | rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ |
f901a83b | 1991 | mtdcr CPC0_PLLMR1,r5 |
53677ef1 | 1992 | oris r5,r5,0x4000 /* Set PLL Reset */ |
f901a83b WD |
1993 | mtdcr CPC0_PLLMR1,r5 |
1994 | ||
53677ef1 WD |
1995 | mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ |
1996 | rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ | |
1997 | oris r5,r5,0x4000 /* Set PLL Reset */ | |
1998 | mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ | |
1999 | rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ | |
f901a83b | 2000 | mtdcr CPC0_PLLMR1,r5 |
b867d705 SR |
2001 | |
2002 | /* | |
8bde7f77 WD |
2003 | ! Wait min of 100us for PLL to lock. |
2004 | ! See CMOS 27E databook for more info. | |
2005 | ! At 200MHz, that means waiting 20,000 instructions | |
b867d705 | 2006 | */ |
f901a83b WD |
2007 | addi r3,0,20000 /* 2000 = 0x4e20 */ |
2008 | mtctr r3 | |
b867d705 | 2009 | pll_wait: |
f901a83b | 2010 | bdnz pll_wait |
8bde7f77 | 2011 | |
f901a83b WD |
2012 | oris r5,r5,0x8000 /* Enable PLL */ |
2013 | mtdcr CPC0_PLLMR1,r5 /* Engage */ | |
8bde7f77 WD |
2014 | |
2015 | /* | |
2016 | * Reset CPU to guarantee timings are OK | |
2017 | * Not sure if this is needed... | |
2018 | */ | |
2019 | addis r3,0,0x1000 | |
53677ef1 WD |
2020 | mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ |
2021 | /* execution will continue from the poweron */ | |
2022 | /* vector of 0xfffffffc */ | |
b867d705 | 2023 | #endif /* CONFIG_405EP */ |
4745acaa SR |
2024 | |
2025 | #if defined(CONFIG_440) | |
4745acaa SR |
2026 | /*----------------------------------------------------------------------------+ |
2027 | | mttlb3. | |
2028 | +----------------------------------------------------------------------------*/ | |
2029 | function_prolog(mttlb3) | |
2030 | TLBWE(4,3,2) | |
2031 | blr | |
2032 | function_epilog(mttlb3) | |
2033 | ||
2034 | /*----------------------------------------------------------------------------+ | |
2035 | | mftlb3. | |
2036 | +----------------------------------------------------------------------------*/ | |
2037 | function_prolog(mftlb3) | |
74357114 | 2038 | TLBRE(3,3,2) |
4745acaa SR |
2039 | blr |
2040 | function_epilog(mftlb3) | |
2041 | ||
2042 | /*----------------------------------------------------------------------------+ | |
2043 | | mttlb2. | |
2044 | +----------------------------------------------------------------------------*/ | |
2045 | function_prolog(mttlb2) | |
2046 | TLBWE(4,3,1) | |
2047 | blr | |
2048 | function_epilog(mttlb2) | |
2049 | ||
2050 | /*----------------------------------------------------------------------------+ | |
2051 | | mftlb2. | |
2052 | +----------------------------------------------------------------------------*/ | |
2053 | function_prolog(mftlb2) | |
74357114 | 2054 | TLBRE(3,3,1) |
4745acaa SR |
2055 | blr |
2056 | function_epilog(mftlb2) | |
2057 | ||
2058 | /*----------------------------------------------------------------------------+ | |
2059 | | mttlb1. | |
2060 | +----------------------------------------------------------------------------*/ | |
2061 | function_prolog(mttlb1) | |
2062 | TLBWE(4,3,0) | |
2063 | blr | |
2064 | function_epilog(mttlb1) | |
2065 | ||
2066 | /*----------------------------------------------------------------------------+ | |
2067 | | mftlb1. | |
2068 | +----------------------------------------------------------------------------*/ | |
2069 | function_prolog(mftlb1) | |
74357114 | 2070 | TLBRE(3,3,0) |
4745acaa SR |
2071 | blr |
2072 | function_epilog(mftlb1) | |
2073 | #endif /* CONFIG_440 */ | |
64852d09 SR |
2074 | |
2075 | #if defined(CONFIG_NAND_SPL) | |
2076 | /* | |
2077 | * void nand_boot_relocate(dst, src, bytes) | |
2078 | * | |
2079 | * r3 = Destination address to copy code to (in SDRAM) | |
2080 | * r4 = Source address to copy code from | |
2081 | * r5 = size to copy in bytes | |
2082 | */ | |
2083 | nand_boot_relocate: | |
2084 | mr r6,r3 | |
2085 | mr r7,r4 | |
2086 | mflr r8 | |
2087 | ||
2088 | /* | |
2089 | * Copy SPL from icache into SDRAM | |
2090 | */ | |
2091 | subi r3,r3,4 | |
2092 | subi r4,r4,4 | |
2093 | srwi r5,r5,2 | |
2094 | mtctr r5 | |
2095 | ..spl_loop: | |
2096 | lwzu r0,4(r4) | |
2097 | stwu r0,4(r3) | |
2098 | bdnz ..spl_loop | |
2099 | ||
2100 | /* | |
2101 | * Calculate "corrected" link register, so that we "continue" | |
2102 | * in execution in destination range | |
2103 | */ | |
2104 | sub r3,r7,r6 /* r3 = src - dst */ | |
2105 | sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ | |
2106 | mtlr r8 | |
2107 | blr | |
2108 | ||
2109 | nand_boot_common: | |
2110 | /* | |
2111 | * First initialize SDRAM. It has to be available *before* calling | |
2112 | * nand_boot(). | |
2113 | */ | |
6d0f6bcf JCPV |
2114 | lis r3,CONFIG_SYS_SDRAM_BASE@h |
2115 | ori r3,r3,CONFIG_SYS_SDRAM_BASE@l | |
64852d09 SR |
2116 | bl initdram |
2117 | ||
2118 | /* | |
2119 | * Now copy the 4k SPL code into SDRAM and continue execution | |
2120 | * from there. | |
2121 | */ | |
6d0f6bcf JCPV |
2122 | lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h |
2123 | ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l | |
2124 | lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h | |
2125 | ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l | |
2126 | lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h | |
2127 | ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l | |
64852d09 SR |
2128 | bl nand_boot_relocate |
2129 | ||
2130 | /* | |
2131 | * We're running from SDRAM now!!! | |
2132 | * | |
2133 | * It is necessary for 4xx systems to relocate from running at | |
2134 | * the original location (0xfffffxxx) to somewhere else (SDRAM | |
2135 | * preferably). This is because CS0 needs to be reconfigured for | |
2136 | * NAND access. And we can't reconfigure this CS when currently | |
2137 | * "running" from it. | |
2138 | */ | |
2139 | ||
2140 | /* | |
2141 | * Finally call nand_boot() to load main NAND U-Boot image from | |
2142 | * NAND and jump to it. | |
2143 | */ | |
2144 | bl nand_boot /* will not return */ | |
2145 | #endif /* CONFIG_NAND_SPL */ |