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0442ed86 WD |
1 | /* |
2 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> | |
3 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> | |
4 | * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> | |
3cb86f3e | 5 | * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering |
c821b5f1 GE |
6 | * Copyright (c) 2008 Nuovation System Designs, LLC |
7 | * Grant Erickson <gerickson@nuovations.com> | |
0442ed86 WD |
8 | * |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
83b4cfa3 WD |
27 | /*------------------------------------------------------------------------------+ |
28 | * | |
29 | * This source code has been made available to you by IBM on an AS-IS | |
30 | * basis. Anyone receiving this source is licensed under IBM | |
31 | * copyrights to use it in any way he or she deems fit, including | |
32 | * copying it, modifying it, compiling it, and redistributing it either | |
33 | * with or without modifications. No license under IBM patents or | |
34 | * patent applications is to be implied by the copyright license. | |
35 | * | |
36 | * Any user of this software should understand that IBM cannot provide | |
37 | * technical support for this software and will not be responsible for | |
38 | * any consequences resulting from the use of this software. | |
39 | * | |
40 | * Any person who transfers this source code or any derivative work | |
41 | * must include the IBM copyright notice, this paragraph, and the | |
42 | * preceding two paragraphs in the transferred software. | |
43 | * | |
44 | * COPYRIGHT I B M CORPORATION 1995 | |
45 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
46 | *------------------------------------------------------------------------------- | |
47 | */ | |
0442ed86 | 48 | |
0c8721a4 | 49 | /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards |
0442ed86 WD |
50 | * |
51 | * | |
52 | * The processor starts at 0xfffffffc and the code is executed | |
53 | * from flash/rom. | |
54 | * in memory, but as long we don't jump around before relocating. | |
55 | * board_init lies at a quite high address and when the cpu has | |
56 | * jumped there, everything is ok. | |
57 | * This works because the cpu gives the FLASH (CS0) the whole | |
58 | * address space at startup, and board_init lies as a echo of | |
59 | * the flash somewhere up there in the memorymap. | |
60 | * | |
61 | * board_init will change CS0 to be positioned at the correct | |
62 | * address and (s)dram will be positioned at address 0 | |
63 | */ | |
64 | #include <config.h> | |
0442ed86 | 65 | #include <ppc4xx.h> |
561858ee | 66 | #include <timestamp.h> |
0442ed86 WD |
67 | #include <version.h> |
68 | ||
69 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
70 | ||
71 | #include <ppc_asm.tmpl> | |
72 | #include <ppc_defs.h> | |
73 | ||
74 | #include <asm/cache.h> | |
75 | #include <asm/mmu.h> | |
b14ca4b6 | 76 | #include <asm/ppc4xx-isram.h> |
0442ed86 WD |
77 | |
78 | #ifndef CONFIG_IDENT_STRING | |
79 | #define CONFIG_IDENT_STRING "" | |
80 | #endif | |
81 | ||
6d0f6bcf JCPV |
82 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
83 | # if (CONFIG_SYS_INIT_DCACHE_CS == 0) | |
0442ed86 WD |
84 | # define PBxAP pb0ap |
85 | # define PBxCR pb0cr | |
6d0f6bcf JCPV |
86 | # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) |
87 | # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP | |
88 | # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR | |
c821b5f1 | 89 | # endif |
0442ed86 | 90 | # endif |
6d0f6bcf | 91 | # if (CONFIG_SYS_INIT_DCACHE_CS == 1) |
0442ed86 WD |
92 | # define PBxAP pb1ap |
93 | # define PBxCR pb1cr | |
6d0f6bcf JCPV |
94 | # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) |
95 | # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP | |
96 | # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR | |
c821b5f1 | 97 | # endif |
0442ed86 | 98 | # endif |
6d0f6bcf | 99 | # if (CONFIG_SYS_INIT_DCACHE_CS == 2) |
0442ed86 WD |
100 | # define PBxAP pb2ap |
101 | # define PBxCR pb2cr | |
6d0f6bcf JCPV |
102 | # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) |
103 | # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP | |
104 | # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR | |
c821b5f1 | 105 | # endif |
0442ed86 | 106 | # endif |
6d0f6bcf | 107 | # if (CONFIG_SYS_INIT_DCACHE_CS == 3) |
0442ed86 WD |
108 | # define PBxAP pb3ap |
109 | # define PBxCR pb3cr | |
6d0f6bcf JCPV |
110 | # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) |
111 | # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP | |
112 | # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR | |
c821b5f1 | 113 | # endif |
0442ed86 | 114 | # endif |
6d0f6bcf | 115 | # if (CONFIG_SYS_INIT_DCACHE_CS == 4) |
0442ed86 WD |
116 | # define PBxAP pb4ap |
117 | # define PBxCR pb4cr | |
6d0f6bcf JCPV |
118 | # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) |
119 | # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP | |
120 | # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR | |
c821b5f1 | 121 | # endif |
0442ed86 | 122 | # endif |
6d0f6bcf | 123 | # if (CONFIG_SYS_INIT_DCACHE_CS == 5) |
0442ed86 WD |
124 | # define PBxAP pb5ap |
125 | # define PBxCR pb5cr | |
6d0f6bcf JCPV |
126 | # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) |
127 | # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP | |
128 | # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR | |
c821b5f1 | 129 | # endif |
0442ed86 | 130 | # endif |
6d0f6bcf | 131 | # if (CONFIG_SYS_INIT_DCACHE_CS == 6) |
0442ed86 WD |
132 | # define PBxAP pb6ap |
133 | # define PBxCR pb6cr | |
6d0f6bcf JCPV |
134 | # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) |
135 | # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP | |
136 | # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR | |
c821b5f1 | 137 | # endif |
0442ed86 | 138 | # endif |
6d0f6bcf | 139 | # if (CONFIG_SYS_INIT_DCACHE_CS == 7) |
0442ed86 WD |
140 | # define PBxAP pb7ap |
141 | # define PBxCR pb7cr | |
6d0f6bcf JCPV |
142 | # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) |
143 | # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP | |
144 | # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR | |
c821b5f1 GE |
145 | # endif |
146 | # endif | |
147 | # ifndef PBxAP_VAL | |
148 | # define PBxAP_VAL 0 | |
149 | # endif | |
150 | # ifndef PBxCR_VAL | |
151 | # define PBxCR_VAL 0 | |
152 | # endif | |
153 | /* | |
6d0f6bcf | 154 | * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB |
c821b5f1 GE |
155 | * used as temporary stack pointer for the primordial stack |
156 | */ | |
6d0f6bcf JCPV |
157 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR |
158 | # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ | |
c821b5f1 GE |
159 | EBC_BXAP_TWT_ENCODE(7) | \ |
160 | EBC_BXAP_BCE_DISABLE | \ | |
161 | EBC_BXAP_BCT_2TRANS | \ | |
162 | EBC_BXAP_CSN_ENCODE(0) | \ | |
163 | EBC_BXAP_OEN_ENCODE(0) | \ | |
164 | EBC_BXAP_WBN_ENCODE(0) | \ | |
165 | EBC_BXAP_WBF_ENCODE(0) | \ | |
166 | EBC_BXAP_TH_ENCODE(2) | \ | |
167 | EBC_BXAP_RE_DISABLED | \ | |
168 | EBC_BXAP_SOR_NONDELAYED | \ | |
169 | EBC_BXAP_BEM_WRITEONLY | \ | |
170 | EBC_BXAP_PEN_DISABLED) | |
6d0f6bcf JCPV |
171 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ |
172 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR | |
173 | # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ | |
c821b5f1 GE |
174 | EBC_BXCR_BS_64MB | \ |
175 | EBC_BXCR_BU_RW | \ | |
176 | EBC_BXCR_BW_16BIT) | |
6d0f6bcf JCPV |
177 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ |
178 | # ifndef CONFIG_SYS_INIT_RAM_PATTERN | |
179 | # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD | |
0442ed86 | 180 | # endif |
6d0f6bcf | 181 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 182 | |
6d0f6bcf JCPV |
183 | #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10))) |
184 | #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END! | |
28d77d96 SR |
185 | #endif |
186 | ||
c821b5f1 GE |
187 | /* |
188 | * Unless otherwise overriden, enable two 128MB cachable instruction regions | |
6d0f6bcf JCPV |
189 | * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering |
190 | * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. | |
c821b5f1 | 191 | */ |
6d0f6bcf | 192 | #if !defined(CONFIG_SYS_FLASH_BASE) |
64852d09 | 193 | /* If not already defined, set it to the "last" 128MByte region */ |
6d0f6bcf | 194 | # define CONFIG_SYS_FLASH_BASE 0xf8000000 |
64852d09 | 195 | #endif |
6d0f6bcf JCPV |
196 | #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) |
197 | # define CONFIG_SYS_ICACHE_SACR_VALUE \ | |
198 | (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ | |
199 | PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ | |
200 | PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) | |
201 | #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ | |
202 | ||
203 | #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) | |
204 | # define CONFIG_SYS_DCACHE_SACR_VALUE \ | |
c821b5f1 | 205 | (0x00000000) |
6d0f6bcf | 206 | #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ |
c821b5f1 | 207 | |
83b4cfa3 | 208 | #define function_prolog(func_name) .text; \ |
cf959c7d SR |
209 | .align 2; \ |
210 | .globl func_name; \ | |
211 | func_name: | |
83b4cfa3 | 212 | #define function_epilog(func_name) .type func_name,@function; \ |
cf959c7d SR |
213 | .size func_name,.-func_name |
214 | ||
0442ed86 WD |
215 | /* We don't want the MMU yet. |
216 | */ | |
217 | #undef MSR_KERNEL | |
218 | #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ | |
219 | ||
220 | ||
221 | .extern ext_bus_cntlr_init | |
887e2ec9 SR |
222 | #ifdef CONFIG_NAND_U_BOOT |
223 | .extern reconfig_tlb0 | |
224 | #endif | |
0442ed86 WD |
225 | |
226 | /* | |
227 | * Set up GOT: Global Offset Table | |
228 | * | |
229 | * Use r14 to access the GOT | |
230 | */ | |
887e2ec9 | 231 | #if !defined(CONFIG_NAND_SPL) |
0442ed86 WD |
232 | START_GOT |
233 | GOT_ENTRY(_GOT2_TABLE_) | |
234 | GOT_ENTRY(_FIXUP_TABLE_) | |
235 | ||
236 | GOT_ENTRY(_start) | |
237 | GOT_ENTRY(_start_of_vectors) | |
238 | GOT_ENTRY(_end_of_vectors) | |
239 | GOT_ENTRY(transfer_to_handler) | |
240 | ||
3b57fe0a | 241 | GOT_ENTRY(__init_end) |
0442ed86 | 242 | GOT_ENTRY(_end) |
5d232d0e | 243 | GOT_ENTRY(__bss_start) |
0442ed86 | 244 | END_GOT |
887e2ec9 SR |
245 | #endif /* CONFIG_NAND_SPL */ |
246 | ||
247 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
248 | /* | |
249 | * NAND U-Boot image is started from offset 0 | |
250 | */ | |
251 | .text | |
c440bfe6 | 252 | #if defined(CONFIG_440) |
887e2ec9 | 253 | bl reconfig_tlb0 |
c440bfe6 | 254 | #endif |
887e2ec9 SR |
255 | GET_GOT |
256 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ | |
257 | bl board_init_f | |
258 | #endif | |
0442ed86 WD |
259 | |
260 | /* | |
261 | * 440 Startup -- on reset only the top 4k of the effective | |
262 | * address space is mapped in by an entry in the instruction | |
263 | * and data shadow TLB. The .bootpg section is located in the | |
264 | * top 4k & does only what's necessary to map in the the rest | |
265 | * of the boot rom. Once the boot rom is mapped in we can | |
266 | * proceed with normal startup. | |
267 | * | |
268 | * NOTE: CS0 only covers the top 2MB of the effective address | |
269 | * space after reset. | |
270 | */ | |
271 | ||
272 | #if defined(CONFIG_440) | |
887e2ec9 | 273 | #if !defined(CONFIG_NAND_SPL) |
0442ed86 | 274 | .section .bootpg,"ax" |
887e2ec9 | 275 | #endif |
0442ed86 WD |
276 | .globl _start_440 |
277 | ||
278 | /**************************************************************************/ | |
279 | _start_440: | |
511d0c72 WD |
280 | /*--------------------------------------------------------------------+ |
281 | | 440EPX BUP Change - Hardware team request | |
282 | +--------------------------------------------------------------------*/ | |
887e2ec9 SR |
283 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
284 | sync | |
285 | nop | |
286 | nop | |
287 | #endif | |
6c5879f3 MB |
288 | /*----------------------------------------------------------------+ |
289 | | Core bug fix. Clear the esr | |
290 | +-----------------------------------------------------------------*/ | |
edd6cf20 | 291 | li r0,0 |
b87dfd28 | 292 | mtspr esr,r0 |
0442ed86 WD |
293 | /*----------------------------------------------------------------*/ |
294 | /* Clear and set up some registers. */ | |
295 | /*----------------------------------------------------------------*/ | |
f901a83b WD |
296 | iccci r0,r0 /* NOTE: operands not used for 440 */ |
297 | dccci r0,r0 /* NOTE: operands not used for 440 */ | |
0442ed86 WD |
298 | sync |
299 | li r0,0 | |
300 | mtspr srr0,r0 | |
301 | mtspr srr1,r0 | |
302 | mtspr csrr0,r0 | |
303 | mtspr csrr1,r0 | |
887e2ec9 SR |
304 | /* NOTE: 440GX adds machine check status regs */ |
305 | #if defined(CONFIG_440) && !defined(CONFIG_440GP) | |
f901a83b WD |
306 | mtspr mcsrr0,r0 |
307 | mtspr mcsrr1,r0 | |
887e2ec9 | 308 | mfspr r1,mcsr |
f901a83b | 309 | mtspr mcsr,r1 |
ba56f625 | 310 | #endif |
20532833 SR |
311 | |
312 | /*----------------------------------------------------------------*/ | |
313 | /* CCR0 init */ | |
314 | /*----------------------------------------------------------------*/ | |
315 | /* Disable store gathering & broadcast, guarantee inst/data | |
316 | * cache block touch, force load/store alignment | |
317 | * (see errata 1.12: 440_33) | |
318 | */ | |
319 | lis r1,0x0030 /* store gathering & broadcast disable */ | |
320 | ori r1,r1,0x6000 /* cache touch */ | |
321 | mtspr ccr0,r1 | |
322 | ||
0442ed86 WD |
323 | /*----------------------------------------------------------------*/ |
324 | /* Initialize debug */ | |
325 | /*----------------------------------------------------------------*/ | |
887e2ec9 SR |
326 | mfspr r1,dbcr0 |
327 | andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ | |
328 | bne skip_debug_init /* if set, don't clear debug register */ | |
0442ed86 WD |
329 | mtspr dbcr0,r0 |
330 | mtspr dbcr1,r0 | |
331 | mtspr dbcr2,r0 | |
332 | mtspr iac1,r0 | |
333 | mtspr iac2,r0 | |
334 | mtspr iac3,r0 | |
335 | mtspr dac1,r0 | |
336 | mtspr dac2,r0 | |
337 | mtspr dvc1,r0 | |
338 | mtspr dvc2,r0 | |
339 | ||
340 | mfspr r1,dbsr | |
341 | mtspr dbsr,r1 /* Clear all valid bits */ | |
887e2ec9 | 342 | skip_debug_init: |
0442ed86 | 343 | |
6c5879f3 MB |
344 | #if defined (CONFIG_440SPE) |
345 | /*----------------------------------------------------------------+ | |
346 | | Initialize Core Configuration Reg1. | |
347 | | a. ICDPEI: Record even parity. Normal operation. | |
348 | | b. ICTPEI: Record even parity. Normal operation. | |
349 | | c. DCTPEI: Record even parity. Normal operation. | |
350 | | d. DCDPEI: Record even parity. Normal operation. | |
351 | | e. DCUPEI: Record even parity. Normal operation. | |
352 | | f. DCMPEI: Record even parity. Normal operation. | |
353 | | g. FCOM: Normal operation | |
354 | | h. MMUPEI: Record even parity. Normal operation. | |
355 | | i. FFF: Flush only as much data as necessary. | |
edd6cf20 | 356 | | j. TCS: Timebase increments from CPU clock. |
6c5879f3 | 357 | +-----------------------------------------------------------------*/ |
edd6cf20 | 358 | li r0,0 |
6c5879f3 MB |
359 | mtspr ccr1, r0 |
360 | ||
361 | /*----------------------------------------------------------------+ | |
362 | | Reset the timebase. | |
363 | | The previous write to CCR1 sets the timebase source. | |
364 | +-----------------------------------------------------------------*/ | |
6c5879f3 MB |
365 | mtspr tbl, r0 |
366 | mtspr tbu, r0 | |
367 | #endif | |
368 | ||
0442ed86 WD |
369 | /*----------------------------------------------------------------*/ |
370 | /* Setup interrupt vectors */ | |
371 | /*----------------------------------------------------------------*/ | |
372 | mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */ | |
f901a83b | 373 | li r1,0x0100 |
0442ed86 | 374 | mtspr ivor0,r1 /* Critical input */ |
f901a83b | 375 | li r1,0x0200 |
0442ed86 | 376 | mtspr ivor1,r1 /* Machine check */ |
f901a83b | 377 | li r1,0x0300 |
0442ed86 | 378 | mtspr ivor2,r1 /* Data storage */ |
f901a83b | 379 | li r1,0x0400 |
0442ed86 WD |
380 | mtspr ivor3,r1 /* Instruction storage */ |
381 | li r1,0x0500 | |
382 | mtspr ivor4,r1 /* External interrupt */ | |
383 | li r1,0x0600 | |
384 | mtspr ivor5,r1 /* Alignment */ | |
385 | li r1,0x0700 | |
386 | mtspr ivor6,r1 /* Program check */ | |
387 | li r1,0x0800 | |
388 | mtspr ivor7,r1 /* Floating point unavailable */ | |
389 | li r1,0x0c00 | |
390 | mtspr ivor8,r1 /* System call */ | |
efa35cf1 | 391 | li r1,0x0a00 |
83b4cfa3 | 392 | mtspr ivor9,r1 /* Auxiliary Processor unavailable */ |
efa35cf1 GB |
393 | li r1,0x0900 |
394 | mtspr ivor10,r1 /* Decrementer */ | |
0442ed86 | 395 | li r1,0x1300 |
efa35cf1 GB |
396 | mtspr ivor13,r1 /* Data TLB error */ |
397 | li r1,0x1400 | |
0442ed86 WD |
398 | mtspr ivor14,r1 /* Instr TLB error */ |
399 | li r1,0x2000 | |
400 | mtspr ivor15,r1 /* Debug */ | |
401 | ||
402 | /*----------------------------------------------------------------*/ | |
403 | /* Configure cache regions */ | |
404 | /*----------------------------------------------------------------*/ | |
405 | mtspr inv0,r0 | |
406 | mtspr inv1,r0 | |
407 | mtspr inv2,r0 | |
408 | mtspr inv3,r0 | |
409 | mtspr dnv0,r0 | |
410 | mtspr dnv1,r0 | |
411 | mtspr dnv2,r0 | |
412 | mtspr dnv3,r0 | |
413 | mtspr itv0,r0 | |
414 | mtspr itv1,r0 | |
415 | mtspr itv2,r0 | |
416 | mtspr itv3,r0 | |
417 | mtspr dtv0,r0 | |
418 | mtspr dtv1,r0 | |
419 | mtspr dtv2,r0 | |
420 | mtspr dtv3,r0 | |
421 | ||
422 | /*----------------------------------------------------------------*/ | |
423 | /* Cache victim limits */ | |
424 | /*----------------------------------------------------------------*/ | |
425 | /* floors 0, ceiling max to use the entire cache -- nothing locked | |
426 | */ | |
427 | lis r1,0x0001 | |
428 | ori r1,r1,0xf800 | |
429 | mtspr ivlim,r1 | |
430 | mtspr dvlim,r1 | |
431 | ||
6c5879f3 MB |
432 | /*----------------------------------------------------------------+ |
433 | |Initialize MMUCR[STID] = 0. | |
434 | +-----------------------------------------------------------------*/ | |
435 | mfspr r0,mmucr | |
436 | addis r1,0,0xFFFF | |
437 | ori r1,r1,0xFF00 | |
438 | and r0,r0,r1 | |
439 | mtspr mmucr,r0 | |
440 | ||
0442ed86 WD |
441 | /*----------------------------------------------------------------*/ |
442 | /* Clear all TLB entries -- TID = 0, TS = 0 */ | |
443 | /*----------------------------------------------------------------*/ | |
6c5879f3 | 444 | addis r0,0,0x0000 |
0442ed86 WD |
445 | li r1,0x003f /* 64 TLB entries */ |
446 | mtctr r1 | |
6c5879f3 MB |
447 | rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ |
448 | tlbwe r0,r1,0x0001 | |
449 | tlbwe r0,r1,0x0002 | |
0442ed86 | 450 | subi r1,r1,0x0001 |
6c5879f3 | 451 | bdnz rsttlb |
0442ed86 WD |
452 | |
453 | /*----------------------------------------------------------------*/ | |
454 | /* TLB entry setup -- step thru tlbtab */ | |
455 | /*----------------------------------------------------------------*/ | |
692519b1 RJ |
456 | #if defined(CONFIG_440SPE) |
457 | /*----------------------------------------------------------------*/ | |
458 | /* We have different TLB tables for revA and rev B of 440SPe */ | |
459 | /*----------------------------------------------------------------*/ | |
460 | mfspr r1, PVR | |
461 | lis r0,0x5342 | |
462 | ori r0,r0,0x1891 | |
463 | cmpw r7,r1,r0 | |
464 | bne r7,..revA | |
465 | bl tlbtabB | |
466 | b ..goon | |
467 | ..revA: | |
468 | bl tlbtabA | |
469 | ..goon: | |
470 | #else | |
0442ed86 | 471 | bl tlbtab /* Get tlbtab pointer */ |
692519b1 | 472 | #endif |
0442ed86 WD |
473 | mr r5,r0 |
474 | li r1,0x003f /* 64 TLB entries max */ | |
475 | mtctr r1 | |
476 | li r4,0 /* TLB # */ | |
477 | ||
478 | addi r5,r5,-4 | |
479 | 1: lwzu r0,4(r5) | |
480 | cmpwi r0,0 | |
481 | beq 2f /* 0 marks end */ | |
482 | lwzu r1,4(r5) | |
483 | lwzu r2,4(r5) | |
484 | tlbwe r0,r4,0 /* TLB Word 0 */ | |
485 | tlbwe r1,r4,1 /* TLB Word 1 */ | |
486 | tlbwe r2,r4,2 /* TLB Word 2 */ | |
487 | addi r4,r4,1 /* Next TLB */ | |
488 | bdnz 1b | |
489 | ||
490 | /*----------------------------------------------------------------*/ | |
491 | /* Continue from 'normal' start */ | |
492 | /*----------------------------------------------------------------*/ | |
887e2ec9 | 493 | 2: |
887e2ec9 | 494 | bl 3f |
0442ed86 WD |
495 | b _start |
496 | ||
497 | 3: li r0,0 | |
498 | mtspr srr1,r0 /* Keep things disabled for now */ | |
499 | mflr r1 | |
500 | mtspr srr0,r1 | |
501 | rfi | |
b867d705 | 502 | #endif /* CONFIG_440 */ |
0442ed86 WD |
503 | |
504 | /* | |
505 | * r3 - 1st arg to board_init(): IMMP pointer | |
506 | * r4 - 2nd arg to board_init(): boot flag | |
507 | */ | |
887e2ec9 | 508 | #ifndef CONFIG_NAND_SPL |
0442ed86 WD |
509 | .text |
510 | .long 0x27051956 /* U-Boot Magic Number */ | |
511 | .globl version_string | |
512 | version_string: | |
513 | .ascii U_BOOT_VERSION | |
561858ee | 514 | .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" |
0442ed86 WD |
515 | .ascii CONFIG_IDENT_STRING, "\0" |
516 | ||
0442ed86 | 517 | . = EXC_OFF_SYS_RESET |
efa35cf1 GB |
518 | .globl _start_of_vectors |
519 | _start_of_vectors: | |
520 | ||
521 | /* Critical input. */ | |
522 | CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) | |
523 | ||
524 | #ifdef CONFIG_440 | |
525 | /* Machine check */ | |
83b4cfa3 | 526 | MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 | 527 | #else |
83b4cfa3 | 528 | CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 GB |
529 | #endif /* CONFIG_440 */ |
530 | ||
531 | /* Data Storage exception. */ | |
532 | STD_EXCEPTION(0x300, DataStorage, UnknownException) | |
533 | ||
534 | /* Instruction Storage exception. */ | |
535 | STD_EXCEPTION(0x400, InstStorage, UnknownException) | |
536 | ||
537 | /* External Interrupt exception. */ | |
538 | STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) | |
539 | ||
540 | /* Alignment exception. */ | |
541 | . = 0x600 | |
542 | Alignment: | |
543 | EXCEPTION_PROLOG(SRR0, SRR1) | |
544 | mfspr r4,DAR | |
545 | stw r4,_DAR(r21) | |
546 | mfspr r5,DSISR | |
547 | stw r5,_DSISR(r21) | |
548 | addi r3,r1,STACK_FRAME_OVERHEAD | |
549 | li r20,MSR_KERNEL | |
550 | rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ | |
551 | lwz r6,GOT(transfer_to_handler) | |
552 | mtlr r6 | |
553 | blrl | |
554 | .L_Alignment: | |
555 | .long AlignmentException - _start + _START_OFFSET | |
556 | .long int_return - _start + _START_OFFSET | |
557 | ||
558 | /* Program check exception */ | |
559 | . = 0x700 | |
560 | ProgramCheck: | |
561 | EXCEPTION_PROLOG(SRR0, SRR1) | |
562 | addi r3,r1,STACK_FRAME_OVERHEAD | |
563 | li r20,MSR_KERNEL | |
564 | rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ | |
565 | lwz r6,GOT(transfer_to_handler) | |
566 | mtlr r6 | |
567 | blrl | |
568 | .L_ProgramCheck: | |
569 | .long ProgramCheckException - _start + _START_OFFSET | |
570 | .long int_return - _start + _START_OFFSET | |
571 | ||
572 | #ifdef CONFIG_440 | |
573 | STD_EXCEPTION(0x800, FPUnavailable, UnknownException) | |
574 | STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) | |
575 | STD_EXCEPTION(0xa00, APU, UnknownException) | |
df8a24cd | 576 | #endif |
efa35cf1 GB |
577 | STD_EXCEPTION(0xc00, SystemCall, UnknownException) |
578 | ||
579 | #ifdef CONFIG_440 | |
580 | STD_EXCEPTION(0x1300, DataTLBError, UnknownException) | |
581 | STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) | |
582 | #else | |
583 | STD_EXCEPTION(0x1000, PIT, DecrementerPITException) | |
584 | STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) | |
585 | STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) | |
586 | #endif | |
587 | CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) | |
588 | ||
589 | .globl _end_of_vectors | |
590 | _end_of_vectors: | |
591 | . = _START_OFFSET | |
887e2ec9 | 592 | #endif |
0442ed86 WD |
593 | .globl _start |
594 | _start: | |
595 | ||
596 | /*****************************************************************************/ | |
597 | #if defined(CONFIG_440) | |
598 | ||
599 | /*----------------------------------------------------------------*/ | |
600 | /* Clear and set up some registers. */ | |
601 | /*----------------------------------------------------------------*/ | |
602 | li r0,0x0000 | |
603 | lis r1,0xffff | |
604 | mtspr dec,r0 /* prevent dec exceptions */ | |
605 | mtspr tbl,r0 /* prevent fit & wdt exceptions */ | |
606 | mtspr tbu,r0 | |
607 | mtspr tsr,r1 /* clear all timer exception status */ | |
608 | mtspr tcr,r0 /* disable all */ | |
609 | mtspr esr,r0 /* clear exception syndrome register */ | |
610 | mtxer r0 /* clear integer exception register */ | |
0442ed86 WD |
611 | |
612 | /*----------------------------------------------------------------*/ | |
613 | /* Debug setup -- some (not very good) ice's need an event*/ | |
6d0f6bcf | 614 | /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ |
0442ed86 WD |
615 | /* value you need in this case 0x8cff 0000 should do the trick */ |
616 | /*----------------------------------------------------------------*/ | |
6d0f6bcf | 617 | #if defined(CONFIG_SYS_INIT_DBCR) |
0442ed86 WD |
618 | lis r1,0xffff |
619 | ori r1,r1,0xffff | |
620 | mtspr dbsr,r1 /* Clear all status bits */ | |
6d0f6bcf JCPV |
621 | lis r0,CONFIG_SYS_INIT_DBCR@h |
622 | ori r0,r0,CONFIG_SYS_INIT_DBCR@l | |
0442ed86 WD |
623 | mtspr dbcr0,r0 |
624 | isync | |
625 | #endif | |
626 | ||
627 | /*----------------------------------------------------------------*/ | |
628 | /* Setup the internal SRAM */ | |
629 | /*----------------------------------------------------------------*/ | |
630 | li r0,0 | |
887e2ec9 | 631 | |
6d0f6bcf | 632 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
c157d8e2 | 633 | /* Clear Dcache to use as RAM */ |
6d0f6bcf JCPV |
634 | addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h |
635 | ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l | |
636 | addis r4,r0,CONFIG_SYS_INIT_RAM_END@h | |
637 | ori r4,r4,CONFIG_SYS_INIT_RAM_END@l | |
c157d8e2 | 638 | rlwinm. r5,r4,0,27,31 |
f901a83b WD |
639 | rlwinm r5,r4,27,5,31 |
640 | beq ..d_ran | |
641 | addi r5,r5,0x0001 | |
c157d8e2 | 642 | ..d_ran: |
f901a83b | 643 | mtctr r5 |
c157d8e2 | 644 | ..d_ag: |
f901a83b WD |
645 | dcbz r0,r3 |
646 | addi r3,r3,32 | |
647 | bdnz ..d_ag | |
e02c521d SR |
648 | |
649 | /* | |
650 | * Lock the init-ram/stack in d-cache, so that other regions | |
651 | * may use d-cache as well | |
652 | * Note, that this current implementation locks exactly 4k | |
653 | * of d-cache, so please make sure that you don't define a | |
654 | * bigger init-ram area. Take a look at the lwmon5 440EPx | |
655 | * implementation as a reference. | |
656 | */ | |
657 | msync | |
658 | isync | |
659 | /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ | |
660 | lis r1,0x0201 | |
661 | ori r1,r1,0xf808 | |
662 | mtspr dvlim,r1 | |
663 | lis r1,0x0808 | |
664 | ori r1,r1,0x0808 | |
665 | mtspr dnv0,r1 | |
666 | mtspr dnv1,r1 | |
667 | mtspr dnv2,r1 | |
668 | mtspr dnv3,r1 | |
669 | mtspr dtv0,r1 | |
670 | mtspr dtv1,r1 | |
671 | mtspr dtv2,r1 | |
672 | mtspr dtv3,r1 | |
673 | msync | |
674 | isync | |
6d0f6bcf | 675 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
887e2ec9 SR |
676 | |
677 | /* 440EP & 440GR are only 440er PPC's without internal SRAM */ | |
678 | #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) | |
679 | /* not all PPC's have internal SRAM usable as L2-cache */ | |
2801b2d2 SR |
680 | #if defined(CONFIG_440GX) || \ |
681 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ | |
7d307936 | 682 | defined(CONFIG_460SX) |
b14ca4b6 | 683 | mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ |
ddf45cc7 DM |
684 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) |
685 | lis r1, 0x0000 | |
686 | ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ | |
687 | mtdcr L2_CACHE_CFG,r1 | |
ba56f625 | 688 | #endif |
0442ed86 | 689 | |
887e2ec9 | 690 | lis r2,0x7fff |
0442ed86 | 691 | ori r2,r2,0xffff |
b14ca4b6 | 692 | mfdcr r1,ISRAM0_DPC |
0442ed86 | 693 | and r1,r1,r2 /* Disable parity check */ |
b14ca4b6 DM |
694 | mtdcr ISRAM0_DPC,r1 |
695 | mfdcr r1,ISRAM0_PMEG | |
887e2ec9 | 696 | and r1,r1,r2 /* Disable pwr mgmt */ |
b14ca4b6 | 697 | mtdcr ISRAM0_PMEG,r1 |
0442ed86 WD |
698 | |
699 | lis r1,0x8000 /* BAS = 8000_0000 */ | |
6e7fb6ea | 700 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) |
ba56f625 | 701 | ori r1,r1,0x0980 /* first 64k */ |
b14ca4b6 | 702 | mtdcr ISRAM0_SB0CR,r1 |
ba56f625 WD |
703 | lis r1,0x8001 |
704 | ori r1,r1,0x0980 /* second 64k */ | |
b14ca4b6 | 705 | mtdcr ISRAM0_SB1CR,r1 |
ba56f625 WD |
706 | lis r1, 0x8002 |
707 | ori r1,r1, 0x0980 /* third 64k */ | |
b14ca4b6 | 708 | mtdcr ISRAM0_SB2CR,r1 |
ba56f625 WD |
709 | lis r1, 0x8003 |
710 | ori r1,r1, 0x0980 /* fourth 64k */ | |
b14ca4b6 | 711 | mtdcr ISRAM0_SB3CR,r1 |
ddf45cc7 DM |
712 | #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) |
713 | lis r1,0x0000 /* BAS = X_0000_0000 */ | |
6c5879f3 | 714 | ori r1,r1,0x0984 /* first 64k */ |
b14ca4b6 | 715 | mtdcr ISRAM0_SB0CR,r1 |
6c5879f3 MB |
716 | lis r1,0x0001 |
717 | ori r1,r1,0x0984 /* second 64k */ | |
b14ca4b6 | 718 | mtdcr ISRAM0_SB1CR,r1 |
6c5879f3 MB |
719 | lis r1, 0x0002 |
720 | ori r1,r1, 0x0984 /* third 64k */ | |
b14ca4b6 | 721 | mtdcr ISRAM0_SB2CR,r1 |
6c5879f3 MB |
722 | lis r1, 0x0003 |
723 | ori r1,r1, 0x0984 /* fourth 64k */ | |
b14ca4b6 | 724 | mtdcr ISRAM0_SB3CR,r1 |
ddf45cc7 DM |
725 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
726 | lis r2,0x7fff | |
727 | ori r2,r2,0xffff | |
728 | mfdcr r1,ISRAM1_DPC | |
729 | and r1,r1,r2 /* Disable parity check */ | |
730 | mtdcr ISRAM1_DPC,r1 | |
731 | mfdcr r1,ISRAM1_PMEG | |
732 | and r1,r1,r2 /* Disable pwr mgmt */ | |
733 | mtdcr ISRAM1_PMEG,r1 | |
734 | ||
735 | lis r1,0x0004 /* BAS = 4_0004_0000 */ | |
736 | ori r1,r1,0x0984 /* 64k */ | |
737 | mtdcr ISRAM1_SB0CR,r1 | |
738 | #endif | |
7d307936 FK |
739 | #elif defined(CONFIG_460SX) |
740 | lis r1,0x0000 /* BAS = 0000_0000 */ | |
741 | ori r1,r1,0x0B84 /* first 128k */ | |
b14ca4b6 | 742 | mtdcr ISRAM0_SB0CR,r1 |
7d307936 FK |
743 | lis r1,0x0001 |
744 | ori r1,r1,0x0B84 /* second 128k */ | |
b14ca4b6 | 745 | mtdcr ISRAM0_SB1CR,r1 |
7d307936 FK |
746 | lis r1, 0x0002 |
747 | ori r1,r1, 0x0B84 /* third 128k */ | |
b14ca4b6 | 748 | mtdcr ISRAM0_SB2CR,r1 |
7d307936 FK |
749 | lis r1, 0x0003 |
750 | ori r1,r1, 0x0B84 /* fourth 128k */ | |
b14ca4b6 | 751 | mtdcr ISRAM0_SB3CR,r1 |
887e2ec9 | 752 | #elif defined(CONFIG_440GP) |
0442ed86 | 753 | ori r1,r1,0x0380 /* 8k rw */ |
b14ca4b6 DM |
754 | mtdcr ISRAM0_SB0CR,r1 |
755 | mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */ | |
c157d8e2 | 756 | #endif |
887e2ec9 | 757 | #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ |
0442ed86 WD |
758 | |
759 | /*----------------------------------------------------------------*/ | |
760 | /* Setup the stack in internal SRAM */ | |
761 | /*----------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
762 | lis r1,CONFIG_SYS_INIT_RAM_ADDR@h |
763 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l | |
0442ed86 WD |
764 | li r0,0 |
765 | stwu r0,-4(r1) | |
766 | stwu r0,-4(r1) /* Terminate call chain */ | |
767 | ||
768 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
769 | lis r0,RESET_VECTOR@h /* Address of reset vector */ | |
770 | ori r0,r0, RESET_VECTOR@l | |
771 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
772 | stw r0,+12(r1) /* Save return addr (underflow vect) */ | |
773 | ||
887e2ec9 | 774 | #ifdef CONFIG_NAND_SPL |
64852d09 | 775 | bl nand_boot_common /* will not return */ |
887e2ec9 | 776 | #else |
0442ed86 | 777 | GET_GOT |
5568e613 SR |
778 | |
779 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ | |
0442ed86 | 780 | bl board_init_f |
887e2ec9 | 781 | #endif |
0442ed86 WD |
782 | |
783 | #endif /* CONFIG_440 */ | |
784 | ||
785 | /*****************************************************************************/ | |
786 | #ifdef CONFIG_IOP480 | |
787 | /*----------------------------------------------------------------------- */ | |
788 | /* Set up some machine state registers. */ | |
789 | /*----------------------------------------------------------------------- */ | |
790 | addi r0,r0,0x0000 /* initialize r0 to zero */ | |
791 | mtspr esr,r0 /* clear Exception Syndrome Reg */ | |
792 | mttcr r0 /* timer control register */ | |
793 | mtexier r0 /* disable all interrupts */ | |
0442ed86 WD |
794 | addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ |
795 | ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ | |
796 | mtdbsr r4 /* clear/reset the dbsr */ | |
797 | mtexisr r4 /* clear all pending interrupts */ | |
798 | addis r4,r0,0x8000 | |
799 | mtexier r4 /* enable critical exceptions */ | |
800 | addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ | |
801 | ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ | |
802 | mtiocr r4 /* since bit not used) & DRC to latch */ | |
803 | /* data bus on rising edge of CAS */ | |
804 | /*----------------------------------------------------------------------- */ | |
805 | /* Clear XER. */ | |
806 | /*----------------------------------------------------------------------- */ | |
807 | mtxer r0 | |
808 | /*----------------------------------------------------------------------- */ | |
809 | /* Invalidate i-cache and d-cache TAG arrays. */ | |
810 | /*----------------------------------------------------------------------- */ | |
811 | addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ | |
812 | addi r4,0,1024 /* 1/4 of I-cache */ | |
813 | ..cloop: | |
814 | iccci 0,r3 | |
815 | iccci r4,r3 | |
816 | dccci 0,r3 | |
817 | addic. r3,r3,-16 /* move back one cache line */ | |
818 | bne ..cloop /* loop back to do rest until r3 = 0 */ | |
819 | ||
820 | /* */ | |
821 | /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ | |
822 | /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ | |
823 | /* */ | |
824 | ||
825 | /* first copy IOP480 register base address into r3 */ | |
826 | addis r3,0,0x5000 /* IOP480 register base address hi */ | |
827 | /* ori r3,r3,0x0000 / IOP480 register base address lo */ | |
828 | ||
829 | #ifdef CONFIG_ADCIOP | |
830 | /* use r4 as the working variable */ | |
831 | /* turn on CS3 (LOCCTL.7) */ | |
832 | lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
833 | andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ | |
834 | stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
835 | #endif | |
836 | ||
837 | #ifdef CONFIG_DASA_SIM | |
838 | /* use r4 as the working variable */ | |
839 | /* turn on MA17 (LOCCTL.7) */ | |
840 | lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
841 | ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ | |
842 | stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
843 | #endif | |
844 | ||
845 | /* turn on MA16..13 (LCS0BRD.12 = 0) */ | |
846 | lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ | |
847 | andi. r4,r4,0xefff /* make bit 12 = 0 */ | |
848 | stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ | |
849 | ||
850 | /* make sure above stores all comlete before going on */ | |
851 | sync | |
852 | ||
853 | /* last thing, set local init status done bit (DEVINIT.31) */ | |
854 | lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ | |
855 | oris r4,r4,0x8000 /* make bit 31 = 1 */ | |
856 | stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ | |
857 | ||
858 | /* clear all pending interrupts and disable all interrupts */ | |
859 | li r4,-1 /* set p1 to 0xffffffff */ | |
860 | stw r4,0x1b0(r3) /* clear all pending interrupts */ | |
861 | stw r4,0x1b8(r3) /* clear all pending interrupts */ | |
862 | li r4,0 /* set r4 to 0 */ | |
863 | stw r4,0x1b4(r3) /* disable all interrupts */ | |
864 | stw r4,0x1bc(r3) /* disable all interrupts */ | |
865 | ||
866 | /* make sure above stores all comlete before going on */ | |
867 | sync | |
868 | ||
c821b5f1 | 869 | /* Set-up icache cacheability. */ |
6d0f6bcf JCPV |
870 | lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h |
871 | ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l | |
c821b5f1 GE |
872 | mticcr r1 |
873 | isync | |
0442ed86 | 874 | |
c821b5f1 | 875 | /* Set-up dcache cacheability. */ |
6d0f6bcf JCPV |
876 | lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h |
877 | ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l | |
c821b5f1 | 878 | mtdccr r1 |
0442ed86 | 879 | |
6d0f6bcf JCPV |
880 | addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h |
881 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ | |
0442ed86 WD |
882 | li r0, 0 /* Make room for stack frame header and */ |
883 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
884 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
885 | ||
886 | GET_GOT /* initialize GOT access */ | |
887 | ||
888 | bl board_init_f /* run first part of init code (from Flash) */ | |
889 | ||
890 | #endif /* CONFIG_IOP480 */ | |
891 | ||
892 | /*****************************************************************************/ | |
e01bd218 SR |
893 | #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ |
894 | defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ | |
dbbd1257 | 895 | defined(CONFIG_405EX) || defined(CONFIG_405) |
0442ed86 WD |
896 | /*----------------------------------------------------------------------- */ |
897 | /* Clear and set up some registers. */ | |
898 | /*----------------------------------------------------------------------- */ | |
899 | addi r4,r0,0x0000 | |
dbbd1257 | 900 | #if !defined(CONFIG_405EX) |
0442ed86 | 901 | mtspr sgr,r4 |
dbbd1257 SR |
902 | #else |
903 | /* | |
904 | * On 405EX, completely clearing the SGR leads to PPC hangup | |
905 | * upon PCIe configuration access. The PCIe memory regions | |
906 | * need to be guarded! | |
907 | */ | |
908 | lis r3,0x0000 | |
909 | ori r3,r3,0x7FFC | |
910 | mtspr sgr,r3 | |
911 | #endif | |
0442ed86 WD |
912 | mtspr dcwr,r4 |
913 | mtesr r4 /* clear Exception Syndrome Reg */ | |
914 | mttcr r4 /* clear Timer Control Reg */ | |
915 | mtxer r4 /* clear Fixed-Point Exception Reg */ | |
916 | mtevpr r4 /* clear Exception Vector Prefix Reg */ | |
0442ed86 WD |
917 | addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ |
918 | /* dbsr is cleared by setting bits to 1) */ | |
919 | mtdbsr r4 /* clear/reset the dbsr */ | |
920 | ||
c821b5f1 | 921 | /* Invalidate the i- and d-caches. */ |
0442ed86 WD |
922 | bl invalidate_icache |
923 | bl invalidate_dcache | |
924 | ||
c821b5f1 | 925 | /* Set-up icache cacheability. */ |
6d0f6bcf JCPV |
926 | lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h |
927 | ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l | |
c821b5f1 | 928 | mticcr r4 |
0442ed86 WD |
929 | isync |
930 | ||
c821b5f1 | 931 | /* Set-up dcache cacheability. */ |
6d0f6bcf JCPV |
932 | lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h |
933 | ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l | |
c821b5f1 | 934 | mtdccr r4 |
0442ed86 | 935 | |
1f4d5326 RR |
936 | #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ |
937 | && !defined (CONFIG_XILINX_405) | |
0442ed86 WD |
938 | /*----------------------------------------------------------------------- */ |
939 | /* Tune the speed and size for flash CS0 */ | |
940 | /*----------------------------------------------------------------------- */ | |
941 | bl ext_bus_cntlr_init | |
942 | #endif | |
64852d09 | 943 | |
6d0f6bcf | 944 | #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) |
dbbd1257 | 945 | /* |
c821b5f1 GE |
946 | * For boards that don't have OCM and can't use the data cache |
947 | * for their primordial stack, setup stack here directly after the | |
948 | * SDRAM is initialized in ext_bus_cntlr_init. | |
dbbd1257 | 949 | */ |
6d0f6bcf JCPV |
950 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
951 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ | |
dbbd1257 SR |
952 | |
953 | li r0, 0 /* Make room for stack frame header and */ | |
954 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
955 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
956 | /* | |
957 | * Set up a dummy frame to store reset vector as return address. | |
958 | * this causes stack underflow to reset board. | |
959 | */ | |
960 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
961 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
962 | ori r0, r0, RESET_VECTOR@l | |
963 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
964 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 965 | #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ |
0442ed86 | 966 | |
b867d705 SR |
967 | #if defined(CONFIG_405EP) |
968 | /*----------------------------------------------------------------------- */ | |
969 | /* DMA Status, clear to come up clean */ | |
970 | /*----------------------------------------------------------------------- */ | |
53677ef1 | 971 | addis r3,r0, 0xFFFF /* Clear all existing DMA status */ |
f901a83b WD |
972 | ori r3,r3, 0xFFFF |
973 | mtdcr dmasr, r3 | |
b867d705 | 974 | |
53677ef1 | 975 | bl ppc405ep_init /* do ppc405ep specific init */ |
b867d705 SR |
976 | #endif /* CONFIG_405EP */ |
977 | ||
6d0f6bcf | 978 | #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) |
e01bd218 SR |
979 | #if defined(CONFIG_405EZ) |
980 | /******************************************************************** | |
981 | * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 | |
982 | *******************************************************************/ | |
983 | /* | |
984 | * We can map the OCM on the PLB3, so map it at | |
6d0f6bcf | 985 | * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 |
e01bd218 | 986 | */ |
6d0f6bcf JCPV |
987 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
988 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
df8a24cd | 989 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
e01bd218 SR |
990 | mtdcr ocmplb3cr1,r3 /* Set PLB Access */ |
991 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ | |
992 | mtdcr ocmplb3cr2,r3 /* Set PLB Access */ | |
993 | isync | |
994 | ||
6d0f6bcf JCPV |
995 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
996 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
83b4cfa3 WD |
997 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
998 | mtdcr ocmdscr1, r3 /* Set Data Side */ | |
999 | mtdcr ocmiscr1, r3 /* Set Instruction Side */ | |
e01bd218 | 1000 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ |
83b4cfa3 WD |
1001 | mtdcr ocmdscr2, r3 /* Set Data Side */ |
1002 | mtdcr ocmiscr2, r3 /* Set Instruction Side */ | |
1003 | addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ | |
d7568947 | 1004 | mtdcr ocmdsisdpc,r3 |
e01bd218 SR |
1005 | |
1006 | isync | |
3cb86f3e | 1007 | #else /* CONFIG_405EZ */ |
0442ed86 WD |
1008 | /******************************************************************** |
1009 | * Setup OCM - On Chip Memory | |
1010 | *******************************************************************/ | |
1011 | /* Setup OCM */ | |
8bde7f77 WD |
1012 | lis r0, 0x7FFF |
1013 | ori r0, r0, 0xFFFF | |
f901a83b | 1014 | mfdcr r3, ocmiscntl /* get instr-side IRAM config */ |
3cb86f3e SR |
1015 | mfdcr r4, ocmdscntl /* get data-side IRAM config */ |
1016 | and r3, r3, r0 /* disable data-side IRAM */ | |
1017 | and r4, r4, r0 /* disable data-side IRAM */ | |
1018 | mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ | |
1019 | mtdcr ocmdscntl, r4 /* set data-side IRAM config */ | |
8bde7f77 | 1020 | isync |
0442ed86 | 1021 | |
6d0f6bcf JCPV |
1022 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
1023 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
0442ed86 WD |
1024 | mtdcr ocmdsarc, r3 |
1025 | addis r4, 0, 0xC000 /* OCM data area enabled */ | |
1026 | mtdcr ocmdscntl, r4 | |
8bde7f77 | 1027 | isync |
e01bd218 | 1028 | #endif /* CONFIG_405EZ */ |
0442ed86 WD |
1029 | #endif |
1030 | ||
1031 | /*----------------------------------------------------------------------- */ | |
1032 | /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ | |
1033 | /*----------------------------------------------------------------------- */ | |
6d0f6bcf | 1034 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
c821b5f1 GE |
1035 | li r4, PBxAP |
1036 | mtdcr ebccfga, r4 | |
6d0f6bcf JCPV |
1037 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h |
1038 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l | |
c821b5f1 GE |
1039 | mtdcr ebccfgd, r4 |
1040 | ||
1041 | addi r4, 0, PBxCR | |
1042 | mtdcr ebccfga, r4 | |
6d0f6bcf JCPV |
1043 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h |
1044 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l | |
c821b5f1 GE |
1045 | mtdcr ebccfgd, r4 |
1046 | ||
1047 | /* | |
1048 | * Enable the data cache for the 128MB storage access control region | |
6d0f6bcf | 1049 | * at CONFIG_SYS_INIT_RAM_ADDR. |
c821b5f1 GE |
1050 | */ |
1051 | mfdccr r4 | |
6d0f6bcf JCPV |
1052 | oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
1053 | ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
0442ed86 WD |
1054 | mtdccr r4 |
1055 | ||
c821b5f1 GE |
1056 | /* |
1057 | * Preallocate data cache lines to be used to avoid a subsequent | |
1058 | * cache miss and an ensuing machine check exception when exceptions | |
1059 | * are enabled. | |
1060 | */ | |
1061 | li r0, 0 | |
0442ed86 | 1062 | |
6d0f6bcf JCPV |
1063 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
1064 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
0442ed86 | 1065 | |
6d0f6bcf JCPV |
1066 | lis r4, CONFIG_SYS_INIT_RAM_END@h |
1067 | ori r4, r4, CONFIG_SYS_INIT_RAM_END@l | |
c821b5f1 GE |
1068 | |
1069 | /* | |
1070 | * Convert the size, in bytes, to the number of cache lines/blocks | |
1071 | * to preallocate. | |
1072 | */ | |
1073 | clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) | |
1074 | srwi r5, r4, L1_CACHE_SHIFT | |
1075 | beq ..load_counter | |
1076 | addi r5, r5, 0x0001 | |
1077 | ..load_counter: | |
1078 | mtctr r5 | |
1079 | ||
1080 | /* Preallocate the computed number of cache blocks. */ | |
1081 | ..alloc_dcache_block: | |
1082 | dcba r0, r3 | |
1083 | addi r3, r3, L1_CACHE_BYTES | |
1084 | bdnz ..alloc_dcache_block | |
1085 | sync | |
1086 | ||
1087 | /* | |
1088 | * Load the initial stack pointer and data area and convert the size, | |
1089 | * in bytes, to the number of words to initialize to a known value. | |
1090 | */ | |
6d0f6bcf JCPV |
1091 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
1092 | ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l | |
c821b5f1 | 1093 | |
6d0f6bcf JCPV |
1094 | lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h |
1095 | ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l | |
0442ed86 WD |
1096 | mtctr r4 |
1097 | ||
6d0f6bcf JCPV |
1098 | lis r2, CONFIG_SYS_INIT_RAM_ADDR@h |
1099 | ori r2, r2, CONFIG_SYS_INIT_RAM_END@l | |
0442ed86 | 1100 | |
6d0f6bcf JCPV |
1101 | lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h |
1102 | ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l | |
0442ed86 WD |
1103 | |
1104 | ..stackloop: | |
c821b5f1 | 1105 | stwu r4, -4(r2) |
0442ed86 WD |
1106 | bdnz ..stackloop |
1107 | ||
c821b5f1 GE |
1108 | /* |
1109 | * Make room for stack frame header and clear final stack frame so | |
1110 | * that stack backtraces terminate cleanly. | |
1111 | */ | |
1112 | stwu r0, -4(r1) | |
1113 | stwu r0, -4(r1) | |
1114 | ||
0442ed86 WD |
1115 | /* |
1116 | * Set up a dummy frame to store reset vector as return address. | |
1117 | * this causes stack underflow to reset board. | |
1118 | */ | |
1119 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1120 | addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ | |
1121 | ori r0, r0, RESET_VECTOR@l | |
1122 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1123 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
1124 | ||
6d0f6bcf JCPV |
1125 | #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ |
1126 | (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) | |
0442ed86 WD |
1127 | /* |
1128 | * Stack in OCM. | |
1129 | */ | |
1130 | ||
1131 | /* Set up Stack at top of OCM */ | |
6d0f6bcf JCPV |
1132 | lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h |
1133 | ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l | |
0442ed86 WD |
1134 | |
1135 | /* Set up a zeroized stack frame so that backtrace works right */ | |
1136 | li r0, 0 | |
1137 | stwu r0, -4(r1) | |
1138 | stwu r0, -4(r1) | |
1139 | ||
1140 | /* | |
1141 | * Set up a dummy frame to store reset vector as return address. | |
1142 | * this causes stack underflow to reset board. | |
1143 | */ | |
1144 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1145 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
1146 | ori r0, r0, RESET_VECTOR@l | |
1147 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1148 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 1149 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 1150 | |
c440bfe6 | 1151 | #ifdef CONFIG_NAND_SPL |
64852d09 | 1152 | bl nand_boot_common /* will not return */ |
c440bfe6 | 1153 | #else |
0442ed86 WD |
1154 | GET_GOT /* initialize GOT access */ |
1155 | ||
f901a83b | 1156 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ |
0442ed86 WD |
1157 | |
1158 | /* NEVER RETURNS! */ | |
1159 | bl board_init_f /* run first part of init code (from Flash) */ | |
c440bfe6 | 1160 | #endif /* CONFIG_NAND_SPL */ |
0442ed86 | 1161 | |
12f34241 WD |
1162 | #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ |
1163 | /*----------------------------------------------------------------------- */ | |
0442ed86 WD |
1164 | |
1165 | ||
887e2ec9 | 1166 | #ifndef CONFIG_NAND_SPL |
0442ed86 WD |
1167 | /* |
1168 | * This code finishes saving the registers to the exception frame | |
1169 | * and jumps to the appropriate handler for the exception. | |
1170 | * Register r21 is pointer into trap frame, r1 has new stack pointer. | |
1171 | */ | |
1172 | .globl transfer_to_handler | |
1173 | transfer_to_handler: | |
1174 | stw r22,_NIP(r21) | |
1175 | lis r22,MSR_POW@h | |
1176 | andc r23,r23,r22 | |
1177 | stw r23,_MSR(r21) | |
1178 | SAVE_GPR(7, r21) | |
1179 | SAVE_4GPRS(8, r21) | |
1180 | SAVE_8GPRS(12, r21) | |
1181 | SAVE_8GPRS(24, r21) | |
0442ed86 WD |
1182 | mflr r23 |
1183 | andi. r24,r23,0x3f00 /* get vector offset */ | |
1184 | stw r24,TRAP(r21) | |
1185 | li r22,0 | |
1186 | stw r22,RESULT(r21) | |
1187 | mtspr SPRG2,r22 /* r1 is now kernel sp */ | |
0442ed86 WD |
1188 | lwz r24,0(r23) /* virtual address of handler */ |
1189 | lwz r23,4(r23) /* where to go when done */ | |
1190 | mtspr SRR0,r24 | |
1191 | mtspr SRR1,r20 | |
1192 | mtlr r23 | |
1193 | SYNC | |
1194 | rfi /* jump to handler, enable MMU */ | |
1195 | ||
1196 | int_return: | |
1197 | mfmsr r28 /* Disable interrupts */ | |
1198 | li r4,0 | |
1199 | ori r4,r4,MSR_EE | |
1200 | andc r28,r28,r4 | |
1201 | SYNC /* Some chip revs need this... */ | |
1202 | mtmsr r28 | |
1203 | SYNC | |
1204 | lwz r2,_CTR(r1) | |
1205 | lwz r0,_LINK(r1) | |
1206 | mtctr r2 | |
1207 | mtlr r0 | |
1208 | lwz r2,_XER(r1) | |
1209 | lwz r0,_CCR(r1) | |
1210 | mtspr XER,r2 | |
1211 | mtcrf 0xFF,r0 | |
1212 | REST_10GPRS(3, r1) | |
1213 | REST_10GPRS(13, r1) | |
1214 | REST_8GPRS(23, r1) | |
1215 | REST_GPR(31, r1) | |
1216 | lwz r2,_NIP(r1) /* Restore environment */ | |
1217 | lwz r0,_MSR(r1) | |
1218 | mtspr SRR0,r2 | |
1219 | mtspr SRR1,r0 | |
1220 | lwz r0,GPR0(r1) | |
1221 | lwz r2,GPR2(r1) | |
1222 | lwz r1,GPR1(r1) | |
1223 | SYNC | |
1224 | rfi | |
1225 | ||
1226 | crit_return: | |
1227 | mfmsr r28 /* Disable interrupts */ | |
1228 | li r4,0 | |
1229 | ori r4,r4,MSR_EE | |
1230 | andc r28,r28,r4 | |
1231 | SYNC /* Some chip revs need this... */ | |
1232 | mtmsr r28 | |
1233 | SYNC | |
1234 | lwz r2,_CTR(r1) | |
1235 | lwz r0,_LINK(r1) | |
1236 | mtctr r2 | |
1237 | mtlr r0 | |
1238 | lwz r2,_XER(r1) | |
1239 | lwz r0,_CCR(r1) | |
1240 | mtspr XER,r2 | |
1241 | mtcrf 0xFF,r0 | |
1242 | REST_10GPRS(3, r1) | |
1243 | REST_10GPRS(13, r1) | |
1244 | REST_8GPRS(23, r1) | |
1245 | REST_GPR(31, r1) | |
1246 | lwz r2,_NIP(r1) /* Restore environment */ | |
1247 | lwz r0,_MSR(r1) | |
83b4cfa3 WD |
1248 | mtspr csrr0,r2 |
1249 | mtspr csrr1,r0 | |
0442ed86 WD |
1250 | lwz r0,GPR0(r1) |
1251 | lwz r2,GPR2(r1) | |
1252 | lwz r1,GPR1(r1) | |
1253 | SYNC | |
1254 | rfci | |
1255 | ||
efa35cf1 GB |
1256 | #ifdef CONFIG_440 |
1257 | mck_return: | |
83b4cfa3 WD |
1258 | mfmsr r28 /* Disable interrupts */ |
1259 | li r4,0 | |
1260 | ori r4,r4,MSR_EE | |
1261 | andc r28,r28,r4 | |
1262 | SYNC /* Some chip revs need this... */ | |
1263 | mtmsr r28 | |
1264 | SYNC | |
1265 | lwz r2,_CTR(r1) | |
1266 | lwz r0,_LINK(r1) | |
1267 | mtctr r2 | |
1268 | mtlr r0 | |
1269 | lwz r2,_XER(r1) | |
1270 | lwz r0,_CCR(r1) | |
1271 | mtspr XER,r2 | |
1272 | mtcrf 0xFF,r0 | |
1273 | REST_10GPRS(3, r1) | |
1274 | REST_10GPRS(13, r1) | |
1275 | REST_8GPRS(23, r1) | |
1276 | REST_GPR(31, r1) | |
1277 | lwz r2,_NIP(r1) /* Restore environment */ | |
1278 | lwz r0,_MSR(r1) | |
1279 | mtspr mcsrr0,r2 | |
1280 | mtspr mcsrr1,r0 | |
1281 | lwz r0,GPR0(r1) | |
1282 | lwz r2,GPR2(r1) | |
1283 | lwz r1,GPR1(r1) | |
1284 | SYNC | |
1285 | rfmci | |
efa35cf1 GB |
1286 | #endif /* CONFIG_440 */ |
1287 | ||
1288 | ||
0442ed86 WD |
1289 | .globl get_pvr |
1290 | get_pvr: | |
1291 | mfspr r3, PVR | |
1292 | blr | |
1293 | ||
0442ed86 WD |
1294 | /*------------------------------------------------------------------------------- */ |
1295 | /* Function: out16 */ | |
1296 | /* Description: Output 16 bits */ | |
1297 | /*------------------------------------------------------------------------------- */ | |
1298 | .globl out16 | |
1299 | out16: | |
1300 | sth r4,0x0000(r3) | |
1301 | blr | |
1302 | ||
1303 | /*------------------------------------------------------------------------------- */ | |
1304 | /* Function: out16r */ | |
1305 | /* Description: Byte reverse and output 16 bits */ | |
1306 | /*------------------------------------------------------------------------------- */ | |
1307 | .globl out16r | |
1308 | out16r: | |
1309 | sthbrx r4,r0,r3 | |
1310 | blr | |
1311 | ||
0442ed86 WD |
1312 | /*------------------------------------------------------------------------------- */ |
1313 | /* Function: out32r */ | |
1314 | /* Description: Byte reverse and output 32 bits */ | |
1315 | /*------------------------------------------------------------------------------- */ | |
1316 | .globl out32r | |
1317 | out32r: | |
1318 | stwbrx r4,r0,r3 | |
1319 | blr | |
1320 | ||
1321 | /*------------------------------------------------------------------------------- */ | |
1322 | /* Function: in16 */ | |
1323 | /* Description: Input 16 bits */ | |
1324 | /*------------------------------------------------------------------------------- */ | |
1325 | .globl in16 | |
1326 | in16: | |
1327 | lhz r3,0x0000(r3) | |
1328 | blr | |
1329 | ||
1330 | /*------------------------------------------------------------------------------- */ | |
1331 | /* Function: in16r */ | |
1332 | /* Description: Input 16 bits and byte reverse */ | |
1333 | /*------------------------------------------------------------------------------- */ | |
1334 | .globl in16r | |
1335 | in16r: | |
1336 | lhbrx r3,r0,r3 | |
1337 | blr | |
1338 | ||
0442ed86 WD |
1339 | /*------------------------------------------------------------------------------- */ |
1340 | /* Function: in32r */ | |
1341 | /* Description: Input 32 bits and byte reverse */ | |
1342 | /*------------------------------------------------------------------------------- */ | |
1343 | .globl in32r | |
1344 | in32r: | |
1345 | lwbrx r3,r0,r3 | |
1346 | blr | |
1347 | ||
0442ed86 WD |
1348 | /* |
1349 | * void relocate_code (addr_sp, gd, addr_moni) | |
1350 | * | |
1351 | * This "function" does not return, instead it continues in RAM | |
1352 | * after relocating the monitor code. | |
1353 | * | |
c821b5f1 GE |
1354 | * r3 = Relocated stack pointer |
1355 | * r4 = Relocated global data pointer | |
1356 | * r5 = Relocated text pointer | |
0442ed86 WD |
1357 | */ |
1358 | .globl relocate_code | |
1359 | relocate_code: | |
6d0f6bcf | 1360 | #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) |
9b94ac61 | 1361 | /* |
c821b5f1 GE |
1362 | * We need to flush the initial global data (gd_t) before the dcache |
1363 | * will be invalidated. | |
9b94ac61 SR |
1364 | */ |
1365 | ||
c821b5f1 GE |
1366 | /* Save registers */ |
1367 | mr r9, r3 | |
1368 | mr r10, r4 | |
1369 | mr r11, r5 | |
9b94ac61 | 1370 | |
c821b5f1 GE |
1371 | /* Flush initial global data range */ |
1372 | mr r3, r4 | |
6d0f6bcf | 1373 | addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l |
9b94ac61 SR |
1374 | bl flush_dcache_range |
1375 | ||
6d0f6bcf | 1376 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) |
c821b5f1 GE |
1377 | /* |
1378 | * Undo the earlier data cache set-up for the primordial stack and | |
1379 | * data area. First, invalidate the data cache and then disable data | |
1380 | * cacheability for that area. Finally, restore the EBC values, if | |
1381 | * any. | |
1382 | */ | |
1383 | ||
1384 | /* Invalidate the primordial stack and data area in cache */ | |
6d0f6bcf JCPV |
1385 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
1386 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
c821b5f1 | 1387 | |
6d0f6bcf JCPV |
1388 | lis r4, CONFIG_SYS_INIT_RAM_END@h |
1389 | ori r4, r4, CONFIG_SYS_INIT_RAM_END@l | |
c821b5f1 GE |
1390 | add r4, r4, r3 |
1391 | ||
1392 | bl invalidate_dcache_range | |
1393 | ||
1394 | /* Disable cacheability for the region */ | |
1395 | mfdccr r3 | |
6d0f6bcf JCPV |
1396 | lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
1397 | ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
c821b5f1 GE |
1398 | and r3, r3, r4 |
1399 | mtdccr r3 | |
1400 | ||
1401 | /* Restore the EBC parameters */ | |
1402 | li r3, PBxAP | |
1403 | mtdcr ebccfga, r3 | |
1404 | lis r3, PBxAP_VAL@h | |
1405 | ori r3, r3, PBxAP_VAL@l | |
1406 | mtdcr ebccfgd, r3 | |
1407 | ||
1408 | li r3, PBxCR | |
1409 | mtdcr ebccfga, r3 | |
1410 | lis r3, PBxCR_VAL@h | |
1411 | ori r3, r3, PBxCR_VAL@l | |
1412 | mtdcr ebccfgd, r3 | |
6d0f6bcf | 1413 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
c821b5f1 GE |
1414 | |
1415 | /* Restore registers */ | |
1416 | mr r3, r9 | |
1417 | mr r4, r10 | |
1418 | mr r5, r11 | |
6d0f6bcf | 1419 | #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
e02c521d | 1420 | |
6d0f6bcf | 1421 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
e02c521d SR |
1422 | /* |
1423 | * Unlock the previously locked d-cache | |
1424 | */ | |
1425 | msync | |
1426 | isync | |
1427 | /* set TFLOOR/NFLOOR to 0 again */ | |
1428 | lis r6,0x0001 | |
1429 | ori r6,r6,0xf800 | |
1430 | mtspr dvlim,r6 | |
1431 | lis r6,0x0000 | |
1432 | ori r6,r6,0x0000 | |
1433 | mtspr dnv0,r6 | |
1434 | mtspr dnv1,r6 | |
1435 | mtspr dnv2,r6 | |
1436 | mtspr dnv3,r6 | |
1437 | mtspr dtv0,r6 | |
1438 | mtspr dtv1,r6 | |
1439 | mtspr dtv2,r6 | |
1440 | mtspr dtv3,r6 | |
1441 | msync | |
1442 | isync | |
6d0f6bcf | 1443 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
e02c521d | 1444 | |
887e2ec9 SR |
1445 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
1446 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
2801b2d2 | 1447 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
7d307936 FK |
1448 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
1449 | defined(CONFIG_460SX) | |
a4c8d138 SR |
1450 | /* |
1451 | * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) | |
1452 | * to speed up the boot process. Now this cache needs to be disabled. | |
1453 | */ | |
1454 | iccci 0,0 /* Invalidate inst cache */ | |
1455 | dccci 0,0 /* Invalidate data cache, now no longer our stack */ | |
c157d8e2 | 1456 | sync |
a4c8d138 | 1457 | isync |
25fb4eaa SR |
1458 | |
1459 | /* Clear all potential pending exceptions */ | |
1460 | mfspr r1,mcsr | |
1461 | mtspr mcsr,r1 | |
6d0f6bcf JCPV |
1462 | #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH |
1463 | addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ | |
85dc2a7f NG |
1464 | #else |
1465 | addi r1,r0,0x0000 /* Default TLB entry is #0 */ | |
6d0f6bcf | 1466 | #endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */ |
c157d8e2 | 1467 | tlbre r0,r1,0x0002 /* Read contents */ |
6e7fb6ea | 1468 | ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ |
f901a83b | 1469 | tlbwe r0,r1,0x0002 /* Save it out */ |
a4c8d138 | 1470 | sync |
c157d8e2 | 1471 | isync |
c821b5f1 | 1472 | #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ |
0442ed86 WD |
1473 | mr r1, r3 /* Set new stack pointer */ |
1474 | mr r9, r4 /* Save copy of Init Data pointer */ | |
1475 | mr r10, r5 /* Save copy of Destination Address */ | |
1476 | ||
1477 | mr r3, r5 /* Destination Address */ | |
6d0f6bcf JCPV |
1478 | lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ |
1479 | ori r4, r4, CONFIG_SYS_MONITOR_BASE@l | |
3b57fe0a WD |
1480 | lwz r5, GOT(__init_end) |
1481 | sub r5, r5, r4 | |
9b94ac61 | 1482 | li r6, L1_CACHE_BYTES /* Cache Line Size */ |
0442ed86 WD |
1483 | |
1484 | /* | |
1485 | * Fix GOT pointer: | |
1486 | * | |
6d0f6bcf | 1487 | * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address |
0442ed86 WD |
1488 | * |
1489 | * Offset: | |
1490 | */ | |
1491 | sub r15, r10, r4 | |
1492 | ||
1493 | /* First our own GOT */ | |
1494 | add r14, r14, r15 | |
c821b5f1 | 1495 | /* then the one used by the C code */ |
0442ed86 WD |
1496 | add r30, r30, r15 |
1497 | ||
1498 | /* | |
1499 | * Now relocate code | |
1500 | */ | |
1501 | ||
1502 | cmplw cr1,r3,r4 | |
1503 | addi r0,r5,3 | |
1504 | srwi. r0,r0,2 | |
1505 | beq cr1,4f /* In place copy is not necessary */ | |
1506 | beq 7f /* Protect against 0 count */ | |
1507 | mtctr r0 | |
1508 | bge cr1,2f | |
1509 | ||
1510 | la r8,-4(r4) | |
1511 | la r7,-4(r3) | |
1512 | 1: lwzu r0,4(r8) | |
1513 | stwu r0,4(r7) | |
1514 | bdnz 1b | |
1515 | b 4f | |
1516 | ||
1517 | 2: slwi r0,r0,2 | |
1518 | add r8,r4,r0 | |
1519 | add r7,r3,r0 | |
1520 | 3: lwzu r0,-4(r8) | |
1521 | stwu r0,-4(r7) | |
1522 | bdnz 3b | |
1523 | ||
1524 | /* | |
1525 | * Now flush the cache: note that we must start from a cache aligned | |
1526 | * address. Otherwise we might miss one cache line. | |
1527 | */ | |
1528 | 4: cmpwi r6,0 | |
1529 | add r5,r3,r5 | |
1530 | beq 7f /* Always flush prefetch queue in any case */ | |
1531 | subi r0,r6,1 | |
1532 | andc r3,r3,r0 | |
1533 | mr r4,r3 | |
1534 | 5: dcbst 0,r4 | |
1535 | add r4,r4,r6 | |
1536 | cmplw r4,r5 | |
1537 | blt 5b | |
1538 | sync /* Wait for all dcbst to complete on bus */ | |
1539 | mr r4,r3 | |
1540 | 6: icbi 0,r4 | |
1541 | add r4,r4,r6 | |
1542 | cmplw r4,r5 | |
1543 | blt 6b | |
1544 | 7: sync /* Wait for all icbi to complete on bus */ | |
1545 | isync | |
1546 | ||
1547 | /* | |
1548 | * We are done. Do not return, instead branch to second part of board | |
1549 | * initialization, now running from RAM. | |
1550 | */ | |
1551 | ||
efa35cf1 | 1552 | addi r0, r10, in_ram - _start + _START_OFFSET |
0442ed86 WD |
1553 | mtlr r0 |
1554 | blr /* NEVER RETURNS! */ | |
1555 | ||
1556 | in_ram: | |
1557 | ||
1558 | /* | |
1559 | * Relocation Function, r14 point to got2+0x8000 | |
1560 | * | |
1561 | * Adjust got2 pointers, no need to check for 0, this code | |
1562 | * already puts a few entries in the table. | |
1563 | */ | |
1564 | li r0,__got2_entries@sectoff@l | |
1565 | la r3,GOT(_GOT2_TABLE_) | |
1566 | lwz r11,GOT(_GOT2_TABLE_) | |
1567 | mtctr r0 | |
1568 | sub r11,r3,r11 | |
1569 | addi r3,r3,-4 | |
1570 | 1: lwzu r0,4(r3) | |
1571 | add r0,r0,r11 | |
1572 | stw r0,0(r3) | |
1573 | bdnz 1b | |
1574 | ||
1575 | /* | |
1576 | * Now adjust the fixups and the pointers to the fixups | |
1577 | * in case we need to move ourselves again. | |
1578 | */ | |
1579 | 2: li r0,__fixup_entries@sectoff@l | |
1580 | lwz r3,GOT(_FIXUP_TABLE_) | |
1581 | cmpwi r0,0 | |
1582 | mtctr r0 | |
1583 | addi r3,r3,-4 | |
1584 | beq 4f | |
1585 | 3: lwzu r4,4(r3) | |
1586 | lwzux r0,r4,r11 | |
1587 | add r0,r0,r11 | |
1588 | stw r10,0(r3) | |
1589 | stw r0,0(r4) | |
1590 | bdnz 3b | |
1591 | 4: | |
1592 | clear_bss: | |
1593 | /* | |
1594 | * Now clear BSS segment | |
1595 | */ | |
5d232d0e | 1596 | lwz r3,GOT(__bss_start) |
0442ed86 WD |
1597 | lwz r4,GOT(_end) |
1598 | ||
1599 | cmplw 0, r3, r4 | |
42ed33ff | 1600 | beq 7f |
0442ed86 WD |
1601 | |
1602 | li r0, 0 | |
42ed33ff AG |
1603 | |
1604 | andi. r5, r4, 3 | |
1605 | beq 6f | |
1606 | sub r4, r4, r5 | |
1607 | mtctr r5 | |
1608 | mr r5, r4 | |
1609 | 5: stb r0, 0(r5) | |
1610 | addi r5, r5, 1 | |
1611 | bdnz 5b | |
1612 | 6: | |
0442ed86 WD |
1613 | stw r0, 0(r3) |
1614 | addi r3, r3, 4 | |
1615 | cmplw 0, r3, r4 | |
42ed33ff | 1616 | bne 6b |
0442ed86 | 1617 | |
42ed33ff | 1618 | 7: |
0442ed86 WD |
1619 | mr r3, r9 /* Init Data pointer */ |
1620 | mr r4, r10 /* Destination Address */ | |
1621 | bl board_init_r | |
1622 | ||
0442ed86 WD |
1623 | /* |
1624 | * Copy exception vector code to low memory | |
1625 | * | |
1626 | * r3: dest_addr | |
1627 | * r7: source address, r8: end address, r9: target address | |
1628 | */ | |
1629 | .globl trap_init | |
1630 | trap_init: | |
efa35cf1 | 1631 | lwz r7, GOT(_start_of_vectors) |
0442ed86 WD |
1632 | lwz r8, GOT(_end_of_vectors) |
1633 | ||
682011ff | 1634 | li r9, 0x100 /* reset vector always at 0x100 */ |
0442ed86 WD |
1635 | |
1636 | cmplw 0, r7, r8 | |
1637 | bgelr /* return if r7>=r8 - just in case */ | |
1638 | ||
1639 | mflr r4 /* save link register */ | |
1640 | 1: | |
1641 | lwz r0, 0(r7) | |
1642 | stw r0, 0(r9) | |
1643 | addi r7, r7, 4 | |
1644 | addi r9, r9, 4 | |
1645 | cmplw 0, r7, r8 | |
1646 | bne 1b | |
1647 | ||
1648 | /* | |
1649 | * relocate `hdlr' and `int_return' entries | |
1650 | */ | |
efa35cf1 GB |
1651 | li r7, .L_MachineCheck - _start + _START_OFFSET |
1652 | li r8, Alignment - _start + _START_OFFSET | |
0442ed86 WD |
1653 | 2: |
1654 | bl trap_reloc | |
efa35cf1 | 1655 | addi r7, r7, 0x100 /* next exception vector */ |
0442ed86 WD |
1656 | cmplw 0, r7, r8 |
1657 | blt 2b | |
1658 | ||
efa35cf1 | 1659 | li r7, .L_Alignment - _start + _START_OFFSET |
0442ed86 WD |
1660 | bl trap_reloc |
1661 | ||
efa35cf1 | 1662 | li r7, .L_ProgramCheck - _start + _START_OFFSET |
0442ed86 WD |
1663 | bl trap_reloc |
1664 | ||
efa35cf1 GB |
1665 | #ifdef CONFIG_440 |
1666 | li r7, .L_FPUnavailable - _start + _START_OFFSET | |
83b4cfa3 | 1667 | bl trap_reloc |
0442ed86 | 1668 | |
efa35cf1 | 1669 | li r7, .L_Decrementer - _start + _START_OFFSET |
83b4cfa3 | 1670 | bl trap_reloc |
efa35cf1 GB |
1671 | |
1672 | li r7, .L_APU - _start + _START_OFFSET | |
83b4cfa3 | 1673 | bl trap_reloc |
df8a24cd | 1674 | |
83b4cfa3 WD |
1675 | li r7, .L_InstructionTLBError - _start + _START_OFFSET |
1676 | bl trap_reloc | |
efa35cf1 | 1677 | |
83b4cfa3 WD |
1678 | li r7, .L_DataTLBError - _start + _START_OFFSET |
1679 | bl trap_reloc | |
efa35cf1 GB |
1680 | #else /* CONFIG_440 */ |
1681 | li r7, .L_PIT - _start + _START_OFFSET | |
83b4cfa3 | 1682 | bl trap_reloc |
efa35cf1 GB |
1683 | |
1684 | li r7, .L_InstructionTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1685 | bl trap_reloc |
efa35cf1 GB |
1686 | |
1687 | li r7, .L_DataTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1688 | bl trap_reloc |
efa35cf1 GB |
1689 | #endif /* CONFIG_440 */ |
1690 | ||
83b4cfa3 WD |
1691 | li r7, .L_DebugBreakpoint - _start + _START_OFFSET |
1692 | bl trap_reloc | |
0442ed86 | 1693 | |
887e2ec9 | 1694 | #if !defined(CONFIG_440) |
9a7b408c SR |
1695 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1696 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
1697 | mtmsr r7 /* change MSR */ | |
1698 | #else | |
887e2ec9 SR |
1699 | bl __440_msr_set |
1700 | b __440_msr_continue | |
9a7b408c | 1701 | |
887e2ec9 | 1702 | __440_msr_set: |
9a7b408c SR |
1703 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1704 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
1705 | mtspr srr1,r7 | |
1706 | mflr r7 | |
1707 | mtspr srr0,r7 | |
1708 | rfi | |
887e2ec9 | 1709 | __440_msr_continue: |
9a7b408c SR |
1710 | #endif |
1711 | ||
0442ed86 WD |
1712 | mtlr r4 /* restore link register */ |
1713 | blr | |
1714 | ||
1715 | /* | |
1716 | * Function: relocate entries for one exception vector | |
1717 | */ | |
1718 | trap_reloc: | |
1719 | lwz r0, 0(r7) /* hdlr ... */ | |
1720 | add r0, r0, r3 /* ... += dest_addr */ | |
1721 | stw r0, 0(r7) | |
1722 | ||
1723 | lwz r0, 4(r7) /* int_return ... */ | |
1724 | add r0, r0, r3 /* ... += dest_addr */ | |
1725 | stw r0, 4(r7) | |
1726 | ||
1727 | blr | |
cf959c7d SR |
1728 | |
1729 | #if defined(CONFIG_440) | |
1730 | /*----------------------------------------------------------------------------+ | |
1731 | | dcbz_area. | |
1732 | +----------------------------------------------------------------------------*/ | |
1733 | function_prolog(dcbz_area) | |
1734 | rlwinm. r5,r4,0,27,31 | |
83b4cfa3 WD |
1735 | rlwinm r5,r4,27,5,31 |
1736 | beq ..d_ra2 | |
1737 | addi r5,r5,0x0001 | |
1738 | ..d_ra2:mtctr r5 | |
1739 | ..d_ag2:dcbz r0,r3 | |
1740 | addi r3,r3,32 | |
1741 | bdnz ..d_ag2 | |
cf959c7d SR |
1742 | sync |
1743 | blr | |
1744 | function_epilog(dcbz_area) | |
cf959c7d | 1745 | #endif /* CONFIG_440 */ |
887e2ec9 | 1746 | #endif /* CONFIG_NAND_SPL */ |
b867d705 | 1747 | |
cf959c7d SR |
1748 | /*------------------------------------------------------------------------------- */ |
1749 | /* Function: in8 */ | |
1750 | /* Description: Input 8 bits */ | |
1751 | /*------------------------------------------------------------------------------- */ | |
1752 | .globl in8 | |
1753 | in8: | |
1754 | lbz r3,0x0000(r3) | |
1755 | blr | |
1756 | ||
1757 | /*------------------------------------------------------------------------------- */ | |
1758 | /* Function: out8 */ | |
1759 | /* Description: Output 8 bits */ | |
1760 | /*------------------------------------------------------------------------------- */ | |
1761 | .globl out8 | |
1762 | out8: | |
1763 | stb r4,0x0000(r3) | |
1764 | blr | |
1765 | ||
1766 | /*------------------------------------------------------------------------------- */ | |
1767 | /* Function: out32 */ | |
1768 | /* Description: Output 32 bits */ | |
1769 | /*------------------------------------------------------------------------------- */ | |
1770 | .globl out32 | |
1771 | out32: | |
1772 | stw r4,0x0000(r3) | |
1773 | blr | |
1774 | ||
1775 | /*------------------------------------------------------------------------------- */ | |
1776 | /* Function: in32 */ | |
1777 | /* Description: Input 32 bits */ | |
1778 | /*------------------------------------------------------------------------------- */ | |
1779 | .globl in32 | |
1780 | in32: | |
1781 | lwz 3,0x0000(3) | |
1782 | blr | |
b867d705 SR |
1783 | |
1784 | /**************************************************************************/ | |
f901a83b | 1785 | /* PPC405EP specific stuff */ |
b867d705 SR |
1786 | /**************************************************************************/ |
1787 | #ifdef CONFIG_405EP | |
1788 | ppc405ep_init: | |
b828dda6 | 1789 | |
c157d8e2 | 1790 | #ifdef CONFIG_BUBINGA |
b828dda6 SR |
1791 | /* |
1792 | * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate | |
1793 | * function) to support FPGA and NVRAM accesses below. | |
1794 | */ | |
1795 | ||
1796 | lis r3,GPIO0_OSRH@h /* config GPIO output select */ | |
1797 | ori r3,r3,GPIO0_OSRH@l | |
6d0f6bcf JCPV |
1798 | lis r4,CONFIG_SYS_GPIO0_OSRH@h |
1799 | ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l | |
b828dda6 SR |
1800 | stw r4,0(r3) |
1801 | lis r3,GPIO0_OSRL@h | |
1802 | ori r3,r3,GPIO0_OSRL@l | |
6d0f6bcf JCPV |
1803 | lis r4,CONFIG_SYS_GPIO0_OSRL@h |
1804 | ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l | |
b828dda6 SR |
1805 | stw r4,0(r3) |
1806 | ||
1807 | lis r3,GPIO0_ISR1H@h /* config GPIO input select */ | |
1808 | ori r3,r3,GPIO0_ISR1H@l | |
6d0f6bcf JCPV |
1809 | lis r4,CONFIG_SYS_GPIO0_ISR1H@h |
1810 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l | |
b828dda6 SR |
1811 | stw r4,0(r3) |
1812 | lis r3,GPIO0_ISR1L@h | |
1813 | ori r3,r3,GPIO0_ISR1L@l | |
6d0f6bcf JCPV |
1814 | lis r4,CONFIG_SYS_GPIO0_ISR1L@h |
1815 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l | |
b828dda6 SR |
1816 | stw r4,0(r3) |
1817 | ||
1818 | lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ | |
1819 | ori r3,r3,GPIO0_TSRH@l | |
6d0f6bcf JCPV |
1820 | lis r4,CONFIG_SYS_GPIO0_TSRH@h |
1821 | ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l | |
b828dda6 SR |
1822 | stw r4,0(r3) |
1823 | lis r3,GPIO0_TSRL@h | |
1824 | ori r3,r3,GPIO0_TSRL@l | |
6d0f6bcf JCPV |
1825 | lis r4,CONFIG_SYS_GPIO0_TSRL@h |
1826 | ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l | |
b828dda6 SR |
1827 | stw r4,0(r3) |
1828 | ||
1829 | lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ | |
1830 | ori r3,r3,GPIO0_TCR@l | |
6d0f6bcf JCPV |
1831 | lis r4,CONFIG_SYS_GPIO0_TCR@h |
1832 | ori r4,r4,CONFIG_SYS_GPIO0_TCR@l | |
b828dda6 SR |
1833 | stw r4,0(r3) |
1834 | ||
1835 | li r3,pb1ap /* program EBC bank 1 for RTC access */ | |
1836 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1837 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1838 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
b828dda6 SR |
1839 | mtdcr ebccfgd,r3 |
1840 | li r3,pb1cr | |
1841 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1842 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1843 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
b828dda6 SR |
1844 | mtdcr ebccfgd,r3 |
1845 | ||
1846 | li r3,pb1ap /* program EBC bank 1 for RTC access */ | |
1847 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1848 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1849 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
b828dda6 SR |
1850 | mtdcr ebccfgd,r3 |
1851 | li r3,pb1cr | |
1852 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1853 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1854 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
b828dda6 SR |
1855 | mtdcr ebccfgd,r3 |
1856 | ||
1857 | li r3,pb4ap /* program EBC bank 4 for FPGA access */ | |
1858 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1859 | lis r3,CONFIG_SYS_EBC_PB4AP@h |
1860 | ori r3,r3,CONFIG_SYS_EBC_PB4AP@l | |
b828dda6 SR |
1861 | mtdcr ebccfgd,r3 |
1862 | li r3,pb4cr | |
1863 | mtdcr ebccfga,r3 | |
6d0f6bcf JCPV |
1864 | lis r3,CONFIG_SYS_EBC_PB4CR@h |
1865 | ori r3,r3,CONFIG_SYS_EBC_PB4CR@l | |
b828dda6 SR |
1866 | mtdcr ebccfgd,r3 |
1867 | #endif | |
8bde7f77 WD |
1868 | |
1869 | /* | |
1870 | !----------------------------------------------------------------------- | |
1871 | ! Check to see if chip is in bypass mode. | |
1872 | ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a | |
1873 | ! CPU reset Otherwise, skip this step and keep going. | |
f901a83b WD |
1874 | ! Note: Running BIOS in bypass mode is not supported since PLB speed |
1875 | ! will not be fast enough for the SDRAM (min 66MHz) | |
8bde7f77 | 1876 | !----------------------------------------------------------------------- |
b867d705 | 1877 | */ |
f901a83b | 1878 | mfdcr r5, CPC0_PLLMR1 |
53677ef1 | 1879 | rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ |
f901a83b | 1880 | cmpi cr0,0,r4,0x1 |
b867d705 | 1881 | |
53677ef1 WD |
1882 | beq pll_done /* if SSCS =b'1' then PLL has */ |
1883 | /* already been set */ | |
1884 | /* and CPU has been reset */ | |
1885 | /* so skip to next section */ | |
b867d705 | 1886 | |
c157d8e2 | 1887 | #ifdef CONFIG_BUBINGA |
b867d705 | 1888 | /* |
8bde7f77 WD |
1889 | !----------------------------------------------------------------------- |
1890 | ! Read NVRAM to get value to write in PLLMR. | |
1891 | ! If value has not been correctly saved, write default value | |
1892 | ! Default config values (assuming on-board 33MHz SYS_CLK) are above. | |
1893 | ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. | |
1894 | ! | |
1895 | ! WARNING: This code assumes the first three words in the nvram_t | |
f901a83b WD |
1896 | ! structure in openbios.h. Changing the beginning of |
1897 | ! the structure will break this code. | |
8bde7f77 WD |
1898 | ! |
1899 | !----------------------------------------------------------------------- | |
b867d705 | 1900 | */ |
f901a83b WD |
1901 | addis r3,0,NVRAM_BASE@h |
1902 | addi r3,r3,NVRAM_BASE@l | |
1903 | ||
1904 | lwz r4, 0(r3) | |
1905 | addis r5,0,NVRVFY1@h | |
1906 | addi r5,r5,NVRVFY1@l | |
53677ef1 | 1907 | cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ |
f901a83b WD |
1908 | bne ..no_pllset |
1909 | addi r3,r3,4 | |
1910 | lwz r4, 0(r3) | |
1911 | addis r5,0,NVRVFY2@h | |
1912 | addi r5,r5,NVRVFY2@l | |
53677ef1 | 1913 | cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ |
f901a83b WD |
1914 | bne ..no_pllset |
1915 | addi r3,r3,8 /* Skip over conf_size */ | |
1916 | lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ | |
1917 | lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ | |
1918 | rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ | |
1919 | cmpi cr0,0,r5,1 /* See if PLL is locked */ | |
1920 | beq pll_write | |
b867d705 | 1921 | ..no_pllset: |
c157d8e2 | 1922 | #endif /* CONFIG_BUBINGA */ |
b867d705 | 1923 | |
d4024bb7 JO |
1924 | #ifdef CONFIG_TAIHU |
1925 | mfdcr r4, CPC0_BOOT | |
1926 | andi. r5, r4, CPC0_BOOT_SEP@l | |
1927 | bne strap_1 /* serial eeprom present */ | |
1928 | addis r5,0,CPLD_REG0_ADDR@h | |
1929 | ori r5,r5,CPLD_REG0_ADDR@l | |
1930 | andi. r5, r5, 0x10 | |
1931 | bne _pci_66mhz | |
1932 | #endif /* CONFIG_TAIHU */ | |
1933 | ||
779e9751 SR |
1934 | #if defined(CONFIG_ZEUS) |
1935 | mfdcr r4, CPC0_BOOT | |
1936 | andi. r5, r4, CPC0_BOOT_SEP@l | |
53677ef1 | 1937 | bne strap_1 /* serial eeprom present */ |
779e9751 SR |
1938 | lis r3,0x0000 |
1939 | addi r3,r3,0x3030 | |
1940 | lis r4,0x8042 | |
1941 | addi r4,r4,0x223e | |
1942 | b 1f | |
1943 | strap_1: | |
1944 | mfdcr r3, CPC0_PLLMR0 | |
1945 | mfdcr r4, CPC0_PLLMR1 | |
1946 | b 1f | |
1947 | #endif | |
1948 | ||
53677ef1 WD |
1949 | addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ |
1950 | ori r3,r3,PLLMR0_DEFAULT@l /* */ | |
1951 | addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ | |
1952 | ori r4,r4,PLLMR1_DEFAULT@l /* */ | |
b867d705 | 1953 | |
d4024bb7 JO |
1954 | #ifdef CONFIG_TAIHU |
1955 | b 1f | |
1956 | _pci_66mhz: | |
1957 | addis r3,0,PLLMR0_DEFAULT_PCI66@h | |
1958 | ori r3,r3,PLLMR0_DEFAULT_PCI66@l | |
1959 | addis r4,0,PLLMR1_DEFAULT_PCI66@h | |
1960 | ori r4,r4,PLLMR1_DEFAULT_PCI66@l | |
1961 | b 1f | |
1962 | strap_1: | |
1963 | mfdcr r3, CPC0_PLLMR0 | |
1964 | mfdcr r4, CPC0_PLLMR1 | |
d4024bb7 JO |
1965 | #endif /* CONFIG_TAIHU */ |
1966 | ||
779e9751 | 1967 | 1: |
53677ef1 | 1968 | b pll_write /* Write the CPC0_PLLMR with new value */ |
b867d705 SR |
1969 | |
1970 | pll_done: | |
8bde7f77 WD |
1971 | /* |
1972 | !----------------------------------------------------------------------- | |
1973 | ! Clear Soft Reset Register | |
1974 | ! This is needed to enable PCI if not booting from serial EPROM | |
1975 | !----------------------------------------------------------------------- | |
b867d705 | 1976 | */ |
f901a83b WD |
1977 | addi r3, 0, 0x0 |
1978 | mtdcr CPC0_SRR, r3 | |
b867d705 | 1979 | |
f901a83b WD |
1980 | addis r3,0,0x0010 |
1981 | mtctr r3 | |
b867d705 | 1982 | pci_wait: |
f901a83b | 1983 | bdnz pci_wait |
b867d705 | 1984 | |
53677ef1 | 1985 | blr /* return to main code */ |
b867d705 SR |
1986 | |
1987 | /* | |
1988 | !----------------------------------------------------------------------------- | |
f901a83b WD |
1989 | ! Function: pll_write |
1990 | ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation | |
1991 | ! That is: | |
1992 | ! 1. Pll is first disabled (de-activated by putting in bypass mode) | |
1993 | ! 2. PLL is reset | |
1994 | ! 3. Clock dividers are set while PLL is held in reset and bypassed | |
1995 | ! 4. PLL Reset is cleared | |
1996 | ! 5. Wait 100us for PLL to lock | |
1997 | ! 6. A core reset is performed | |
b867d705 SR |
1998 | ! Input: r3 = Value to write to CPC0_PLLMR0 |
1999 | ! Input: r4 = Value to write to CPC0_PLLMR1 | |
2000 | ! Output r3 = none | |
2001 | !----------------------------------------------------------------------------- | |
2002 | */ | |
2003 | pll_write: | |
8bde7f77 WD |
2004 | mfdcr r5, CPC0_UCR |
2005 | andis. r5,r5,0xFFFF | |
53677ef1 WD |
2006 | ori r5,r5,0x0101 /* Stop the UART clocks */ |
2007 | mtdcr CPC0_UCR,r5 /* Before changing PLL */ | |
8bde7f77 WD |
2008 | |
2009 | mfdcr r5, CPC0_PLLMR1 | |
53677ef1 | 2010 | rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ |
f901a83b | 2011 | mtdcr CPC0_PLLMR1,r5 |
53677ef1 | 2012 | oris r5,r5,0x4000 /* Set PLL Reset */ |
f901a83b WD |
2013 | mtdcr CPC0_PLLMR1,r5 |
2014 | ||
53677ef1 WD |
2015 | mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ |
2016 | rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ | |
2017 | oris r5,r5,0x4000 /* Set PLL Reset */ | |
2018 | mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ | |
2019 | rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ | |
f901a83b | 2020 | mtdcr CPC0_PLLMR1,r5 |
b867d705 SR |
2021 | |
2022 | /* | |
8bde7f77 WD |
2023 | ! Wait min of 100us for PLL to lock. |
2024 | ! See CMOS 27E databook for more info. | |
2025 | ! At 200MHz, that means waiting 20,000 instructions | |
b867d705 | 2026 | */ |
f901a83b WD |
2027 | addi r3,0,20000 /* 2000 = 0x4e20 */ |
2028 | mtctr r3 | |
b867d705 | 2029 | pll_wait: |
f901a83b | 2030 | bdnz pll_wait |
8bde7f77 | 2031 | |
f901a83b WD |
2032 | oris r5,r5,0x8000 /* Enable PLL */ |
2033 | mtdcr CPC0_PLLMR1,r5 /* Engage */ | |
8bde7f77 WD |
2034 | |
2035 | /* | |
2036 | * Reset CPU to guarantee timings are OK | |
2037 | * Not sure if this is needed... | |
2038 | */ | |
2039 | addis r3,0,0x1000 | |
53677ef1 WD |
2040 | mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ |
2041 | /* execution will continue from the poweron */ | |
2042 | /* vector of 0xfffffffc */ | |
b867d705 | 2043 | #endif /* CONFIG_405EP */ |
4745acaa SR |
2044 | |
2045 | #if defined(CONFIG_440) | |
4745acaa SR |
2046 | /*----------------------------------------------------------------------------+ |
2047 | | mttlb3. | |
2048 | +----------------------------------------------------------------------------*/ | |
2049 | function_prolog(mttlb3) | |
2050 | TLBWE(4,3,2) | |
2051 | blr | |
2052 | function_epilog(mttlb3) | |
2053 | ||
2054 | /*----------------------------------------------------------------------------+ | |
2055 | | mftlb3. | |
2056 | +----------------------------------------------------------------------------*/ | |
2057 | function_prolog(mftlb3) | |
74357114 | 2058 | TLBRE(3,3,2) |
4745acaa SR |
2059 | blr |
2060 | function_epilog(mftlb3) | |
2061 | ||
2062 | /*----------------------------------------------------------------------------+ | |
2063 | | mttlb2. | |
2064 | +----------------------------------------------------------------------------*/ | |
2065 | function_prolog(mttlb2) | |
2066 | TLBWE(4,3,1) | |
2067 | blr | |
2068 | function_epilog(mttlb2) | |
2069 | ||
2070 | /*----------------------------------------------------------------------------+ | |
2071 | | mftlb2. | |
2072 | +----------------------------------------------------------------------------*/ | |
2073 | function_prolog(mftlb2) | |
74357114 | 2074 | TLBRE(3,3,1) |
4745acaa SR |
2075 | blr |
2076 | function_epilog(mftlb2) | |
2077 | ||
2078 | /*----------------------------------------------------------------------------+ | |
2079 | | mttlb1. | |
2080 | +----------------------------------------------------------------------------*/ | |
2081 | function_prolog(mttlb1) | |
2082 | TLBWE(4,3,0) | |
2083 | blr | |
2084 | function_epilog(mttlb1) | |
2085 | ||
2086 | /*----------------------------------------------------------------------------+ | |
2087 | | mftlb1. | |
2088 | +----------------------------------------------------------------------------*/ | |
2089 | function_prolog(mftlb1) | |
74357114 | 2090 | TLBRE(3,3,0) |
4745acaa SR |
2091 | blr |
2092 | function_epilog(mftlb1) | |
2093 | #endif /* CONFIG_440 */ | |
64852d09 SR |
2094 | |
2095 | #if defined(CONFIG_NAND_SPL) | |
2096 | /* | |
2097 | * void nand_boot_relocate(dst, src, bytes) | |
2098 | * | |
2099 | * r3 = Destination address to copy code to (in SDRAM) | |
2100 | * r4 = Source address to copy code from | |
2101 | * r5 = size to copy in bytes | |
2102 | */ | |
2103 | nand_boot_relocate: | |
2104 | mr r6,r3 | |
2105 | mr r7,r4 | |
2106 | mflr r8 | |
2107 | ||
2108 | /* | |
2109 | * Copy SPL from icache into SDRAM | |
2110 | */ | |
2111 | subi r3,r3,4 | |
2112 | subi r4,r4,4 | |
2113 | srwi r5,r5,2 | |
2114 | mtctr r5 | |
2115 | ..spl_loop: | |
2116 | lwzu r0,4(r4) | |
2117 | stwu r0,4(r3) | |
2118 | bdnz ..spl_loop | |
2119 | ||
2120 | /* | |
2121 | * Calculate "corrected" link register, so that we "continue" | |
2122 | * in execution in destination range | |
2123 | */ | |
2124 | sub r3,r7,r6 /* r3 = src - dst */ | |
2125 | sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ | |
2126 | mtlr r8 | |
2127 | blr | |
2128 | ||
2129 | nand_boot_common: | |
2130 | /* | |
2131 | * First initialize SDRAM. It has to be available *before* calling | |
2132 | * nand_boot(). | |
2133 | */ | |
6d0f6bcf JCPV |
2134 | lis r3,CONFIG_SYS_SDRAM_BASE@h |
2135 | ori r3,r3,CONFIG_SYS_SDRAM_BASE@l | |
64852d09 SR |
2136 | bl initdram |
2137 | ||
2138 | /* | |
2139 | * Now copy the 4k SPL code into SDRAM and continue execution | |
2140 | * from there. | |
2141 | */ | |
6d0f6bcf JCPV |
2142 | lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h |
2143 | ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l | |
2144 | lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h | |
2145 | ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l | |
2146 | lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h | |
2147 | ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l | |
64852d09 SR |
2148 | bl nand_boot_relocate |
2149 | ||
2150 | /* | |
2151 | * We're running from SDRAM now!!! | |
2152 | * | |
2153 | * It is necessary for 4xx systems to relocate from running at | |
2154 | * the original location (0xfffffxxx) to somewhere else (SDRAM | |
2155 | * preferably). This is because CS0 needs to be reconfigured for | |
2156 | * NAND access. And we can't reconfigure this CS when currently | |
2157 | * "running" from it. | |
2158 | */ | |
2159 | ||
2160 | /* | |
2161 | * Finally call nand_boot() to load main NAND U-Boot image from | |
2162 | * NAND and jump to it. | |
2163 | */ | |
2164 | bl nand_boot /* will not return */ | |
2165 | #endif /* CONFIG_NAND_SPL */ |