[people/ms/u-boot.git] / drivers / clk / clk_stm32f.c

/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <stm32_rcc.h>

#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_pwr.h>

#include <dt-bindings/mfd/stm32f7-rcc.h>

#define RCC_CR_HSION			BIT(0)
#define RCC_CR_HSEON			BIT(16)
#define RCC_CR_HSERDY			BIT(17)
#define RCC_CR_HSEBYP			BIT(18)
#define RCC_CR_CSSON			BIT(19)
#define RCC_CR_PLLON			BIT(24)
#define RCC_CR_PLLRDY			BIT(25)
#define RCC_CR_PLLSAION			BIT(28)
#define RCC_CR_PLLSAIRDY		BIT(29)

#define RCC_PLLCFGR_PLLM_MASK		GENMASK(5, 0)
#define RCC_PLLCFGR_PLLN_MASK		GENMASK(14, 6)
#define RCC_PLLCFGR_PLLP_MASK		GENMASK(17, 16)
#define RCC_PLLCFGR_PLLQ_MASK		GENMASK(27, 24)
#define RCC_PLLCFGR_PLLSRC		BIT(22)
#define RCC_PLLCFGR_PLLM_SHIFT		0
#define RCC_PLLCFGR_PLLN_SHIFT		6
#define RCC_PLLCFGR_PLLP_SHIFT		16
#define RCC_PLLCFGR_PLLQ_SHIFT		24

#define RCC_CFGR_AHB_PSC_MASK		GENMASK(7, 4)
#define RCC_CFGR_APB1_PSC_MASK		GENMASK(12, 10)
#define RCC_CFGR_APB2_PSC_MASK		GENMASK(15, 13)
#define RCC_CFGR_SW0			BIT(0)
#define RCC_CFGR_SW1			BIT(1)
#define RCC_CFGR_SW_MASK		GENMASK(1, 0)
#define RCC_CFGR_SW_HSI			0
#define RCC_CFGR_SW_HSE			RCC_CFGR_SW0
#define RCC_CFGR_SW_PLL			RCC_CFGR_SW1
#define RCC_CFGR_SWS0			BIT(2)
#define RCC_CFGR_SWS1			BIT(3)
#define RCC_CFGR_SWS_MASK		GENMASK(3, 2)
#define RCC_CFGR_SWS_HSI		0
#define RCC_CFGR_SWS_HSE		RCC_CFGR_SWS0
#define RCC_CFGR_SWS_PLL		RCC_CFGR_SWS1
#define RCC_CFGR_HPRE_SHIFT		4
#define RCC_CFGR_PPRE1_SHIFT		10
#define RCC_CFGR_PPRE2_SHIFT		13

#define RCC_PLLCFGR_PLLSAIN_MASK	GENMASK(14, 6)
#define RCC_PLLCFGR_PLLSAIP_MASK	GENMASK(17, 16)
#define RCC_PLLSAICFGR_PLLSAIN_SHIFT	6
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT	16
#define RCC_PLLSAICFGR_PLLSAIP_4	BIT(16)
#define RCC_PLLSAICFGR_PLLSAIQ_4	BIT(26)
#define RCC_PLLSAICFGR_PLLSAIR_2	BIT(29)

#define RCC_DCKCFGRX_CK48MSEL		BIT(27)
#define RCC_DCKCFGRX_SDMMC1SEL		BIT(28)
#define RCC_DCKCFGR2_SDMMC2SEL		BIT(29)

/*
 * RCC AHB1ENR specific definitions
 */
#define RCC_AHB1ENR_ETHMAC_EN		BIT(25)
#define RCC_AHB1ENR_ETHMAC_TX_EN	BIT(26)
#define RCC_AHB1ENR_ETHMAC_RX_EN	BIT(27)

/*
 * RCC APB1ENR specific definitions
 */
#define RCC_APB1ENR_TIM2EN		BIT(0)
#define RCC_APB1ENR_PWREN		BIT(28)

/*
 * RCC APB2ENR specific definitions
 */
#define RCC_APB2ENR_SYSCFGEN		BIT(14)
#define RCC_APB2ENR_SAI1EN		BIT(22)

enum periph_clock {
	TIMER2_CLOCK_CFG,
};

static const struct stm32_clk_info stm32f4_clk_info = {
	/* 180 MHz */
	.sys_pll_psc = {
		.pll_n = 360,
		.pll_p = 2,
		.pll_q = 8,
		.ahb_psc = AHB_PSC_1,
		.apb1_psc = APB_PSC_4,
		.apb2_psc = APB_PSC_2,
	},
	.has_overdrive = false,
	.v2 = false,
};

static const struct stm32_clk_info stm32f7_clk_info = {
	/* 200 MHz */
	.sys_pll_psc = {
		.pll_n = 400,
		.pll_p = 2,
		.pll_q = 8,
		.ahb_psc = AHB_PSC_1,
		.apb1_psc = APB_PSC_4,
		.apb2_psc = APB_PSC_2,
	},
	.has_overdrive = true,
	.v2 = true,
};

struct stm32_clk {
	struct stm32_rcc_regs *base;
	struct stm32_pwr_regs *pwr_regs;
	struct stm32_clk_info info;
	unsigned long hse_rate;
};

static int configure_clocks(struct udevice *dev)
{
	struct stm32_clk *priv = dev_get_priv(dev);
	struct stm32_rcc_regs *regs = priv->base;
	struct stm32_pwr_regs *pwr = priv->pwr_regs;
	struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
	u32 pllsaicfgr = 0;

	/* Reset RCC configuration */
	setbits_le32(&regs->cr, RCC_CR_HSION);
	writel(0, &regs->cfgr); /* Reset CFGR */
	clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
		| RCC_CR_PLLON | RCC_CR_PLLSAION));
	writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
	clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
	writel(0, &regs->cir); /* Disable all interrupts */

	/* Configure for HSE+PLL operation */
	setbits_le32(&regs->cr, RCC_CR_HSEON);
	while (!(readl(&regs->cr) & RCC_CR_HSERDY))
		;

	setbits_le32(&regs->cfgr, ((
		sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
		| (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
		| (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));

	/* Configure the main PLL */
	setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
			sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
			sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
			((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
			sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);

	/* Configure the SAI PLL to get a 48 MHz source */
	pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
		     RCC_PLLSAICFGR_PLLSAIP_4;
	pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
	writel(pllsaicfgr, &regs->pllsaicfgr);

	/* Enable the main PLL */
	setbits_le32(&regs->cr, RCC_CR_PLLON);
	while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
		;

	if (priv->info.v2) { /*stm32f7 case */
		/* select PLLSAI as 48MHz clock source */
		setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);

		/* select 48MHz as SDMMC1 clock source */
		clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);

		/* select 48MHz as SDMMC2 clock source */
		clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
	} else  { /* stm32f4 case */
		/* select PLLSAI as 48MHz clock source */
		setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);

		/* select 48MHz as SDMMC1 clock source */
		clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
	}

	/* Enable the SAI PLL */
	setbits_le32(&regs->cr, RCC_CR_PLLSAION);
	while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
		;

	setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);

	if (priv->info.has_overdrive) {
		/*
		 * Enable high performance mode
		 * System frequency up to 200 MHz
		 */
		setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
		/* Infinite wait! */
		while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
			;
		/* Enable the Over-drive switch */
		setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
		/* Infinite wait! */
		while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
			;
	}

	stm32_flash_latency_cfg(5);
	clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
	setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);

	while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
			RCC_CFGR_SWS_PLL)
		;
	/* gate the SAI clock, needed for MMC 1&2 clocks */
	setbits_le32(&regs->apb2enr, RCC_APB2ENR_SAI1EN);

#ifdef CONFIG_ETH_DESIGNWARE
	/* gate the SYSCFG clock, needed to set RMII ethernet interface */
	setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
#endif

	return 0;
}

static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
					     u32 sysclk)
{
	struct stm32_rcc_regs *regs = priv->base;
	u16 pllq, pllm, pllsain, pllsaip;
	bool pllsai;

	pllq = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
	       >> RCC_PLLCFGR_PLLQ_SHIFT;

	if (priv->info.v2) /*stm32f7 case */
		pllsai = readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
	else
		pllsai = readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;

	if (pllsai) {
		/* PLL48CLK is selected from PLLSAI, get PLLSAI value */
		pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
		pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
			>> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
		pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
			>> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
		return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
	}
	/* PLL48CLK is selected from PLLQ */
	return sysclk / pllq;
}

static unsigned long stm32_clk_get_rate(struct clk *clk)
{
	struct stm32_clk *priv = dev_get_priv(clk->dev);
	struct stm32_rcc_regs *regs = priv->base;
	u32 sysclk = 0;
	u32 shift = 0;
	u16 pllm, plln, pllp;
	/* Prescaler table lookups for clock computation */
	u8 ahb_psc_table[16] = {
		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
	};
	u8 apb_psc_table[8] = {
		0, 0, 0, 0, 1, 2, 3, 4
	};

	if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
			RCC_CFGR_SWS_PLL) {
		pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
		plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
			>> RCC_PLLCFGR_PLLN_SHIFT);
		pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
			>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
		sysclk = ((priv->hse_rate / pllm) * plln) / pllp;
	} else {
		return -EINVAL;
	}

	switch (clk->id) {
	/*
	 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
	 * AHB1, AHB2 and AHB3
	 */
	case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
		shift = ahb_psc_table[(
			(readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
			>> RCC_CFGR_HPRE_SHIFT)];
		return sysclk >>= shift;
	/* APB1 CLOCK */
	case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
		shift = apb_psc_table[(
			(readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
			>> RCC_CFGR_PPRE1_SHIFT)];
		return sysclk >>= shift;
	/* APB2 CLOCK */
	case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
		/*
		 * particular case for SDMMC1 and SDMMC2 :
		 * 48Mhz source clock can be from main PLL or from
		 * SAI PLL
		 */
		switch (clk->id) {
		case STM32F7_APB2_CLOCK(SDMMC1):
			if (readl(&regs->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
				/* System clock is selected as SDMMC1 clock */
				return sysclk;
			else
				return stm32_clk_pll48clk_rate(priv, sysclk);
			break;
		case STM32F7_APB2_CLOCK(SDMMC2):
			if (readl(&regs->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
				/* System clock is selected as SDMMC2 clock */
				return sysclk;
			else
				return stm32_clk_pll48clk_rate(priv, sysclk);
			break;
		}

		shift = apb_psc_table[(
			(readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
			>> RCC_CFGR_PPRE2_SHIFT)];
		return sysclk >>= shift;
	default:
		pr_err("clock index %ld out of range\n", clk->id);
		return -EINVAL;
	}
}

static ulong stm32_set_rate(struct clk *clk, ulong rate)
{
	return 0;
}

static int stm32_clk_enable(struct clk *clk)
{
	struct stm32_clk *priv = dev_get_priv(clk->dev);
	struct stm32_rcc_regs *regs = priv->base;
	u32 offset = clk->id / 32;
	u32 bit_index = clk->id % 32;

	debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
	      __func__, clk->id, offset, bit_index);
	setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));

	return 0;
}

void clock_setup(int peripheral)
{
	switch (peripheral) {
	case TIMER2_CLOCK_CFG:
		setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
		break;
	default:
		break;
	}
}

static int stm32_clk_probe(struct udevice *dev)
{
	struct ofnode_phandle_args args;
	struct udevice *fixed_clock_dev = NULL;
	struct clk clk;
	int err;

	debug("%s\n", __func__);

	struct stm32_clk *priv = dev_get_priv(dev);
	fdt_addr_t addr;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->base = (struct stm32_rcc_regs *)addr;

	switch (dev_get_driver_data(dev)) {
	case STM32F4:
		memcpy(&priv->info, &stm32f4_clk_info,
		       sizeof(struct stm32_clk_info));
		break;
	case STM32F7:
		memcpy(&priv->info, &stm32f7_clk_info,
		       sizeof(struct stm32_clk_info));
		break;
	default:
		return -EINVAL;
	}

	/* retrieve HSE frequency (external oscillator) */
	err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
					&fixed_clock_dev);

	if (err) {
		pr_err("Can't find fixed clock (%d)", err);
		return err;
	}

	err = clk_request(fixed_clock_dev, &clk);
	if (err) {
		pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
		       err);
		return err;
	}

	/*
	 * set pllm factor accordingly to the external oscillator
	 * frequency (HSE). For STM32F4 and STM32F7, we want VCO
	 * freq at 1MHz
	 * if input PLL frequency is 25Mhz, divide it by 25
	 */
	clk.id = 0;
	priv->hse_rate = clk_get_rate(&clk);

	if (priv->hse_rate < 1000000) {
		pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
		       priv->hse_rate);
		return -EINVAL;
	}

	priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;

	if (priv->info.has_overdrive) {
		err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
						 &args);
		if (err) {
			debug("%s: can't find syscon device (%d)\n", __func__,
			      err);
			return err;
		}

		priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
	}

	configure_clocks(dev);

	return 0;
}

static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
{
	debug("%s(clk=%p)\n", __func__, clk);

	if (args->args_count != 2) {
		debug("Invaild args_count: %d\n", args->args_count);
		return -EINVAL;
	}

	if (args->args_count)
		clk->id = args->args[1];
	else
		clk->id = 0;

	return 0;
}

static struct clk_ops stm32_clk_ops = {
	.of_xlate	= stm32_clk_of_xlate,
	.enable		= stm32_clk_enable,
	.get_rate	= stm32_clk_get_rate,
	.set_rate	= stm32_set_rate,
};

U_BOOT_DRIVER(stm32fx_clk) = {
	.name			= "stm32fx_rcc_clock",
	.id			= UCLASS_CLK,
	.ops			= &stm32_clk_ops,
	.probe			= stm32_clk_probe,
	.priv_auto_alloc_size	= sizeof(struct stm32_clk),
	.flags			= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
e66c49fa	1	/*
3bc599c9 PC	2	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3bc599c9 PC	3	* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
e66c49fa VM	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
3bc599c9	7
e66c49fa	8	#include <common.h>
712f99a5 VM	9	#include <clk-uclass.h>
712f99a5 VM	10	#include <dm.h>
928954fe	11	#include <stm32_rcc.h>
d0a768b1	12
e66c49fa	13	#include <asm/io.h>
e66c49fa	14	#include <asm/arch/stm32.h>
d0a768b1	15	#include <asm/arch/stm32_pwr.h>
e66c49fa	16
288f17e6 PC	17	#include <dt-bindings/mfd/stm32f7-rcc.h>
288f17e6 PC	18
bad5188b MK	19	#define RCC_CR_HSION BIT(0)
	20	#define RCC_CR_HSEON BIT(16)
	21	#define RCC_CR_HSERDY BIT(17)
	22	#define RCC_CR_HSEBYP BIT(18)
	23	#define RCC_CR_CSSON BIT(19)
	24	#define RCC_CR_PLLON BIT(24)
	25	#define RCC_CR_PLLRDY BIT(25)
4e97e257 PC	26	#define RCC_CR_PLLSAION BIT(28)
4e97e257 PC	27	#define RCC_CR_PLLSAIRDY BIT(29)
ba0a3c16	28
bad5188b MK	29	#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
	30	#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
	31	#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
	32	#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
	33	#define RCC_PLLCFGR_PLLSRC BIT(22)
	34	#define RCC_PLLCFGR_PLLM_SHIFT 0
	35	#define RCC_PLLCFGR_PLLN_SHIFT 6
	36	#define RCC_PLLCFGR_PLLP_SHIFT 16
	37	#define RCC_PLLCFGR_PLLQ_SHIFT 24
ba0a3c16	38
bad5188b MK	39	#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
	40	#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
	41	#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
	42	#define RCC_CFGR_SW0 BIT(0)
	43	#define RCC_CFGR_SW1 BIT(1)
	44	#define RCC_CFGR_SW_MASK GENMASK(1, 0)
	45	#define RCC_CFGR_SW_HSI 0
	46	#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
	47	#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
	48	#define RCC_CFGR_SWS0 BIT(2)
	49	#define RCC_CFGR_SWS1 BIT(3)
	50	#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
	51	#define RCC_CFGR_SWS_HSI 0
	52	#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
	53	#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
	54	#define RCC_CFGR_HPRE_SHIFT 4
	55	#define RCC_CFGR_PPRE1_SHIFT 10
	56	#define RCC_CFGR_PPRE2_SHIFT 13
ba0a3c16	57
4e97e257 PC	58	#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6)
	59	#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16)
	60	#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
	61	#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
990dba64	62	#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
4e97e257 PC	63	#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
	64	#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
	65
	66	#define RCC_DCKCFGRX_CK48MSEL BIT(27)
	67	#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
	68	#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
	69
c88c6a9e PC	70	/*
	71	* RCC AHB1ENR specific definitions
	72	*/
	73	#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
	74	#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
	75	#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
	76
	77	/*
	78	* RCC APB1ENR specific definitions
	79	*/
	80	#define RCC_APB1ENR_TIM2EN BIT(0)
	81	#define RCC_APB1ENR_PWREN BIT(28)
	82
	83	/*
	84	* RCC APB2ENR specific definitions
	85	*/
	86	#define RCC_APB2ENR_SYSCFGEN BIT(14)
20fe38e7	87	#define RCC_APB2ENR_SAI1EN BIT(22)
c88c6a9e	88
4a56fd48	89	enum periph_clock {
4a56fd48	90	TIMER2_CLOCK_CFG,
4a56fd48 PC	91	};
4a56fd48 PC	92
cb97ff9d	93	static const struct stm32_clk_info stm32f4_clk_info = {
f9333c93 PC	94	/* 180 MHz */
f9333c93 PC	95	.sys_pll_psc = {
f9333c93 PC	96	.pll_n = 360,
	97	.pll_p = 2,
	98	.pll_q = 8,
	99	.ahb_psc = AHB_PSC_1,
	100	.apb1_psc = APB_PSC_4,
	101	.apb2_psc = APB_PSC_2,
	102	},
	103	.has_overdrive = false,
4e97e257	104	.v2 = false,
f9333c93 PC	105	};
f9333c93 PC	106
cb97ff9d	107	static const struct stm32_clk_info stm32f7_clk_info = {
f9333c93 PC	108	/* 200 MHz */
f9333c93 PC	109	.sys_pll_psc = {
f9333c93 PC	110	.pll_n = 400,
	111	.pll_p = 2,
	112	.pll_q = 8,
	113	.ahb_psc = AHB_PSC_1,
	114	.apb1_psc = APB_PSC_4,
	115	.apb2_psc = APB_PSC_2,
	116	},
	117	.has_overdrive = true,
4e97e257	118	.v2 = true,
f9333c93 PC	119	};
f9333c93 PC	120
199a2178 PC	121	struct stm32_clk {
199a2178 PC	122	struct stm32_rcc_regs *base;
d0a768b1	123	struct stm32_pwr_regs *pwr_regs;
cb97ff9d PC	124	struct stm32_clk_info info;
cb97ff9d PC	125	unsigned long hse_rate;
199a2178 PC	126	};
199a2178 PC	127
199a2178	128	static int configure_clocks(struct udevice *dev)
ba0a3c16	129	{
199a2178 PC	130	struct stm32_clk *priv = dev_get_priv(dev);
199a2178 PC	131	struct stm32_rcc_regs *regs = priv->base;
d0a768b1	132	struct stm32_pwr_regs *pwr = priv->pwr_regs;
cb97ff9d	133	struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
4e97e257	134	u32 pllsaicfgr = 0;
199a2178	135
ba0a3c16	136	/* Reset RCC configuration */
199a2178 PC	137	setbits_le32(&regs->cr, RCC_CR_HSION);
	138	writel(0, &regs->cfgr); /* Reset CFGR */
	139	clrbits_le32(&regs->cr, (RCC_CR_HSEON \| RCC_CR_CSSON
4e97e257	140	\| RCC_CR_PLLON \| RCC_CR_PLLSAION));
199a2178 PC	141	writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
	142	clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
	143	writel(0, &regs->cir); /* Disable all interrupts */
ba0a3c16 TN	144
ba0a3c16 TN	145	/* Configure for HSE+PLL operation */
199a2178 PC	146	setbits_le32(&regs->cr, RCC_CR_HSEON);
199a2178 PC	147	while (!(readl(&regs->cr) & RCC_CR_HSERDY))
ba0a3c16 TN	148	;
ba0a3c16 TN	149
199a2178	150	setbits_le32(&regs->cfgr, ((
cb97ff9d PC	151	sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
	152	\| (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
	153	\| (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
ba0a3c16 TN	154
ba0a3c16 TN	155	/* Configure the main PLL */
1543bf79 PC	156	setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
1543bf79 PC	157	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
cb97ff9d	158	sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
1543bf79	159	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
cb97ff9d	160	sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
1543bf79	161	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
cb97ff9d	162	((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
1543bf79	163	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
cb97ff9d	164	sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
ba0a3c16	165
4e97e257 PC	166	/* Configure the SAI PLL to get a 48 MHz source */
	167	pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIQ_4 \|
	168	RCC_PLLSAICFGR_PLLSAIP_4;
	169	pllsaicfgr \|= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
	170	writel(pllsaicfgr, &regs->pllsaicfgr);
	171
ba0a3c16	172	/* Enable the main PLL */
199a2178 PC	173	setbits_le32(&regs->cr, RCC_CR_PLLON);
199a2178 PC	174	while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
ba0a3c16 TN	175	;
ba0a3c16 TN	176
cb97ff9d	177	if (priv->info.v2) { /stm32f7 case /
4e97e257 PC	178	/* select PLLSAI as 48MHz clock source */
	179	setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
	180
	181	/* select 48MHz as SDMMC1 clock source */
	182	clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
	183
	184	/* select 48MHz as SDMMC2 clock source */
	185	clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
	186	} else { /* stm32f4 case */
	187	/* select PLLSAI as 48MHz clock source */
	188	setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
	189
	190	/* select 48MHz as SDMMC1 clock source */
	191	clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
	192	}
	193
	194	/* Enable the SAI PLL */
	195	setbits_le32(&regs->cr, RCC_CR_PLLSAION);
	196	while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
	197	;
	198
199a2178	199	setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
f9333c93	200
cb97ff9d	201	if (priv->info.has_overdrive) {
f9333c93 PC	202	/*
	203	* Enable high performance mode
	204	* System frequency up to 200 MHz
	205	*/
	206	setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
	207	/* Infinite wait! */
	208	while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
	209	;
	210	/* Enable the Over-drive switch */
	211	setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
	212	/* Infinite wait! */
	213	while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
	214	;
	215	}
ba0a3c16 TN	216
ba0a3c16 TN	217	stm32_flash_latency_cfg(5);
199a2178 PC	218	clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 \| RCC_CFGR_SW1));
199a2178 PC	219	setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
ba0a3c16	220
199a2178	221	while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
ba0a3c16 TN	222	RCC_CFGR_SWS_PLL)
ba0a3c16 TN	223	;
4e97e257 PC	224	/* gate the SAI clock, needed for MMC 1&2 clocks */
4e97e257 PC	225	setbits_le32(&regs->apb2enr, RCC_APB2ENR_SAI1EN);
ba0a3c16	226
20fe38e7 PC	227	#ifdef CONFIG_ETH_DESIGNWARE
	228	/* gate the SYSCFG clock, needed to set RMII ethernet interface */
	229	setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
	230	#endif
	231
ba0a3c16 TN	232	return 0;
	233	}
	234
4e97e257 PC	235	static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
	236	u32 sysclk)
	237	{
	238	struct stm32_rcc_regs *regs = priv->base;
	239	u16 pllq, pllm, pllsain, pllsaip;
	240	bool pllsai;
	241
	242	pllq = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
	243	>> RCC_PLLCFGR_PLLQ_SHIFT;
	244
cb97ff9d	245	if (priv->info.v2) /stm32f7 case /
4e97e257 PC	246	pllsai = readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
	247	else
	248	pllsai = readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
	249
	250	if (pllsai) {
	251	/* PLL48CLK is selected from PLLSAI, get PLLSAI value */
	252	pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
	253	pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
	254	>> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
	255	pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
	256	>> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
cb97ff9d	257	return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
4e97e257 PC	258	}
	259	/* PLL48CLK is selected from PLLQ */
	260	return sysclk / pllq;
	261	}
	262
288f17e6 PC	263	static unsigned long stm32_clk_get_rate(struct clk *clk)
	264	{
	265	struct stm32_clk *priv = dev_get_priv(clk->dev);
	266	struct stm32_rcc_regs *regs = priv->base;
	267	u32 sysclk = 0;
	268	u32 shift = 0;
f264e235	269	u16 pllm, plln, pllp;
288f17e6 PC	270	/* Prescaler table lookups for clock computation */
	271	u8 ahb_psc_table[16] = {
	272	0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
	273	};
	274	u8 apb_psc_table[8] = {
	275	0, 0, 0, 0, 1, 2, 3, 4
	276	};
	277
	278	if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
	279	RCC_CFGR_SWS_PLL) {
288f17e6 PC	280	pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
	281	plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
	282	>> RCC_PLLCFGR_PLLN_SHIFT);
	283	pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
	284	>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
cb97ff9d	285	sysclk = ((priv->hse_rate / pllm) * plln) / pllp;
288f17e6 PC	286	} else {
	287	return -EINVAL;
	288	}
	289
	290	switch (clk->id) {
	291	/*
	292	* AHB CLOCK: 3 x 32 bits consecutive registers are used :
	293	* AHB1, AHB2 and AHB3
	294	*/
	295	case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
	296	shift = ahb_psc_table[(
	297	(readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
	298	>> RCC_CFGR_HPRE_SHIFT)];
	299	return sysclk >>= shift;
288f17e6 PC	300	/* APB1 CLOCK */
	301	case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
	302	shift = apb_psc_table[(
	303	(readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
	304	>> RCC_CFGR_PPRE1_SHIFT)];
	305	return sysclk >>= shift;
288f17e6 PC	306	/* APB2 CLOCK */
288f17e6 PC	307	case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
4e97e257 PC	308	/*
	309	* particular case for SDMMC1 and SDMMC2 :
	310	* 48Mhz source clock can be from main PLL or from
	311	* SAI PLL
	312	*/
	313	switch (clk->id) {
	314	case STM32F7_APB2_CLOCK(SDMMC1):
	315	if (readl(&regs->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
	316	/* System clock is selected as SDMMC1 clock */
	317	return sysclk;
	318	else
	319	return stm32_clk_pll48clk_rate(priv, sysclk);
	320	break;
	321	case STM32F7_APB2_CLOCK(SDMMC2):
	322	if (readl(&regs->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
	323	/* System clock is selected as SDMMC2 clock */
	324	return sysclk;
	325	else
	326	return stm32_clk_pll48clk_rate(priv, sysclk);
	327	break;
	328	}
	329
288f17e6 PC	330	shift = apb_psc_table[(
	331	(readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
	332	>> RCC_CFGR_PPRE2_SHIFT)];
	333	return sysclk >>= shift;
288f17e6	334	default:
9b643e31	335	pr_err("clock index %ld out of range\n", clk->id);
288f17e6	336	return -EINVAL;
288f17e6 PC	337	}
	338	}
	339
05e23dd4 PC	340	static ulong stm32_set_rate(struct clk *clk, ulong rate)
	341	{
	342	return 0;
	343	}
	344
712f99a5 VM	345	static int stm32_clk_enable(struct clk *clk)
712f99a5 VM	346	{
199a2178 PC	347	struct stm32_clk *priv = dev_get_priv(clk->dev);
199a2178 PC	348	struct stm32_rcc_regs *regs = priv->base;
712f99a5 VM	349	u32 offset = clk->id / 32;
	350	u32 bit_index = clk->id % 32;
	351
	352	debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
	353	__func__, clk->id, offset, bit_index);
199a2178	354	setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
712f99a5 VM	355
	356	return 0;
	357	}
ba0a3c16	358
e66c49fa VM	359	void clock_setup(int peripheral)
	360	{
	361	switch (peripheral) {
081de09d MK	362	case TIMER2_CLOCK_CFG:
	363	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
	364	break;
e66c49fa VM	365	default:
	366	break;
	367	}
	368	}
712f99a5 VM	369
	370	static int stm32_clk_probe(struct udevice *dev)
	371	{
d0a768b1	372	struct ofnode_phandle_args args;
cb97ff9d PC	373	struct udevice *fixed_clock_dev = NULL;
cb97ff9d PC	374	struct clk clk;
d0a768b1 PC	375	int err;
d0a768b1 PC	376
f264e235	377	debug("%s\n", __func__);
199a2178 PC	378
	379	struct stm32_clk *priv = dev_get_priv(dev);
	380	fdt_addr_t addr;
	381
f9333c93	382	addr = dev_read_addr(dev);
199a2178 PC	383	if (addr == FDT_ADDR_T_NONE)
	384	return -EINVAL;
	385
	386	priv->base = (struct stm32_rcc_regs *)addr;
928954fe PC	387
	388	switch (dev_get_driver_data(dev)) {
	389	case STM32F4:
cb97ff9d PC	390	memcpy(&priv->info, &stm32f4_clk_info,
cb97ff9d PC	391	sizeof(struct stm32_clk_info));
928954fe PC	392	break;
928954fe PC	393	case STM32F7:
cb97ff9d PC	394	memcpy(&priv->info, &stm32f7_clk_info,
cb97ff9d PC	395	sizeof(struct stm32_clk_info));
928954fe PC	396	break;
	397	default:
	398	return -EINVAL;
	399	}
f9333c93	400
cb97ff9d PC	401	/* retrieve HSE frequency (external oscillator) */
	402	err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
	403	&fixed_clock_dev);
	404
	405	if (err) {
	406	pr_err("Can't find fixed clock (%d)", err);
	407	return err;
	408	}
	409
	410	err = clk_request(fixed_clock_dev, &clk);
	411	if (err) {
	412	pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
	413	err);
	414	return err;
	415	}
	416
	417	/*
	418	* set pllm factor accordingly to the external oscillator
	419	* frequency (HSE). For STM32F4 and STM32F7, we want VCO
	420	* freq at 1MHz
	421	* if input PLL frequency is 25Mhz, divide it by 25
	422	*/
	423	clk.id = 0;
	424	priv->hse_rate = clk_get_rate(&clk);
	425
	426	if (priv->hse_rate < 1000000) {
	427	pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
	428	priv->hse_rate);
	429	return -EINVAL;
	430	}
	431
	432	priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
	433
	434	if (priv->info.has_overdrive) {
f9333c93 PC	435	err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
	436	&args);
	437	if (err) {
	438	debug("%s: can't find syscon device (%d)\n", __func__,
	439	err);
	440	return err;
	441	}
	442
	443	priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
d0a768b1 PC	444	}
d0a768b1 PC	445
199a2178	446	configure_clocks(dev);
712f99a5 VM	447
	448	return 0;
	449	}
	450
a4e0ef50	451	static int stm32_clk_of_xlate(struct clk clk, struct ofnode_phandle_args args)
712f99a5 VM	452	{
	453	debug("%s(clk=%p)\n", __func__, clk);
	454
	455	if (args->args_count != 2) {
	456	debug("Invaild args_count: %d\n", args->args_count);
	457	return -EINVAL;
	458	}
	459
	460	if (args->args_count)
	461	clk->id = args->args[1];
	462	else
	463	clk->id = 0;
	464
	465	return 0;
	466	}
	467
	468	static struct clk_ops stm32_clk_ops = {
	469	.of_xlate = stm32_clk_of_xlate,
	470	.enable = stm32_clk_enable,
288f17e6	471	.get_rate = stm32_clk_get_rate,
05e23dd4	472	.set_rate = stm32_set_rate,
712f99a5 VM	473	};
712f99a5 VM	474
f264e235	475	U_BOOT_DRIVER(stm32fx_clk) = {
928954fe	476	.name = "stm32fx_rcc_clock",
0cc40dfc	477	.id = UCLASS_CLK,
0cc40dfc PC	478	.ops = &stm32_clk_ops,
	479	.probe = stm32_clk_probe,
	480	.priv_auto_alloc_size = sizeof(struct stm32_clk),
	481	.flags = DM_FLAG_PRE_RELOC,
712f99a5	482	};