drivers/clk/clk_stm32f.c

   1 /*
   2  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   3  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <stm32_rcc.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/arch/stm32.h>
  15 #include <asm/arch/stm32_pwr.h>
  16
  17 #include <dt-bindings/mfd/stm32f7-rcc.h>
  18
  19 #define RCC_CR_HSION                    BIT(0)
  20 #define RCC_CR_HSEON                    BIT(16)
  21 #define RCC_CR_HSERDY                   BIT(17)
  22 #define RCC_CR_HSEBYP                   BIT(18)
  23 #define RCC_CR_CSSON                    BIT(19)
  24 #define RCC_CR_PLLON                    BIT(24)
  25 #define RCC_CR_PLLRDY                   BIT(25)
  26 #define RCC_CR_PLLSAION                 BIT(28)
  27 #define RCC_CR_PLLSAIRDY                BIT(29)
  28
  29 #define RCC_PLLCFGR_PLLM_MASK           GENMASK(5, 0)
  30 #define RCC_PLLCFGR_PLLN_MASK           GENMASK(14, 6)
  31 #define RCC_PLLCFGR_PLLP_MASK           GENMASK(17, 16)
  32 #define RCC_PLLCFGR_PLLQ_MASK           GENMASK(27, 24)
  33 #define RCC_PLLCFGR_PLLSRC              BIT(22)
  34 #define RCC_PLLCFGR_PLLM_SHIFT          0
  35 #define RCC_PLLCFGR_PLLN_SHIFT          6
  36 #define RCC_PLLCFGR_PLLP_SHIFT          16
  37 #define RCC_PLLCFGR_PLLQ_SHIFT          24
  38
  39 #define RCC_CFGR_AHB_PSC_MASK           GENMASK(7, 4)
  40 #define RCC_CFGR_APB1_PSC_MASK          GENMASK(12, 10)
  41 #define RCC_CFGR_APB2_PSC_MASK          GENMASK(15, 13)
  42 #define RCC_CFGR_SW0                    BIT(0)
  43 #define RCC_CFGR_SW1                    BIT(1)
  44 #define RCC_CFGR_SW_MASK                GENMASK(1, 0)
  45 #define RCC_CFGR_SW_HSI                 0
  46 #define RCC_CFGR_SW_HSE                 RCC_CFGR_SW0
  47 #define RCC_CFGR_SW_PLL                 RCC_CFGR_SW1
  48 #define RCC_CFGR_SWS0                   BIT(2)
  49 #define RCC_CFGR_SWS1                   BIT(3)
  50 #define RCC_CFGR_SWS_MASK               GENMASK(3, 2)
  51 #define RCC_CFGR_SWS_HSI                0
  52 #define RCC_CFGR_SWS_HSE                RCC_CFGR_SWS0
  53 #define RCC_CFGR_SWS_PLL                RCC_CFGR_SWS1
  54 #define RCC_CFGR_HPRE_SHIFT             4
  55 #define RCC_CFGR_PPRE1_SHIFT            10
  56 #define RCC_CFGR_PPRE2_SHIFT            13
  57
  58 #define RCC_PLLCFGR_PLLSAIN_MASK        GENMASK(14, 6)
  59 #define RCC_PLLCFGR_PLLSAIP_MASK        GENMASK(17, 16)
  60 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT    6
  61 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT    16
  62 #define RCC_PLLSAICFGR_PLLSAIP_4        BIT(16)
  63 #define RCC_PLLSAICFGR_PLLSAIQ_4        BIT(26)
  64 #define RCC_PLLSAICFGR_PLLSAIR_2        BIT(29)
  65
  66 #define RCC_DCKCFGRX_CK48MSEL           BIT(27)
  67 #define RCC_DCKCFGRX_SDMMC1SEL          BIT(28)
  68 #define RCC_DCKCFGR2_SDMMC2SEL          BIT(29)
  69
  70 /*
  71  * RCC AHB1ENR specific definitions
  72  */
  73 #define RCC_AHB1ENR_ETHMAC_EN           BIT(25)
  74 #define RCC_AHB1ENR_ETHMAC_TX_EN        BIT(26)
  75 #define RCC_AHB1ENR_ETHMAC_RX_EN        BIT(27)
  76
  77 /*
  78  * RCC APB1ENR specific definitions
  79  */
  80 #define RCC_APB1ENR_TIM2EN              BIT(0)
  81 #define RCC_APB1ENR_PWREN               BIT(28)
  82
  83 /*
  84  * RCC APB2ENR specific definitions
  85  */
  86 #define RCC_APB2ENR_SYSCFGEN            BIT(14)
  87 #define RCC_APB2ENR_SAI1EN              BIT(22)
  88
  89 enum periph_clock {
  90         TIMER2_CLOCK_CFG,
  91 };
  92
  93 static const struct stm32_clk_info stm32f4_clk_info = {
  94         /* 180 MHz */
  95         .sys_pll_psc = {
  96                 .pll_n = 360,
  97                 .pll_p = 2,
  98                 .pll_q = 8,
  99                 .ahb_psc = AHB_PSC_1,
 100                 .apb1_psc = APB_PSC_4,
 101                 .apb2_psc = APB_PSC_2,
 102         },
 103         .has_overdrive = false,
 104         .v2 = false,
 105 };
 106
 107 static const struct stm32_clk_info stm32f7_clk_info = {
 108         /* 200 MHz */
 109         .sys_pll_psc = {
 110                 .pll_n = 400,
 111                 .pll_p = 2,
 112                 .pll_q = 8,
 113                 .ahb_psc = AHB_PSC_1,
 114                 .apb1_psc = APB_PSC_4,
 115                 .apb2_psc = APB_PSC_2,
 116         },
 117         .has_overdrive = true,
 118         .v2 = true,
 119 };
 120
 121 struct stm32_clk {
 122         struct stm32_rcc_regs *base;
 123         struct stm32_pwr_regs *pwr_regs;
 124         struct stm32_clk_info info;
 125         unsigned long hse_rate;
 126 };
 127
 128 static int configure_clocks(struct udevice *dev)
 129 {
 130         struct stm32_clk *priv = dev_get_priv(dev);
 131         struct stm32_rcc_regs *regs = priv->base;
 132         struct stm32_pwr_regs *pwr = priv->pwr_regs;
 133         struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
 134         u32 pllsaicfgr = 0;
 135
 136         /* Reset RCC configuration */
 137         setbits_le32(&regs->cr, RCC_CR_HSION);
 138         writel(0, &regs->cfgr); /* Reset CFGR */
 139         clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
 140                 | RCC_CR_PLLON | RCC_CR_PLLSAION));
 141         writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
 142         clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
 143         writel(0, &regs->cir); /* Disable all interrupts */
 144
 145         /* Configure for HSE+PLL operation */
 146         setbits_le32(&regs->cr, RCC_CR_HSEON);
 147         while (!(readl(&regs->cr) & RCC_CR_HSERDY))
 148                 ;
 149
 150         setbits_le32(&regs->cfgr, ((
 151                 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
 152                 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
 153                 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 154
 155         /* Configure the main PLL */
 156         setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
 157         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
 158                         sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
 159         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
 160                         sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
 161         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
 162                         ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
 163         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
 164                         sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
 165
 166         /* Configure the SAI PLL to get a 48 MHz source */
 167         pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
 168                      RCC_PLLSAICFGR_PLLSAIP_4;
 169         pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
 170         writel(pllsaicfgr, &regs->pllsaicfgr);
 171
 172         /* Enable the main PLL */
 173         setbits_le32(&regs->cr, RCC_CR_PLLON);
 174         while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
 175                 ;
 176
 177         if (priv->info.v2) { /*stm32f7 case */
 178                 /* select PLLSAI as 48MHz clock source */
 179                 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
 180
 181                 /* select 48MHz as SDMMC1 clock source */
 182                 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
 183
 184                 /* select 48MHz as SDMMC2 clock source */
 185                 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
 186         } else  { /* stm32f4 case */
 187                 /* select PLLSAI as 48MHz clock source */
 188                 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
 189
 190                 /* select 48MHz as SDMMC1 clock source */
 191                 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
 192         }
 193
 194         /* Enable the SAI PLL */
 195         setbits_le32(&regs->cr, RCC_CR_PLLSAION);
 196         while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
 197                 ;
 198
 199         setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
 200
 201         if (priv->info.has_overdrive) {
 202                 /*
 203                  * Enable high performance mode
 204                  * System frequency up to 200 MHz
 205                  */
 206                 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
 207                 /* Infinite wait! */
 208                 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
 209                         ;
 210                 /* Enable the Over-drive switch */
 211                 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
 212                 /* Infinite wait! */
 213                 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
 214                         ;
 215         }
 216
 217         stm32_flash_latency_cfg(5);
 218         clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 219         setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
 220
 221         while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
 222                         RCC_CFGR_SWS_PLL)
 223                 ;
 224         /* gate the SAI clock, needed for MMC 1&2 clocks */
 225         setbits_le32(&regs->apb2enr, RCC_APB2ENR_SAI1EN);
 226
 227 #ifdef CONFIG_ETH_DESIGNWARE
 228         /* gate the SYSCFG clock, needed to set RMII ethernet interface */
 229         setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
 230 #endif
 231
 232         return 0;
 233 }
 234
 235 static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
 236                                              u32 sysclk)
 237 {
 238         struct stm32_rcc_regs *regs = priv->base;
 239         u16 pllq, pllm, pllsain, pllsaip;
 240         bool pllsai;
 241
 242         pllq = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
 243                >> RCC_PLLCFGR_PLLQ_SHIFT;
 244
 245         if (priv->info.v2) /*stm32f7 case */
 246                 pllsai = readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
 247         else
 248                 pllsai = readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
 249
 250         if (pllsai) {
 251                 /* PLL48CLK is selected from PLLSAI, get PLLSAI value */
 252                 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 253                 pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
 254                         >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
 255                 pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
 256                         >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
 257                 return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
 258         }
 259         /* PLL48CLK is selected from PLLQ */
 260         return sysclk / pllq;
 261 }
 262
 263 static unsigned long stm32_clk_get_rate(struct clk *clk)
 264 {
 265         struct stm32_clk *priv = dev_get_priv(clk->dev);
 266         struct stm32_rcc_regs *regs = priv->base;
 267         u32 sysclk = 0;
 268         u32 shift = 0;
 269         u16 pllm, plln, pllp;
 270         /* Prescaler table lookups for clock computation */
 271         u8 ahb_psc_table[16] = {
 272                 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 273         };
 274         u8 apb_psc_table[8] = {
 275                 0, 0, 0, 0, 1, 2, 3, 4
 276         };
 277
 278         if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
 279                         RCC_CFGR_SWS_PLL) {
 280                 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 281                 plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 282                         >> RCC_PLLCFGR_PLLN_SHIFT);
 283                 pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 284                         >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 285                 sysclk = ((priv->hse_rate / pllm) * plln) / pllp;
 286         } else {
 287                 return -EINVAL;
 288         }
 289
 290         switch (clk->id) {
 291         /*
 292          * AHB CLOCK: 3 x 32 bits consecutive registers are used :
 293          * AHB1, AHB2 and AHB3
 294          */
 295         case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
 296                 shift = ahb_psc_table[(
 297                         (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 298                         >> RCC_CFGR_HPRE_SHIFT)];
 299                 return sysclk >>= shift;
 300         /* APB1 CLOCK */
 301         case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
 302                 shift = apb_psc_table[(
 303                         (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 304                         >> RCC_CFGR_PPRE1_SHIFT)];
 305                 return sysclk >>= shift;
 306         /* APB2 CLOCK */
 307         case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
 308                 /*
 309                  * particular case for SDMMC1 and SDMMC2 :
 310                  * 48Mhz source clock can be from main PLL or from
 311                  * SAI PLL
 312                  */
 313                 switch (clk->id) {
 314                 case STM32F7_APB2_CLOCK(SDMMC1):
 315                         if (readl(&regs->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
 316                                 /* System clock is selected as SDMMC1 clock */
 317                                 return sysclk;
 318                         else
 319                                 return stm32_clk_pll48clk_rate(priv, sysclk);
 320                         break;
 321                 case STM32F7_APB2_CLOCK(SDMMC2):
 322                         if (readl(&regs->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
 323                                 /* System clock is selected as SDMMC2 clock */
 324                                 return sysclk;
 325                         else
 326                                 return stm32_clk_pll48clk_rate(priv, sysclk);
 327                         break;
 328                 }
 329
 330                 shift = apb_psc_table[(
 331                         (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 332                         >> RCC_CFGR_PPRE2_SHIFT)];
 333                 return sysclk >>= shift;
 334         default:
 335                 pr_err("clock index %ld out of range\n", clk->id);
 336                 return -EINVAL;
 337         }
 338 }
 339
 340 static ulong stm32_set_rate(struct clk *clk, ulong rate)
 341 {
 342         return 0;
 343 }
 344
 345 static int stm32_clk_enable(struct clk *clk)
 346 {
 347         struct stm32_clk *priv = dev_get_priv(clk->dev);
 348         struct stm32_rcc_regs *regs = priv->base;
 349         u32 offset = clk->id / 32;
 350         u32 bit_index = clk->id % 32;
 351
 352         debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
 353               __func__, clk->id, offset, bit_index);
 354         setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
 355
 356         return 0;
 357 }
 358
 359 void clock_setup(int peripheral)
 360 {
 361         switch (peripheral) {
 362         case TIMER2_CLOCK_CFG:
 363                 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
 364                 break;
 365         default:
 366                 break;
 367         }
 368 }
 369
 370 static int stm32_clk_probe(struct udevice *dev)
 371 {
 372         struct ofnode_phandle_args args;
 373         struct udevice *fixed_clock_dev = NULL;
 374         struct clk clk;
 375         int err;
 376
 377         debug("%s\n", __func__);
 378
 379         struct stm32_clk *priv = dev_get_priv(dev);
 380         fdt_addr_t addr;
 381
 382         addr = dev_read_addr(dev);
 383         if (addr == FDT_ADDR_T_NONE)
 384                 return -EINVAL;
 385
 386         priv->base = (struct stm32_rcc_regs *)addr;
 387
 388         switch (dev_get_driver_data(dev)) {
 389         case STM32F4:
 390                 memcpy(&priv->info, &stm32f4_clk_info,
 391                        sizeof(struct stm32_clk_info));
 392                 break;
 393         case STM32F7:
 394                 memcpy(&priv->info, &stm32f7_clk_info,
 395                        sizeof(struct stm32_clk_info));
 396                 break;
 397         default:
 398                 return -EINVAL;
 399         }
 400
 401         /* retrieve HSE frequency (external oscillator) */
 402         err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
 403                                         &fixed_clock_dev);
 404
 405         if (err) {
 406                 pr_err("Can't find fixed clock (%d)", err);
 407                 return err;
 408         }
 409
 410         err = clk_request(fixed_clock_dev, &clk);
 411         if (err) {
 412                 pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
 413                        err);
 414                 return err;
 415         }
 416
 417         /*
 418          * set pllm factor accordingly to the external oscillator
 419          * frequency (HSE). For STM32F4 and STM32F7, we want VCO
 420          * freq at 1MHz
 421          * if input PLL frequency is 25Mhz, divide it by 25
 422          */
 423         clk.id = 0;
 424         priv->hse_rate = clk_get_rate(&clk);
 425
 426         if (priv->hse_rate < 1000000) {
 427                 pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
 428                        priv->hse_rate);
 429                 return -EINVAL;
 430         }
 431
 432         priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
 433
 434         if (priv->info.has_overdrive) {
 435                 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
 436                                                  &args);
 437                 if (err) {
 438                         debug("%s: can't find syscon device (%d)\n", __func__,
 439                               err);
 440                         return err;
 441                 }
 442
 443                 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
 444         }
 445
 446         configure_clocks(dev);
 447
 448         return 0;
 449 }
 450
 451 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 452 {
 453         debug("%s(clk=%p)\n", __func__, clk);
 454
 455         if (args->args_count != 2) {
 456                 debug("Invaild args_count: %d\n", args->args_count);
 457                 return -EINVAL;
 458         }
 459
 460         if (args->args_count)
 461                 clk->id = args->args[1];
 462         else
 463                 clk->id = 0;
 464
 465         return 0;
 466 }
 467
 468 static struct clk_ops stm32_clk_ops = {
 469         .of_xlate       = stm32_clk_of_xlate,
 470         .enable         = stm32_clk_enable,
 471         .get_rate       = stm32_clk_get_rate,
 472         .set_rate       = stm32_set_rate,
 473 };
 474
 475 U_BOOT_DRIVER(stm32fx_clk) = {
 476         .name                   = "stm32fx_rcc_clock",
 477         .id                     = UCLASS_CLK,
 478         .ops                    = &stm32_clk_ops,
 479         .probe                  = stm32_clk_probe,
 480         .priv_auto_alloc_size   = sizeof(struct stm32_clk),
 481         .flags                  = DM_FLAG_PRE_RELOC,
 482 };