[people/ms/u-boot.git] / drivers / crypto / fsl / jr.c

/*
 * Copyright 2008-2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Based on CAAM driver in drivers/crypto/caam in Linux
 */

#include <common.h>
#include <malloc.h>
#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
#ifdef CONFIG_FSL_CORENET
#include <asm/fsl_pamu.h>
#endif

#define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))

uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
	0,
#if defined(CONFIG_ARCH_C29X)
	CONFIG_SYS_FSL_SEC_IDX_OFFSET,
	2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
#endif
};

#define SEC_ADDR(idx)	\
	((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))

#define SEC_JR0_ADDR(idx)	\
	(SEC_ADDR(idx) +	\
	 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))

struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];

static inline void start_jr0(uint8_t sec_idx)
{
	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
	u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
	u32 scfgr = sec_in32(&sec->scfgr);

	if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
		/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
		 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
		 */
		if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
		    (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
					(scfgr & SEC_SCFGR_VIRT_EN)))
			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
	} else {
		/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
		if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
	}
}

static inline void jr_reset_liodn(uint8_t sec_idx)
{
	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
	sec_out32(&sec->jrliodnr[0].ls, 0);
}

static inline void jr_disable_irq(uint8_t sec_idx)
{
	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
	uint32_t jrcfg = sec_in32(&regs->jrcfg1);

	jrcfg = jrcfg | JR_INTMASK;

	sec_out32(&regs->jrcfg1, jrcfg);
}

static void jr_initregs(uint8_t sec_idx)
{
	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
	struct jobring *jr = &jr0[sec_idx];
	phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
	phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);

#ifdef CONFIG_PHYS_64BIT
	sec_out32(&regs->irba_h, ip_base >> 32);
#else
	sec_out32(&regs->irba_h, 0x0);
#endif
	sec_out32(&regs->irba_l, (uint32_t)ip_base);
#ifdef CONFIG_PHYS_64BIT
	sec_out32(&regs->orba_h, op_base >> 32);
#else
	sec_out32(&regs->orba_h, 0x0);
#endif
	sec_out32(&regs->orba_l, (uint32_t)op_base);
	sec_out32(&regs->ors, JR_SIZE);
	sec_out32(&regs->irs, JR_SIZE);

	if (!jr->irq)
		jr_disable_irq(sec_idx);
}

static int jr_init(uint8_t sec_idx)
{
	struct jobring *jr = &jr0[sec_idx];

	memset(jr, 0, sizeof(struct jobring));

	jr->jq_id = DEFAULT_JR_ID;
	jr->irq = DEFAULT_IRQ;

#ifdef CONFIG_FSL_CORENET
	jr->liodn = DEFAULT_JR_LIODN;
#endif
	jr->size = JR_SIZE;
	jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
				JR_SIZE * sizeof(dma_addr_t));
	if (!jr->input_ring)
		return -1;

	jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
			      ARCH_DMA_MINALIGN);
	jr->output_ring =
	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
	if (!jr->output_ring)
		return -1;

	memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
	memset(jr->output_ring, 0, jr->op_size);

	start_jr0(sec_idx);

	jr_initregs(sec_idx);

	return 0;
}

static int jr_sw_cleanup(uint8_t sec_idx)
{
	struct jobring *jr = &jr0[sec_idx];

	jr->head = 0;
	jr->tail = 0;
	jr->read_idx = 0;
	jr->write_idx = 0;
	memset(jr->info, 0, sizeof(jr->info));
	memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
	memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));

	return 0;
}

static int jr_hw_reset(uint8_t sec_idx)
{
	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
	uint32_t timeout = 100000;
	uint32_t jrint, jrcr;

	sec_out32(&regs->jrcr, JRCR_RESET);
	do {
		jrint = sec_in32(&regs->jrint);
	} while (((jrint & JRINT_ERR_HALT_MASK) ==
		  JRINT_ERR_HALT_INPROGRESS) && --timeout);

	jrint = sec_in32(&regs->jrint);
	if (((jrint & JRINT_ERR_HALT_MASK) !=
	     JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
		return -1;

	timeout = 100000;
	sec_out32(&regs->jrcr, JRCR_RESET);
	do {
		jrcr = sec_in32(&regs->jrcr);
	} while ((jrcr & JRCR_RESET) && --timeout);

	if (timeout == 0)
		return -1;

	return 0;
}

/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
	       void (*callback)(uint32_t status, void *arg),
	       void *arg, uint8_t sec_idx)
{
	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
	struct jobring *jr = &jr0[sec_idx];
	int head = jr->head;
	uint32_t desc_word;
	int length = desc_len(desc_addr);
	int i;
#ifdef CONFIG_PHYS_64BIT
	uint32_t *addr_hi, *addr_lo;
#endif

	/* The descriptor must be submitted to SEC block as per endianness
	 * of the SEC Block.
	 * So, if the endianness of Core and SEC block is different, each word
	 * of the descriptor will be byte-swapped.
	 */
	for (i = 0; i < length; i++) {
		desc_word = desc_addr[i];
		sec_out32((uint32_t *)&desc_addr[i], desc_word);
	}

	phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);

	jr->info[head].desc_phys_addr = desc_phys_addr;
	jr->info[head].callback = (void *)callback;
	jr->info[head].arg = arg;
	jr->info[head].op_done = 0;

	unsigned long start = (unsigned long)&jr->info[head] &
					~(ARCH_DMA_MINALIGN - 1);
	unsigned long end = ALIGN((unsigned long)&jr->info[head] +
				  sizeof(struct jr_info), ARCH_DMA_MINALIGN);
	flush_dcache_range(start, end);

#ifdef CONFIG_PHYS_64BIT
	/* Write the 64 bit Descriptor address on Input Ring.
	 * The 32 bit hign and low part of the address will
	 * depend on endianness of SEC block.
	 */
#ifdef CONFIG_SYS_FSL_SEC_LE
	addr_lo = (uint32_t *)(&jr->input_ring[head]);
	addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
#elif defined(CONFIG_SYS_FSL_SEC_BE)
	addr_hi = (uint32_t *)(&jr->input_ring[head]);
	addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */

	sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
	sec_out32(addr_lo, (uint32_t)(desc_phys_addr));

#else
	/* Write the 32 bit Descriptor address on Input Ring. */
	sec_out32(&jr->input_ring[head], desc_phys_addr);
#endif /* ifdef CONFIG_PHYS_64BIT */

	start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
	end = ALIGN((unsigned long)&jr->input_ring[head] +
		     sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
	flush_dcache_range(start, end);

	jr->head = (head + 1) & (jr->size - 1);

	/* Invalidate output ring */
	start = (unsigned long)jr->output_ring &
					~(ARCH_DMA_MINALIGN - 1);
	end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
		    ARCH_DMA_MINALIGN);
	invalidate_dcache_range(start, end);

	sec_out32(&regs->irja, 1);

	return 0;
}

static int jr_dequeue(int sec_idx)
{
	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
	struct jobring *jr = &jr0[sec_idx];
	int head = jr->head;
	int tail = jr->tail;
	int idx, i, found;
	void (*callback)(uint32_t status, void *arg);
	void *arg = NULL;
#ifdef CONFIG_PHYS_64BIT
	uint32_t *addr_hi, *addr_lo;
#else
	uint32_t *addr;
#endif

	while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
						 jr->size)) {

		found = 0;

		phys_addr_t op_desc;
	#ifdef CONFIG_PHYS_64BIT
		/* Read the 64 bit Descriptor address from Output Ring.
		 * The 32 bit hign and low part of the address will
		 * depend on endianness of SEC block.
		 */
	#ifdef CONFIG_SYS_FSL_SEC_LE
		addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
		addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
	#elif defined(CONFIG_SYS_FSL_SEC_BE)
		addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
		addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
	#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */

		op_desc = ((u64)sec_in32(addr_hi) << 32) |
			  ((u64)sec_in32(addr_lo));

	#else
		/* Read the 32 bit Descriptor address from Output Ring. */
		addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
		op_desc = sec_in32(addr);
	#endif /* ifdef CONFIG_PHYS_64BIT */

		uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);

		for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
			idx = (tail + i) & (jr->size - 1);
			if (op_desc == jr->info[idx].desc_phys_addr) {
				found = 1;
				break;
			}
		}

		/* Error condition if match not found */
		if (!found)
			return -1;

		jr->info[idx].op_done = 1;
		callback = (void *)jr->info[idx].callback;
		arg = jr->info[idx].arg;

		/* When the job on tail idx gets done, increment
		 * tail till the point where job completed out of oredr has
		 * been taken into account
		 */
		if (idx == tail)
			do {
				tail = (tail + 1) & (jr->size - 1);
			} while (jr->info[tail].op_done);

		jr->tail = tail;
		jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);

		sec_out32(&regs->orjr, 1);
		jr->info[idx].op_done = 0;

		callback(status, arg);
	}

	return 0;
}

static void desc_done(uint32_t status, void *arg)
{
	struct result *x = arg;
	x->status = status;
	caam_jr_strstatus(status);
	x->done = 1;
}

static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
{
	unsigned long long timeval = get_ticks();
	unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
	struct result op;
	int ret = 0;

	memset(&op, 0, sizeof(op));

	ret = jr_enqueue(desc, desc_done, &op, sec_idx);
	if (ret) {
		debug("Error in SEC enq\n");
		ret = JQ_ENQ_ERR;
		goto out;
	}

	timeval = get_ticks();
	timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
	while (op.done != 1) {
		ret = jr_dequeue(sec_idx);
		if (ret) {
			debug("Error in SEC deq\n");
			ret = JQ_DEQ_ERR;
			goto out;
		}

		if ((get_ticks() - timeval) > timeout) {
			debug("SEC Dequeue timed out\n");
			ret = JQ_DEQ_TO_ERR;
			goto out;
		}
	}

	if (op.status) {
		debug("Error %x\n", op.status);
		ret = op.status;
	}
out:
	return ret;
}

int run_descriptor_jr(uint32_t *desc)
{
	return run_descriptor_jr_idx(desc, 0);
}

static inline int jr_reset_sec(uint8_t sec_idx)
{
	if (jr_hw_reset(sec_idx) < 0)
		return -1;

	/* Clean up the jobring structure maintained by software */
	jr_sw_cleanup(sec_idx);

	return 0;
}

int jr_reset(void)
{
	return jr_reset_sec(0);
}

static inline int sec_reset_idx(uint8_t sec_idx)
{
	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
	uint32_t mcfgr = sec_in32(&sec->mcfgr);
	uint32_t timeout = 100000;

	mcfgr |= MCFGR_SWRST;
	sec_out32(&sec->mcfgr, mcfgr);

	mcfgr |= MCFGR_DMA_RST;
	sec_out32(&sec->mcfgr, mcfgr);
	do {
		mcfgr = sec_in32(&sec->mcfgr);
	} while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);

	if (timeout == 0)
		return -1;

	timeout = 100000;
	do {
		mcfgr = sec_in32(&sec->mcfgr);
	} while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);

	if (timeout == 0)
		return -1;

	return 0;
}

static int instantiate_rng(uint8_t sec_idx)
{
	struct result op;
	u32 *desc;
	u32 rdsta_val;
	int ret = 0;
	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
	struct rng4tst __iomem *rng =
			(struct rng4tst __iomem *)&sec->rng;

	memset(&op, 0, sizeof(struct result));

	desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
	if (!desc) {
		printf("cannot allocate RNG init descriptor memory\n");
		return -1;
	}

	inline_cnstr_jobdesc_rng_instantiation(desc);
	int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
	flush_dcache_range((unsigned long)desc,
			   (unsigned long)desc + size);

	ret = run_descriptor_jr_idx(desc, sec_idx);

	if (ret)
		printf("RNG: Instantiation failed with error %x\n", ret);

	rdsta_val = sec_in32(&rng->rdsta);
	if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
		return -1;

	return ret;
}

int sec_reset(void)
{
	return sec_reset_idx(0);
}

static u8 get_rng_vid(uint8_t sec_idx)
{
	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
	u32 cha_vid = sec_in32(&sec->chavid_ls);

	return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
}

/*
 * By default, the TRNG runs for 200 clocks per sample;
 * 1200 clocks per sample generates better entropy.
 */
static void kick_trng(int ent_delay, uint8_t sec_idx)
{
	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
	struct rng4tst __iomem *rng =
			(struct rng4tst __iomem *)&sec->rng;
	u32 val;

	/* put RNG4 into program mode */
	sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
	/* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
	 * length (in system clocks) of each Entropy sample taken
	 * */
	val = sec_in32(&rng->rtsdctl);
	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
	      (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
	sec_out32(&rng->rtsdctl, val);
	/* min. freq. count, equal to 1/4 of the entropy sample length */
	sec_out32(&rng->rtfreqmin, ent_delay >> 2);
	/* disable maximum frequency count */
	sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
	/*
	 * select raw sampling in both entropy shifter
	 * and statistical checker
	 */
	sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
	/* put RNG4 into run mode */
	sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
}

static int rng_init(uint8_t sec_idx)
{
	int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
	struct rng4tst __iomem *rng =
			(struct rng4tst __iomem *)&sec->rng;

	u32 rdsta = sec_in32(&rng->rdsta);

	/* Check if RNG state 0 handler is already instantiated */
	if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
		return 0;

	do {
		/*
		 * If either of the SH's were instantiated by somebody else
		 * then it is assumed that the entropy
		 * parameters are properly set and thus the function
		 * setting these (kick_trng(...)) is skipped.
		 * Also, if a handle was instantiated, do not change
		 * the TRNG parameters.
		 */
		kick_trng(ent_delay, sec_idx);
		ent_delay += 400;
		/*
		 * if instantiate_rng(...) fails, the loop will rerun
		 * and the kick_trng(...) function will modfiy the
		 * upper and lower limits of the entropy sampling
		 * interval, leading to a sucessful initialization of
		 * the RNG.
		 */
		ret = instantiate_rng(sec_idx);
	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
	if (ret) {
		printf("RNG: Failed to instantiate RNG\n");
		return ret;
	}

	 /* Enable RDB bit so that RNG works faster */
	sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);

	return ret;
}

int sec_init_idx(uint8_t sec_idx)
{
	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
	uint32_t mcr = sec_in32(&sec->mcfgr);
	int ret = 0;

#ifdef CONFIG_FSL_CORENET
	uint32_t liodnr;
	uint32_t liodn_ns;
	uint32_t liodn_s;
#endif

	if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
		printf("SEC initialization failed\n");
		return -1;
	}

	/*
	 * Modifying CAAM Read/Write Attributes
	 * For LS2080A
	 * For AXI Write - Cacheable, Write Back, Write allocate
	 * For AXI Read - Cacheable, Read allocate
	 * Only For LS2080a, to solve CAAM coherency issues
	 */
#ifdef CONFIG_LS2080A
	mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
	mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
#else
	mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
#endif

#ifdef CONFIG_PHYS_64BIT
	mcr |= (1 << MCFGR_PS_SHIFT);
#endif
	sec_out32(&sec->mcfgr, mcr);

#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SPL_BUILD
	/*
	 * For SPL Build, Set the Liodns in SEC JR0 for
	 * creating PAMU entries corresponding to these.
	 * For normal build, these are set in set_liodns().
	 */
	liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
	liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;

	liodnr = sec_in32(&sec->jrliodnr[0].ls) &
		 ~(JRNSLIODN_MASK | JRSLIODN_MASK);
	liodnr = liodnr |
		 (liodn_ns << JRNSLIODN_SHIFT) |
		 (liodn_s << JRSLIODN_SHIFT);
	sec_out32(&sec->jrliodnr[0].ls, liodnr);
#else
	liodnr = sec_in32(&sec->jrliodnr[0].ls);
	liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
	liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
#endif

	ret = jr_init(sec_idx);
	if (ret < 0) {
		printf("SEC initialization failed\n");
		return -1;
	}

#ifdef CONFIG_FSL_CORENET
	ret = sec_config_pamu_table(liodn_ns, liodn_s);
	if (ret < 0)
		return -1;

	pamu_enable();
#endif

	if (get_rng_vid(sec_idx) >= 4) {
		if (rng_init(sec_idx) < 0) {
			printf("SEC%u: RNG instantiation failed\n", sec_idx);
			return -1;
		}
		printf("SEC%u: RNG instantiated\n", sec_idx);
	}

	return ret;
}

int sec_init(void)
{
	return sec_init_idx(0);
}
Commit	Line	Data
b9eebfad RG	1	/*
	2	* Copyright 2008-2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*
	6	* Based on CAAM driver in drivers/crypto/caam in Linux
	7	*/
	8
	9	#include <common.h>
	10	#include <malloc.h>
	11	#include "fsl_sec.h"
	12	#include "jr.h"
c5de15cb	13	#include "jobdesc.h"
f59e69cb	14	#include "desc_constr.h"
f698e9f3 AB	15	#ifdef CONFIG_FSL_CORENET
	16	#include <asm/fsl_pamu.h>
	17	#endif
b9eebfad RG	18
	19	#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
	20	#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
	21
76394c9c AP	22	uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
76394c9c AP	23	0,
4fd64746	24	#if defined(CONFIG_ARCH_C29X)
76394c9c AP	25	CONFIG_SYS_FSL_SEC_IDX_OFFSET,
	26	2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
	27	#endif
	28	};
	29
	30	#define SEC_ADDR(idx) \
	31	((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
	32
	33	#define SEC_JR0_ADDR(idx) \
	34	(SEC_ADDR(idx) + \
	35	(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
	36
	37	struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
b9eebfad	38
76394c9c	39	static inline void start_jr0(uint8_t sec_idx)
b9eebfad	40	{
76394c9c	41	ccsr_sec_t sec = (void )SEC_ADDR(sec_idx);
b9eebfad RG	42	u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
	43	u32 scfgr = sec_in32(&sec->scfgr);
	44
	45	if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
	46	/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
	47	* VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
	48	*/
	49	if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) \|\|
	50	(!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
	51	(scfgr & SEC_SCFGR_VIRT_EN)))
	52	sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
	53	} else {
	54	/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
	55	if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
	56	sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
	57	}
	58	}
	59
76394c9c	60	static inline void jr_reset_liodn(uint8_t sec_idx)
b9eebfad	61	{
76394c9c	62	ccsr_sec_t sec = (void )SEC_ADDR(sec_idx);
b9eebfad RG	63	sec_out32(&sec->jrliodnr[0].ls, 0);
	64	}
	65
76394c9c	66	static inline void jr_disable_irq(uint8_t sec_idx)
b9eebfad	67	{
76394c9c	68	struct jr_regs regs = (struct jr_regs )SEC_JR0_ADDR(sec_idx);
b9eebfad RG	69	uint32_t jrcfg = sec_in32(&regs->jrcfg1);
	70
	71	jrcfg = jrcfg \| JR_INTMASK;
	72
	73	sec_out32(&regs->jrcfg1, jrcfg);
	74	}
	75
76394c9c	76	static void jr_initregs(uint8_t sec_idx)
b9eebfad	77	{
76394c9c AP	78	struct jr_regs regs = (struct jr_regs )SEC_JR0_ADDR(sec_idx);
	79	struct jobring *jr = &jr0[sec_idx];
	80	phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
	81	phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
b9eebfad RG	82
	83	#ifdef CONFIG_PHYS_64BIT
	84	sec_out32(&regs->irba_h, ip_base >> 32);
	85	#else
	86	sec_out32(&regs->irba_h, 0x0);
	87	#endif
	88	sec_out32(&regs->irba_l, (uint32_t)ip_base);
	89	#ifdef CONFIG_PHYS_64BIT
	90	sec_out32(&regs->orba_h, op_base >> 32);
	91	#else
	92	sec_out32(&regs->orba_h, 0x0);
	93	#endif
	94	sec_out32(&regs->orba_l, (uint32_t)op_base);
	95	sec_out32(&regs->ors, JR_SIZE);
	96	sec_out32(&regs->irs, JR_SIZE);
	97
76394c9c AP	98	if (!jr->irq)
76394c9c AP	99	jr_disable_irq(sec_idx);
b9eebfad RG	100	}
b9eebfad RG	101
76394c9c	102	static int jr_init(uint8_t sec_idx)
b9eebfad	103	{
76394c9c	104	struct jobring *jr = &jr0[sec_idx];
b9eebfad	105
76394c9c AP	106	memset(jr, 0, sizeof(struct jobring));
	107
	108	jr->jq_id = DEFAULT_JR_ID;
	109	jr->irq = DEFAULT_IRQ;
b9eebfad RG	110
b9eebfad RG	111	#ifdef CONFIG_FSL_CORENET
76394c9c	112	jr->liodn = DEFAULT_JR_LIODN;
b9eebfad	113	#endif
76394c9c AP	114	jr->size = JR_SIZE;
76394c9c AP	115	jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
0200020b	116	JR_SIZE * sizeof(dma_addr_t));
76394c9c	117	if (!jr->input_ring)
b9eebfad	118	return -1;
7f4736bd	119
76394c9c AP	120	jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
	121	ARCH_DMA_MINALIGN);
	122	jr->output_ring =
	123	(struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
	124	if (!jr->output_ring)
b9eebfad RG	125	return -1;
b9eebfad RG	126
76394c9c AP	127	memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
76394c9c AP	128	memset(jr->output_ring, 0, jr->op_size);
b9eebfad	129
76394c9c	130	start_jr0(sec_idx);
b9eebfad	131
76394c9c	132	jr_initregs(sec_idx);
b9eebfad RG	133
	134	return 0;
	135	}
	136
76394c9c	137	static int jr_sw_cleanup(uint8_t sec_idx)
b9eebfad	138	{
76394c9c AP	139	struct jobring *jr = &jr0[sec_idx];
	140
	141	jr->head = 0;
	142	jr->tail = 0;
	143	jr->read_idx = 0;
	144	jr->write_idx = 0;
	145	memset(jr->info, 0, sizeof(jr->info));
	146	memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
	147	memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
b9eebfad RG	148
	149	return 0;
	150	}
	151
76394c9c	152	static int jr_hw_reset(uint8_t sec_idx)
b9eebfad	153	{
76394c9c	154	struct jr_regs regs = (struct jr_regs )SEC_JR0_ADDR(sec_idx);
b9eebfad RG	155	uint32_t timeout = 100000;
	156	uint32_t jrint, jrcr;
	157
	158	sec_out32(&regs->jrcr, JRCR_RESET);
	159	do {
	160	jrint = sec_in32(&regs->jrint);
	161	} while (((jrint & JRINT_ERR_HALT_MASK) ==
	162	JRINT_ERR_HALT_INPROGRESS) && --timeout);
	163
	164	jrint = sec_in32(&regs->jrint);
	165	if (((jrint & JRINT_ERR_HALT_MASK) !=
	166	JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
	167	return -1;
	168
	169	timeout = 100000;
	170	sec_out32(&regs->jrcr, JRCR_RESET);
	171	do {
	172	jrcr = sec_in32(&regs->jrcr);
	173	} while ((jrcr & JRCR_RESET) && --timeout);
	174
	175	if (timeout == 0)
	176	return -1;
	177
	178	return 0;
	179	}
	180
	181	/* -1 --- error, can't enqueue -- no space available */
	182	static int jr_enqueue(uint32_t *desc_addr,
f59e69cb	183	void (callback)(uint32_t status, void arg),
76394c9c	184	void *arg, uint8_t sec_idx)
b9eebfad	185	{
76394c9c AP	186	struct jr_regs regs = (struct jr_regs )SEC_JR0_ADDR(sec_idx);
	187	struct jobring *jr = &jr0[sec_idx];
	188	int head = jr->head;
f59e69cb AB	189	uint32_t desc_word;
	190	int length = desc_len(desc_addr);
	191	int i;
	192	#ifdef CONFIG_PHYS_64BIT
	193	uint32_t addr_hi, addr_lo;
	194	#endif
	195
	196	/* The descriptor must be submitted to SEC block as per endianness
	197	* of the SEC Block.
	198	* So, if the endianness of Core and SEC block is different, each word
	199	* of the descriptor will be byte-swapped.
	200	*/
	201	for (i = 0; i < length; i++) {
	202	desc_word = desc_addr[i];
	203	sec_out32((uint32_t *)&desc_addr[i], desc_word);
	204	}
	205
	206	phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
b9eebfad	207
76394c9c AP	208	jr->info[head].desc_phys_addr = desc_phys_addr;
	209	jr->info[head].callback = (void *)callback;
	210	jr->info[head].arg = arg;
	211	jr->info[head].op_done = 0;
b9eebfad	212
76394c9c	213	unsigned long start = (unsigned long)&jr->info[head] &
0200020b	214	~(ARCH_DMA_MINALIGN - 1);
76394c9c	215	unsigned long end = ALIGN((unsigned long)&jr->info[head] +
7f4736bd	216	sizeof(struct jr_info), ARCH_DMA_MINALIGN);
0200020b RC	217	flush_dcache_range(start, end);
0200020b RC	218
f59e69cb AB	219	#ifdef CONFIG_PHYS_64BIT
	220	/* Write the 64 bit Descriptor address on Input Ring.
	221	* The 32 bit hign and low part of the address will
	222	* depend on endianness of SEC block.
	223	*/
	224	#ifdef CONFIG_SYS_FSL_SEC_LE
76394c9c AP	225	addr_lo = (uint32_t *)(&jr->input_ring[head]);
76394c9c AP	226	addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
f59e69cb	227	#elif defined(CONFIG_SYS_FSL_SEC_BE)
76394c9c AP	228	addr_hi = (uint32_t *)(&jr->input_ring[head]);
76394c9c AP	229	addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
f59e69cb AB	230	#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
	231
	232	sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
	233	sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
	234
	235	#else
	236	/* Write the 32 bit Descriptor address on Input Ring. */
76394c9c	237	sec_out32(&jr->input_ring[head], desc_phys_addr);
f59e69cb AB	238	#endif /* ifdef CONFIG_PHYS_64BIT */
f59e69cb AB	239
76394c9c AP	240	start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
76394c9c AP	241	end = ALIGN((unsigned long)&jr->input_ring[head] +
7f4736bd	242	sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
0200020b RC	243	flush_dcache_range(start, end);
0200020b RC	244
76394c9c	245	jr->head = (head + 1) & (jr->size - 1);
b9eebfad	246
7f4736bd	247	/* Invalidate output ring */
76394c9c	248	start = (unsigned long)jr->output_ring &
7f4736bd	249	~(ARCH_DMA_MINALIGN - 1);
76394c9c AP	250	end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
76394c9c AP	251	ARCH_DMA_MINALIGN);
7f4736bd RG	252	invalidate_dcache_range(start, end);
7f4736bd RG	253
b9eebfad RG	254	sec_out32(&regs->irja, 1);
	255
	256	return 0;
	257	}
	258
76394c9c	259	static int jr_dequeue(int sec_idx)
b9eebfad	260	{
76394c9c AP	261	struct jr_regs regs = (struct jr_regs )SEC_JR0_ADDR(sec_idx);
	262	struct jobring *jr = &jr0[sec_idx];
	263	int head = jr->head;
	264	int tail = jr->tail;
b9eebfad	265	int idx, i, found;
f59e69cb	266	void (callback)(uint32_t status, void arg);
b9eebfad	267	void *arg = NULL;
f59e69cb AB	268	#ifdef CONFIG_PHYS_64BIT
	269	uint32_t addr_hi, addr_lo;
	270	#else
	271	uint32_t *addr;
	272	#endif
b9eebfad	273
76394c9c AP	274	while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
76394c9c AP	275	jr->size)) {
0200020b	276
b9eebfad RG	277	found = 0;
b9eebfad RG	278
f59e69cb AB	279	phys_addr_t op_desc;
	280	#ifdef CONFIG_PHYS_64BIT
	281	/* Read the 64 bit Descriptor address from Output Ring.
	282	* The 32 bit hign and low part of the address will
	283	* depend on endianness of SEC block.
	284	*/
	285	#ifdef CONFIG_SYS_FSL_SEC_LE
76394c9c AP	286	addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
76394c9c AP	287	addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
f59e69cb	288	#elif defined(CONFIG_SYS_FSL_SEC_BE)
76394c9c AP	289	addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
76394c9c AP	290	addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
f59e69cb AB	291	#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
	292
	293	op_desc = ((u64)sec_in32(addr_hi) << 32) \|
	294	((u64)sec_in32(addr_lo));
	295
	296	#else
	297	/* Read the 32 bit Descriptor address from Output Ring. */
76394c9c	298	addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
f59e69cb AB	299	op_desc = sec_in32(addr);
	300	#endif /* ifdef CONFIG_PHYS_64BIT */
	301
76394c9c	302	uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
b9eebfad	303
76394c9c AP	304	for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
	305	idx = (tail + i) & (jr->size - 1);
	306	if (op_desc == jr->info[idx].desc_phys_addr) {
b9eebfad RG	307	found = 1;
	308	break;
	309	}
	310	}
	311
	312	/* Error condition if match not found */
	313	if (!found)
	314	return -1;
	315
76394c9c AP	316	jr->info[idx].op_done = 1;
	317	callback = (void *)jr->info[idx].callback;
	318	arg = jr->info[idx].arg;
b9eebfad RG	319
	320	/* When the job on tail idx gets done, increment
	321	* tail till the point where job completed out of oredr has
	322	* been taken into account
	323	*/
	324	if (idx == tail)
	325	do {
76394c9c AP	326	tail = (tail + 1) & (jr->size - 1);
76394c9c AP	327	} while (jr->info[tail].op_done);
b9eebfad	328
76394c9c AP	329	jr->tail = tail;
76394c9c AP	330	jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
b9eebfad RG	331
b9eebfad RG	332	sec_out32(&regs->orjr, 1);
76394c9c	333	jr->info[idx].op_done = 0;
b9eebfad	334
f59e69cb	335	callback(status, arg);
b9eebfad RG	336	}
	337
	338	return 0;
	339	}
	340
f59e69cb	341	static void desc_done(uint32_t status, void *arg)
b9eebfad RG	342	{
	343	struct result *x = arg;
	344	x->status = status;
	345	caam_jr_strstatus(status);
	346	x->done = 1;
	347	}
	348
76394c9c	349	static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
b9eebfad RG	350	{
	351	unsigned long long timeval = get_ticks();
	352	unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
	353	struct result op;
	354	int ret = 0;
	355
851c9dba	356	memset(&op, 0, sizeof(op));
b9eebfad	357
76394c9c	358	ret = jr_enqueue(desc, desc_done, &op, sec_idx);
b9eebfad RG	359	if (ret) {
	360	debug("Error in SEC enq\n");
	361	ret = JQ_ENQ_ERR;
	362	goto out;
	363	}
	364
	365	timeval = get_ticks();
	366	timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
	367	while (op.done != 1) {
76394c9c	368	ret = jr_dequeue(sec_idx);
b9eebfad RG	369	if (ret) {
	370	debug("Error in SEC deq\n");
	371	ret = JQ_DEQ_ERR;
	372	goto out;
	373	}
	374
	375	if ((get_ticks() - timeval) > timeout) {
	376	debug("SEC Dequeue timed out\n");
	377	ret = JQ_DEQ_TO_ERR;
	378	goto out;
	379	}
	380	}
	381
6178e959	382	if (op.status) {
b9eebfad RG	383	debug("Error %x\n", op.status);
	384	ret = op.status;
	385	}
	386	out:
	387	return ret;
	388	}
	389
76394c9c AP	390	int run_descriptor_jr(uint32_t *desc)
	391	{
	392	return run_descriptor_jr_idx(desc, 0);
	393	}
	394
	395	static inline int jr_reset_sec(uint8_t sec_idx)
b9eebfad	396	{
76394c9c	397	if (jr_hw_reset(sec_idx) < 0)
b9eebfad RG	398	return -1;
	399
	400	/* Clean up the jobring structure maintained by software */
76394c9c	401	jr_sw_cleanup(sec_idx);
b9eebfad RG	402
	403	return 0;
	404	}
	405
76394c9c	406	int jr_reset(void)
b9eebfad	407	{
76394c9c AP	408	return jr_reset_sec(0);
	409	}
	410
	411	static inline int sec_reset_idx(uint8_t sec_idx)
	412	{
	413	ccsr_sec_t sec = (void )SEC_ADDR(sec_idx);
b9eebfad RG	414	uint32_t mcfgr = sec_in32(&sec->mcfgr);
	415	uint32_t timeout = 100000;
	416
	417	mcfgr \|= MCFGR_SWRST;
	418	sec_out32(&sec->mcfgr, mcfgr);
	419
	420	mcfgr \|= MCFGR_DMA_RST;
	421	sec_out32(&sec->mcfgr, mcfgr);
	422	do {
	423	mcfgr = sec_in32(&sec->mcfgr);
	424	} while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
	425
	426	if (timeout == 0)
	427	return -1;
	428
	429	timeout = 100000;
	430	do {
	431	mcfgr = sec_in32(&sec->mcfgr);
	432	} while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
	433
	434	if (timeout == 0)
	435	return -1;
	436
	437	return 0;
	438	}
	439
76394c9c	440	static int instantiate_rng(uint8_t sec_idx)
c5de15cb RG	441	{
	442	struct result op;
	443	u32 *desc;
	444	u32 rdsta_val;
	445	int ret = 0;
76394c9c	446	ccsr_sec_t __iomem sec = (ccsr_sec_t __iomem )SEC_ADDR(sec_idx);
c5de15cb RG	447	struct rng4tst __iomem *rng =
	448	(struct rng4tst __iomem *)&sec->rng;
	449
	450	memset(&op, 0, sizeof(struct result));
	451
0200020b	452	desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
c5de15cb RG	453	if (!desc) {
	454	printf("cannot allocate RNG init descriptor memory\n");
	455	return -1;
	456	}
	457
	458	inline_cnstr_jobdesc_rng_instantiation(desc);
0200020b RC	459	int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
	460	flush_dcache_range((unsigned long)desc,
	461	(unsigned long)desc + size);
	462
76394c9c	463	ret = run_descriptor_jr_idx(desc, sec_idx);
c5de15cb RG	464
	465	if (ret)
	466	printf("RNG: Instantiation failed with error %x\n", ret);
	467
	468	rdsta_val = sec_in32(&rng->rdsta);
	469	if (op.status \|\| !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
	470	return -1;
	471
	472	return ret;
	473	}
	474
76394c9c AP	475	int sec_reset(void)
	476	{
	477	return sec_reset_idx(0);
	478	}
	479
	480	static u8 get_rng_vid(uint8_t sec_idx)
c5de15cb	481	{
76394c9c	482	ccsr_sec_t sec = (void )SEC_ADDR(sec_idx);
c5de15cb RG	483	u32 cha_vid = sec_in32(&sec->chavid_ls);
	484
	485	return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
	486	}
	487
	488	/*
	489	* By default, the TRNG runs for 200 clocks per sample;
	490	* 1200 clocks per sample generates better entropy.
	491	*/
76394c9c	492	static void kick_trng(int ent_delay, uint8_t sec_idx)
c5de15cb	493	{
76394c9c	494	ccsr_sec_t __iomem sec = (ccsr_sec_t __iomem )SEC_ADDR(sec_idx);
c5de15cb RG	495	struct rng4tst __iomem *rng =
	496	(struct rng4tst __iomem *)&sec->rng;
	497	u32 val;
	498
	499	/* put RNG4 into program mode */
	500	sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
	501	/* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
	502	* length (in system clocks) of each Entropy sample taken
	503	* */
	504	val = sec_in32(&rng->rtsdctl);
	505	val = (val & ~RTSDCTL_ENT_DLY_MASK) \|
	506	(ent_delay << RTSDCTL_ENT_DLY_SHIFT);
	507	sec_out32(&rng->rtsdctl, val);
	508	/* min. freq. count, equal to 1/4 of the entropy sample length */
	509	sec_out32(&rng->rtfreqmin, ent_delay >> 2);
026a3f1b AP	510	/* disable maximum frequency count */
026a3f1b AP	511	sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
c4065517 AP	512	/*
	513	* select raw sampling in both entropy shifter
	514	* and statistical checker
	515	*/
3a4800a5	516	sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
c5de15cb	517	/* put RNG4 into run mode */
3a4800a5	518	sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
c5de15cb RG	519	}
c5de15cb RG	520
76394c9c	521	static int rng_init(uint8_t sec_idx)
c5de15cb RG	522	{
c5de15cb RG	523	int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
76394c9c	524	ccsr_sec_t __iomem sec = (ccsr_sec_t __iomem )SEC_ADDR(sec_idx);
c5de15cb RG	525	struct rng4tst __iomem *rng =
	526	(struct rng4tst __iomem *)&sec->rng;
	527
	528	u32 rdsta = sec_in32(&rng->rdsta);
	529
	530	/* Check if RNG state 0 handler is already instantiated */
	531	if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
	532	return 0;
	533
	534	do {
	535	/*
	536	* If either of the SH's were instantiated by somebody else
	537	* then it is assumed that the entropy
	538	* parameters are properly set and thus the function
	539	* setting these (kick_trng(...)) is skipped.
	540	* Also, if a handle was instantiated, do not change
	541	* the TRNG parameters.
	542	*/
76394c9c	543	kick_trng(ent_delay, sec_idx);
c5de15cb RG	544	ent_delay += 400;
	545	/*
	546	* if instantiate_rng(...) fails, the loop will rerun
	547	* and the kick_trng(...) function will modfiy the
	548	* upper and lower limits of the entropy sampling
	549	* interval, leading to a sucessful initialization of
	550	* the RNG.
	551	*/
76394c9c	552	ret = instantiate_rng(sec_idx);
c5de15cb RG	553	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
	554	if (ret) {
	555	printf("RNG: Failed to instantiate RNG\n");
	556	return ret;
	557	}
	558
	559	/* Enable RDB bit so that RNG works faster */
	560	sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
	561
	562	return ret;
	563	}
	564
76394c9c	565	int sec_init_idx(uint8_t sec_idx)
b9eebfad	566	{
76394c9c	567	ccsr_sec_t sec = (void )SEC_ADDR(sec_idx);
b9eebfad	568	uint32_t mcr = sec_in32(&sec->mcfgr);
3ef2412d	569	int ret = 0;
b9eebfad	570
f698e9f3 AB	571	#ifdef CONFIG_FSL_CORENET
	572	uint32_t liodnr;
	573	uint32_t liodn_ns;
	574	uint32_t liodn_s;
	575	#endif
	576
76394c9c AP	577	if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
	578	printf("SEC initialization failed\n");
	579	return -1;
	580	}
	581
8a6f83dc SJ	582	/*
8a6f83dc SJ	583	* Modifying CAAM Read/Write Attributes
3c1d218a	584	* For LS2080A
8a6f83dc SJ	585	* For AXI Write - Cacheable, Write Back, Write allocate
8a6f83dc SJ	586	* For AXI Read - Cacheable, Read allocate
3c1d218a	587	* Only For LS2080a, to solve CAAM coherency issues
8a6f83dc	588	*/
3c1d218a	589	#ifdef CONFIG_LS2080A
8a6f83dc SJ	590	mcr = (mcr & ~MCFGR_AWCACHE_MASK) \| (0xb << MCFGR_AWCACHE_SHIFT);
	591	mcr = (mcr & ~MCFGR_ARCACHE_MASK) \| (0x6 << MCFGR_ARCACHE_SHIFT);
	592	#else
3ef2412d	593	mcr = (mcr & ~MCFGR_AWCACHE_MASK) \| (0x2 << MCFGR_AWCACHE_SHIFT);
8a6f83dc SJ	594	#endif
8a6f83dc SJ	595
3ef2412d	596	#ifdef CONFIG_PHYS_64BIT
3ef2412d	597	mcr \|= (1 << MCFGR_PS_SHIFT);
b9eebfad	598	#endif
3ef2412d	599	sec_out32(&sec->mcfgr, mcr);
3ef2412d	600
f698e9f3	601	#ifdef CONFIG_FSL_CORENET
8f01397b SG	602	#ifdef CONFIG_SPL_BUILD
	603	/*
	604	* For SPL Build, Set the Liodns in SEC JR0 for
	605	* creating PAMU entries corresponding to these.
	606	* For normal build, these are set in set_liodns().
	607	*/
	608	liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
	609	liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
	610
	611	liodnr = sec_in32(&sec->jrliodnr[0].ls) &
	612	~(JRNSLIODN_MASK \| JRSLIODN_MASK);
	613	liodnr = liodnr \|
	614	(liodn_ns << JRNSLIODN_SHIFT) \|
	615	(liodn_s << JRSLIODN_SHIFT);
	616	sec_out32(&sec->jrliodnr[0].ls, liodnr);
	617	#else
f698e9f3 AB	618	liodnr = sec_in32(&sec->jrliodnr[0].ls);
	619	liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
	620	liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
8f01397b	621	#endif
f698e9f3 AB	622	#endif
f698e9f3 AB	623
76394c9c	624	ret = jr_init(sec_idx);
c5de15cb RG	625	if (ret < 0) {
c5de15cb RG	626	printf("SEC initialization failed\n");
b9eebfad	627	return -1;
c5de15cb RG	628	}
c5de15cb RG	629
f698e9f3 AB	630	#ifdef CONFIG_FSL_CORENET
	631	ret = sec_config_pamu_table(liodn_ns, liodn_s);
	632	if (ret < 0)
	633	return -1;
	634
	635	pamu_enable();
	636	#endif
	637
76394c9c AP	638	if (get_rng_vid(sec_idx) >= 4) {
	639	if (rng_init(sec_idx) < 0) {
	640	printf("SEC%u: RNG instantiation failed\n", sec_idx);
c5de15cb RG	641	return -1;
c5de15cb RG	642	}
76394c9c	643	printf("SEC%u: RNG instantiated\n", sec_idx);
c5de15cb	644	}
b9eebfad RG	645
	646	return ret;
	647	}
76394c9c AP	648
	649	int sec_init(void)
	650	{
	651	return sec_init_idx(0);
	652	}