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1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
3 | * | |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
233fdd50 KG |
5 | */ |
6 | ||
7 | #include <common.h> | |
5614e71b | 8 | #include <fsl_ddr_sdram.h> |
233fdd50 | 9 | |
5614e71b | 10 | #include <fsl_ddr.h> |
233fdd50 KG |
11 | /* |
12 | * Calculate the Density of each Physical Rank. | |
13 | * Returned size is in bytes. | |
14 | * | |
15 | * Study these table from Byte 31 of JEDEC SPD Spec. | |
16 | * | |
17 | * DDR I DDR II | |
18 | * Bit Size Size | |
19 | * --- ----- ------ | |
20 | * 7 high 512MB 512MB | |
21 | * 6 256MB 256MB | |
22 | * 5 128MB 128MB | |
23 | * 4 64MB 16GB | |
24 | * 3 32MB 8GB | |
25 | * 2 16MB 4GB | |
26 | * 1 2GB 2GB | |
27 | * 0 low 1GB 1GB | |
28 | * | |
29 | * Reorder Table to be linear by stripping the bottom | |
30 | * 2 or 5 bits off and shifting them up to the top. | |
31 | * | |
32 | */ | |
e7563aff | 33 | static unsigned long long |
233fdd50 KG |
34 | compute_ranksize(unsigned int mem_type, unsigned char row_dens) |
35 | { | |
e7563aff | 36 | unsigned long long bsize; |
233fdd50 KG |
37 | |
38 | /* Bottom 5 bits up to the top. */ | |
39 | bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)); | |
40 | bsize <<= 27ULL; | |
cd84b1fa | 41 | debug("DDR: DDR II rank density = 0x%16llx\n", bsize); |
233fdd50 KG |
42 | |
43 | return bsize; | |
44 | } | |
45 | ||
46 | /* | |
47 | * Convert a two-nibble BCD value into a cycle time. | |
48 | * While the spec calls for nano-seconds, picos are returned. | |
49 | * | |
50 | * This implements the tables for bytes 9, 23 and 25 for both | |
51 | * DDR I and II. No allowance for distinguishing the invalid | |
52 | * fields absent for DDR I yet present in DDR II is made. | |
53 | * (That is, cycle times of .25, .33, .66 and .75 ns are | |
54 | * allowed for both DDR II and I.) | |
55 | */ | |
56 | static unsigned int | |
57 | convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) | |
58 | { | |
59 | /* Table look up the lower nibble, allow DDR I & II. */ | |
60 | unsigned int tenths_ps[16] = { | |
61 | 0, | |
62 | 100, | |
63 | 200, | |
64 | 300, | |
65 | 400, | |
66 | 500, | |
67 | 600, | |
68 | 700, | |
69 | 800, | |
70 | 900, | |
71 | 250, /* This and the next 3 entries valid ... */ | |
72 | 330, /* ... only for tCK calculations. */ | |
73 | 660, | |
74 | 750, | |
75 | 0, /* undefined */ | |
76 | 0 /* undefined */ | |
77 | }; | |
78 | ||
79 | unsigned int whole_ns = (spd_val & 0xF0) >> 4; | |
80 | unsigned int tenth_ns = spd_val & 0x0F; | |
81 | unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; | |
82 | ||
83 | return ps; | |
84 | } | |
85 | ||
86 | static unsigned int | |
87 | convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) | |
88 | { | |
89 | unsigned int tenth_ns = (spd_val & 0xF0) >> 4; | |
90 | unsigned int hundredth_ns = spd_val & 0x0F; | |
91 | unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; | |
92 | ||
93 | return ps; | |
94 | } | |
95 | ||
96 | static unsigned int byte40_table_ps[8] = { | |
97 | 0, | |
98 | 250, | |
99 | 330, | |
100 | 500, | |
101 | 660, | |
102 | 750, | |
103 | 0, /* supposed to be RFC, but not sure what that means */ | |
104 | 0 /* Undefined */ | |
105 | }; | |
106 | ||
107 | static unsigned int | |
108 | compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) | |
109 | { | |
a4ca3799 | 110 | return (((trctrfc_ext & 0x1) * 256) + trfc) * 1000 |
233fdd50 | 111 | + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; |
233fdd50 KG |
112 | } |
113 | ||
114 | static unsigned int | |
115 | compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) | |
116 | { | |
a4ca3799 | 117 | return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; |
233fdd50 KG |
118 | } |
119 | ||
120 | /* | |
121 | * Determine Refresh Rate. Ignore self refresh bit on DDR I. | |
122 | * Table from SPD Spec, Byte 12, converted to picoseconds and | |
123 | * filled in with "default" normal values. | |
124 | */ | |
125 | static unsigned int | |
126 | determine_refresh_rate_ps(const unsigned int spd_refresh) | |
127 | { | |
128 | unsigned int refresh_time_ps[8] = { | |
129 | 15625000, /* 0 Normal 1.00x */ | |
130 | 3900000, /* 1 Reduced .25x */ | |
131 | 7800000, /* 2 Extended .50x */ | |
132 | 31300000, /* 3 Extended 2.00x */ | |
133 | 62500000, /* 4 Extended 4.00x */ | |
134 | 125000000, /* 5 Extended 8.00x */ | |
135 | 15625000, /* 6 Normal 1.00x filler */ | |
136 | 15625000, /* 7 Normal 1.00x filler */ | |
137 | }; | |
138 | ||
139 | return refresh_time_ps[spd_refresh & 0x7]; | |
140 | } | |
141 | ||
142 | /* | |
143 | * The purpose of this function is to compute a suitable | |
144 | * CAS latency given the DRAM clock period. The SPD only | |
145 | * defines at most 3 CAS latencies. Typically the slower in | |
146 | * frequency the DIMM runs at, the shorter its CAS latency can. | |
147 | * be. If the DIMM is operating at a sufficiently low frequency, | |
148 | * it may be able to run at a CAS latency shorter than the | |
149 | * shortest SPD-defined CAS latency. | |
150 | * | |
151 | * If a CAS latency is not found, 0 is returned. | |
152 | * | |
153 | * Do this by finding in the standard speed bin table the longest | |
154 | * tCKmin that doesn't exceed the value of mclk_ps (tCK). | |
155 | * | |
156 | * An assumption made is that the SDRAM device allows the | |
157 | * CL to be programmed for a value that is lower than those | |
158 | * advertised by the SPD. This is not always the case, | |
159 | * as those modes not defined in the SPD are optional. | |
160 | * | |
161 | * CAS latency de-rating based upon values JEDEC Standard No. 79-2C | |
162 | * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS, | |
163 | * and tRC for corresponding bin" | |
164 | * | |
165 | * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3 | |
166 | * Not certain if any good value exists for CL=2 | |
167 | */ | |
bcb6c2bb YS |
168 | /* CL2 CL3 CL4 CL5 CL6 CL7*/ |
169 | unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 }; | |
233fdd50 KG |
170 | |
171 | unsigned int | |
172 | compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) | |
173 | { | |
174 | const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins); | |
175 | unsigned int lowest_tCKmin_found = 0; | |
176 | unsigned int lowest_tCKmin_CL = 0; | |
177 | unsigned int i; | |
178 | ||
179 | debug("mclk_ps = %u\n", mclk_ps); | |
180 | ||
181 | for (i = 0; i < num_speed_bins; i++) { | |
182 | unsigned int x = ddr2_speed_bins[i]; | |
183 | debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", | |
184 | i, x, lowest_tCKmin_found); | |
185 | if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) { | |
186 | lowest_tCKmin_found = x; | |
187 | lowest_tCKmin_CL = i + 2; | |
188 | } | |
189 | } | |
190 | ||
191 | debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); | |
192 | ||
193 | return lowest_tCKmin_CL; | |
194 | } | |
195 | ||
196 | /* | |
197 | * ddr_compute_dimm_parameters for DDR2 SPD | |
198 | * | |
199 | * Compute DIMM parameters based upon the SPD information in spd. | |
200 | * Writes the results to the dimm_params_t structure pointed by pdimm. | |
201 | * | |
202 | * FIXME: use #define for the retvals | |
203 | */ | |
03e664d8 YS |
204 | unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, |
205 | const ddr2_spd_eeprom_t *spd, | |
206 | dimm_params_t *pdimm, | |
207 | unsigned int dimm_number) | |
233fdd50 KG |
208 | { |
209 | unsigned int retval; | |
210 | ||
211 | if (spd->mem_type) { | |
212 | if (spd->mem_type != SPD_MEMTYPE_DDR2) { | |
213 | printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number); | |
214 | return 1; | |
215 | } | |
216 | } else { | |
217 | memset(pdimm, 0, sizeof(dimm_params_t)); | |
218 | return 1; | |
219 | } | |
220 | ||
221 | retval = ddr2_spd_check(spd); | |
222 | if (retval) { | |
223 | printf("DIMM %u: failed checksum\n", dimm_number); | |
224 | return 2; | |
225 | } | |
226 | ||
227 | /* | |
228 | * The part name in ASCII in the SPD EEPROM is not null terminated. | |
229 | * Guarantee null termination here by presetting all bytes to 0 | |
230 | * and copying the part name in ASCII from the SPD onto it | |
231 | */ | |
232 | memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); | |
233 | memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); | |
234 | ||
235 | /* DIMM organization parameters */ | |
236 | pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1; | |
237 | pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens); | |
238 | pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; | |
239 | pdimm->data_width = spd->dataw; | |
240 | pdimm->primary_sdram_width = spd->primw; | |
241 | pdimm->ec_sdram_width = spd->ecw; | |
242 | ||
c7fd27cc | 243 | /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ |
233fdd50 | 244 | switch (spd->dimm_type) { |
c7fd27cc KM |
245 | case DDR2_SPD_DIMMTYPE_RDIMM: |
246 | case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: | |
247 | case DDR2_SPD_DIMMTYPE_MINI_RDIMM: | |
248 | /* Registered/buffered DIMMs */ | |
249 | pdimm->registered_dimm = 1; | |
233fdd50 KG |
250 | break; |
251 | ||
c7fd27cc KM |
252 | case DDR2_SPD_DIMMTYPE_UDIMM: |
253 | case DDR2_SPD_DIMMTYPE_SO_DIMM: | |
254 | case DDR2_SPD_DIMMTYPE_MICRO_DIMM: | |
255 | case DDR2_SPD_DIMMTYPE_MINI_UDIMM: | |
256 | /* Unbuffered DIMMs */ | |
257 | pdimm->registered_dimm = 0; | |
233fdd50 KG |
258 | break; |
259 | ||
c7fd27cc | 260 | case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: |
233fdd50 KG |
261 | default: |
262 | printf("unknown dimm_type 0x%02X\n", spd->dimm_type); | |
263 | return 1; | |
233fdd50 KG |
264 | } |
265 | ||
266 | /* SDRAM device parameters */ | |
267 | pdimm->n_row_addr = spd->nrow_addr; | |
268 | pdimm->n_col_addr = spd->ncol_addr; | |
269 | pdimm->n_banks_per_sdram_device = spd->nbanks; | |
270 | pdimm->edc_config = spd->config; | |
271 | pdimm->burst_lengths_bitmask = spd->burstl; | |
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272 | |
273 | /* | |
274 | * Calculate the Maximum Data Rate based on the Minimum Cycle time. | |
275 | * The SPD clk_cycle field (tCKmin) is measured in tenths of | |
276 | * nanoseconds and represented as BCD. | |
277 | */ | |
0dd38a35 | 278 | pdimm->tckmin_x_ps |
233fdd50 | 279 | = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); |
0dd38a35 | 280 | pdimm->tckmin_x_minus_1_ps |
233fdd50 | 281 | = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); |
0dd38a35 | 282 | pdimm->tckmin_x_minus_2_ps |
233fdd50 KG |
283 | = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); |
284 | ||
0dd38a35 | 285 | pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); |
233fdd50 KG |
286 | |
287 | /* | |
288 | * Compute CAS latencies defined by SPD | |
0dd38a35 | 289 | * The SPD caslat_x should have at least 1 and at most 3 bits set. |
233fdd50 KG |
290 | * |
291 | * If cas_lat after masking is 0, the __ilog2 function returns | |
292 | * 255 into the variable. This behavior is abused once. | |
293 | */ | |
0dd38a35 PJ |
294 | pdimm->caslat_x = __ilog2(spd->cas_lat); |
295 | pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat | |
296 | & ~(1 << pdimm->caslat_x)); | |
297 | pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat | |
298 | & ~(1 << pdimm->caslat_x) | |
299 | & ~(1 << pdimm->caslat_x_minus_1)); | |
233fdd50 KG |
300 | |
301 | /* Compute CAS latencies below that defined by SPD */ | |
03e664d8 YS |
302 | pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency( |
303 | get_memory_clk_period_ps(ctrl_num)); | |
233fdd50 KG |
304 | |
305 | /* Compute timing parameters */ | |
0dd38a35 PJ |
306 | pdimm->trcd_ps = spd->trcd * 250; |
307 | pdimm->trp_ps = spd->trp * 250; | |
308 | pdimm->tras_ps = spd->tras * 1000; | |
233fdd50 | 309 | |
0dd38a35 PJ |
310 | pdimm->twr_ps = spd->twr * 250; |
311 | pdimm->twtr_ps = spd->twtr * 250; | |
312 | pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); | |
233fdd50 | 313 | |
0dd38a35 PJ |
314 | pdimm->trrd_ps = spd->trrd * 250; |
315 | pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); | |
233fdd50 KG |
316 | |
317 | pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); | |
318 | ||
0dd38a35 PJ |
319 | pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); |
320 | pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); | |
321 | pdimm->tds_ps | |
233fdd50 | 322 | = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); |
0dd38a35 | 323 | pdimm->tdh_ps |
233fdd50 KG |
324 | = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); |
325 | ||
0dd38a35 PJ |
326 | pdimm->trtp_ps = spd->trtp * 250; |
327 | pdimm->tdqsq_max_ps = spd->tdqsq * 10; | |
328 | pdimm->tqhs_ps = spd->tqhs * 10; | |
233fdd50 KG |
329 | |
330 | return 0; | |
331 | } |