[people/ms/u-boot.git] / drivers / ddr / fsl / ddr2_dimm_params.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <fsl_ddr_sdram.h>

#include <fsl_ddr.h>
/*
 * Calculate the Density of each Physical Rank.
 * Returned size is in bytes.
 *
 * Study these table from Byte 31 of JEDEC SPD Spec.
 *
 *		DDR I	DDR II
 *	Bit	Size	Size
 *	---	-----	------
 *	7 high	512MB	512MB
 *	6	256MB	256MB
 *	5	128MB	128MB
 *	4	 64MB	 16GB
 *	3	 32MB	  8GB
 *	2	 16MB	  4GB
 *	1	  2GB	  2GB
 *	0 low	  1GB	  1GB
 *
 * Reorder Table to be linear by stripping the bottom
 * 2 or 5 bits off and shifting them up to the top.
 *
 */
static unsigned long long
compute_ranksize(unsigned int mem_type, unsigned char row_dens)
{
	unsigned long long bsize;

	/* Bottom 5 bits up to the top. */
	bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));
	bsize <<= 27ULL;
	debug("DDR: DDR II rank density = 0x%16llx\n", bsize);

	return bsize;
}

/*
 * Convert a two-nibble BCD value into a cycle time.
 * While the spec calls for nano-seconds, picos are returned.
 *
 * This implements the tables for bytes 9, 23 and 25 for both
 * DDR I and II.  No allowance for distinguishing the invalid
 * fields absent for DDR I yet present in DDR II is made.
 * (That is, cycle times of .25, .33, .66 and .75 ns are
 * allowed for both DDR II and I.)
 */
static unsigned int
convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
{
	/* Table look up the lower nibble, allow DDR I & II. */
	unsigned int tenths_ps[16] = {
		0,
		100,
		200,
		300,
		400,
		500,
		600,
		700,
		800,
		900,
		250,	/* This and the next 3 entries valid ... */
		330,	/* ...  only for tCK calculations. */
		660,
		750,
		0,	/* undefined */
		0	/* undefined */
	};

	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
	unsigned int tenth_ns = spd_val & 0x0F;
	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];

	return ps;
}

static unsigned int
convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
{
	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
	unsigned int hundredth_ns = spd_val & 0x0F;
	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;

	return ps;
}

static unsigned int byte40_table_ps[8] = {
	0,
	250,
	330,
	500,
	660,
	750,
	0,	/* supposed to be RFC, but not sure what that means */
	0	/* Undefined */
};

static unsigned int
compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
{
	unsigned int trfc_ps;

	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];

	return trfc_ps;
}

static unsigned int
compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
{
	unsigned int trc_ps;

	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];

	return trc_ps;
}

/*
 * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
 * Table from SPD Spec, Byte 12, converted to picoseconds and
 * filled in with "default" normal values.
 */
static unsigned int
determine_refresh_rate_ps(const unsigned int spd_refresh)
{
	unsigned int refresh_time_ps[8] = {
		15625000,	/* 0 Normal    1.00x */
		3900000,	/* 1 Reduced    .25x */
		7800000,	/* 2 Extended   .50x */
		31300000,	/* 3 Extended  2.00x */
		62500000,	/* 4 Extended  4.00x */
		125000000,	/* 5 Extended  8.00x */
		15625000,	/* 6 Normal    1.00x  filler */
		15625000,	/* 7 Normal    1.00x  filler */
	};

	return refresh_time_ps[spd_refresh & 0x7];
}

/*
 * The purpose of this function is to compute a suitable
 * CAS latency given the DRAM clock period.  The SPD only
 * defines at most 3 CAS latencies.  Typically the slower in
 * frequency the DIMM runs at, the shorter its CAS latency can.
 * be.  If the DIMM is operating at a sufficiently low frequency,
 * it may be able to run at a CAS latency shorter than the
 * shortest SPD-defined CAS latency.
 *
 * If a CAS latency is not found, 0 is returned.
 *
 * Do this by finding in the standard speed bin table the longest
 * tCKmin that doesn't exceed the value of mclk_ps (tCK).
 *
 * An assumption made is that the SDRAM device allows the
 * CL to be programmed for a value that is lower than those
 * advertised by the SPD.  This is not always the case,
 * as those modes not defined in the SPD are optional.
 *
 * CAS latency de-rating based upon values JEDEC Standard No. 79-2C
 * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS,
 * and tRC for corresponding bin"
 *
 * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
 * Not certain if any good value exists for CL=2
 */
				 /* CL2   CL3   CL4   CL5   CL6  CL7*/
unsigned short ddr2_speed_bins[] = {   0, 5000, 3750, 3000, 2500, 1875 };

unsigned int
compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
{
	const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins);
	unsigned int lowest_tCKmin_found = 0;
	unsigned int lowest_tCKmin_CL = 0;
	unsigned int i;

	debug("mclk_ps = %u\n", mclk_ps);

	for (i = 0; i < num_speed_bins; i++) {
		unsigned int x = ddr2_speed_bins[i];
		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
		      i, x, lowest_tCKmin_found);
		if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) {
			lowest_tCKmin_found = x;
			lowest_tCKmin_CL = i + 2;
		}
	}

	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);

	return lowest_tCKmin_CL;
}

/*
 * ddr_compute_dimm_parameters for DDR2 SPD
 *
 * Compute DIMM parameters based upon the SPD information in spd.
 * Writes the results to the dimm_params_t structure pointed by pdimm.
 *
 * FIXME: use #define for the retvals
 */
unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
					 const ddr2_spd_eeprom_t *spd,
					 dimm_params_t *pdimm,
					 unsigned int dimm_number)
{
	unsigned int retval;

	if (spd->mem_type) {
		if (spd->mem_type != SPD_MEMTYPE_DDR2) {
			printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number);
			return 1;
		}
	} else {
		memset(pdimm, 0, sizeof(dimm_params_t));
		return 1;
	}

	retval = ddr2_spd_check(spd);
	if (retval) {
		printf("DIMM %u: failed checksum\n", dimm_number);
		return 2;
	}

	/*
	 * The part name in ASCII in the SPD EEPROM is not null terminated.
	 * Guarantee null termination here by presetting all bytes to 0
	 * and copying the part name in ASCII from the SPD onto it
	 */
	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);

	/* DIMM organization parameters */
	pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1;
	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens);
	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
	pdimm->data_width = spd->dataw;
	pdimm->primary_sdram_width = spd->primw;
	pdimm->ec_sdram_width = spd->ecw;

	/* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */
	switch (spd->dimm_type) {
	case DDR2_SPD_DIMMTYPE_RDIMM:
	case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM:
	case DDR2_SPD_DIMMTYPE_MINI_RDIMM:
		/* Registered/buffered DIMMs */
		pdimm->registered_dimm = 1;
		break;

	case DDR2_SPD_DIMMTYPE_UDIMM:
	case DDR2_SPD_DIMMTYPE_SO_DIMM:
	case DDR2_SPD_DIMMTYPE_MICRO_DIMM:
	case DDR2_SPD_DIMMTYPE_MINI_UDIMM:
		/* Unbuffered DIMMs */
		pdimm->registered_dimm = 0;
		break;

	case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM:
	default:
		printf("unknown dimm_type 0x%02X\n", spd->dimm_type);
		return 1;
	}

	/* SDRAM device parameters */
	pdimm->n_row_addr = spd->nrow_addr;
	pdimm->n_col_addr = spd->ncol_addr;
	pdimm->n_banks_per_sdram_device = spd->nbanks;
	pdimm->edc_config = spd->config;
	pdimm->burst_lengths_bitmask = spd->burstl;
	pdimm->row_density = spd->rank_dens;

	/*
	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
	 * nanoseconds and represented as BCD.
	 */
	pdimm->tckmin_x_ps
		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
	pdimm->tckmin_x_minus_1_ps
		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
	pdimm->tckmin_x_minus_2_ps
		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);

	pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);

	/*
	 * Compute CAS latencies defined by SPD
	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
	 *
	 * If cas_lat after masking is 0, the __ilog2 function returns
	 * 255 into the variable.   This behavior is abused once.
	 */
	pdimm->caslat_x  = __ilog2(spd->cas_lat);
	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
					  & ~(1 << pdimm->caslat_x));
	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
					  & ~(1 << pdimm->caslat_x)
					  & ~(1 << pdimm->caslat_x_minus_1));

	/* Compute CAS latencies below that defined by SPD */
	pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(
					get_memory_clk_period_ps(ctrl_num));

	/* Compute timing parameters */
	pdimm->trcd_ps = spd->trcd * 250;
	pdimm->trp_ps = spd->trp * 250;
	pdimm->tras_ps = spd->tras * 1000;

	pdimm->twr_ps = spd->twr * 250;
	pdimm->twtr_ps = spd->twtr * 250;
	pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);

	pdimm->trrd_ps = spd->trrd * 250;
	pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);

	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);

	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
	pdimm->tds_ps
		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
	pdimm->tdh_ps
		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);

	pdimm->trtp_ps = spd->trtp * 250;
	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
	pdimm->tqhs_ps = spd->tqhs * 10;

	return 0;
}
Commit	Line	Data
233fdd50 KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
5b8031cc	4	* SPDX-License-Identifier: GPL-2.0
233fdd50 KG	5	*/
	6
	7	#include <common.h>
5614e71b	8	#include <fsl_ddr_sdram.h>
233fdd50	9
5614e71b	10	#include <fsl_ddr.h>
233fdd50 KG	11	/*
	12	* Calculate the Density of each Physical Rank.
	13	* Returned size is in bytes.
	14	*
	15	* Study these table from Byte 31 of JEDEC SPD Spec.
	16	*
	17	* DDR I DDR II
	18	* Bit Size Size
	19	* --- ----- ------
	20	* 7 high 512MB 512MB
	21	* 6 256MB 256MB
	22	* 5 128MB 128MB
	23	* 4 64MB 16GB
	24	* 3 32MB 8GB
	25	* 2 16MB 4GB
	26	* 1 2GB 2GB
	27	* 0 low 1GB 1GB
	28	*
	29	* Reorder Table to be linear by stripping the bottom
	30	* 2 or 5 bits off and shifting them up to the top.
	31	*
	32	*/
e7563aff	33	static unsigned long long
233fdd50 KG	34	compute_ranksize(unsigned int mem_type, unsigned char row_dens)
233fdd50 KG	35	{
e7563aff	36	unsigned long long bsize;
233fdd50 KG	37
	38	/* Bottom 5 bits up to the top. */
	39	bsize = ((row_dens >> 5) \| ((row_dens & 31) << 3));
	40	bsize <<= 27ULL;
cd84b1fa	41	debug("DDR: DDR II rank density = 0x%16llx\n", bsize);
233fdd50 KG	42
	43	return bsize;
	44	}
	45
	46	/*
	47	* Convert a two-nibble BCD value into a cycle time.
	48	* While the spec calls for nano-seconds, picos are returned.
	49	*
	50	* This implements the tables for bytes 9, 23 and 25 for both
	51	* DDR I and II. No allowance for distinguishing the invalid
	52	* fields absent for DDR I yet present in DDR II is made.
	53	* (That is, cycle times of .25, .33, .66 and .75 ns are
	54	* allowed for both DDR II and I.)
	55	*/
	56	static unsigned int
	57	convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
	58	{
	59	/* Table look up the lower nibble, allow DDR I & II. */
	60	unsigned int tenths_ps[16] = {
	61	0,
	62	100,
	63	200,
	64	300,
	65	400,
	66	500,
	67	600,
	68	700,
	69	800,
	70	900,
	71	250, /* This and the next 3 entries valid ... */
	72	330, /* ... only for tCK calculations. */
	73	660,
	74	750,
	75	0, /* undefined */
	76	0 /* undefined */
	77	};
	78
	79	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
	80	unsigned int tenth_ns = spd_val & 0x0F;
	81	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
	82
	83	return ps;
	84	}
	85
	86	static unsigned int
	87	convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
	88	{
	89	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
	90	unsigned int hundredth_ns = spd_val & 0x0F;
	91	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
	92
	93	return ps;
	94	}
	95
	96	static unsigned int byte40_table_ps[8] = {
	97	0,
	98	250,
	99	330,
	100	500,
	101	660,
	102	750,
	103	0, /* supposed to be RFC, but not sure what that means */
	104	0 /* Undefined */
	105	};
106
107	static unsigned int
108	compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
109	{
110	unsigned int trfc_ps;
111
112	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
113	+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
114
115	return trfc_ps;
116	}
117
118	static unsigned int
119	compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
120	{
121	unsigned int trc_ps;
122
123	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
124
125	return trc_ps;
126	}
127
128	/*
129	* Determine Refresh Rate. Ignore self refresh bit on DDR I.
130	* Table from SPD Spec, Byte 12, converted to picoseconds and
131	* filled in with "default" normal values.
132	*/
133	static unsigned int
134	determine_refresh_rate_ps(const unsigned int spd_refresh)
135	{
136	unsigned int refresh_time_ps[8] = {
137	15625000, /* 0 Normal 1.00x */
138	3900000, /* 1 Reduced .25x */
139	7800000, /* 2 Extended .50x */
140	31300000, /* 3 Extended 2.00x */
141	62500000, /* 4 Extended 4.00x */
142	125000000, /* 5 Extended 8.00x */
143	15625000, /* 6 Normal 1.00x filler */
144	15625000, /* 7 Normal 1.00x filler */
145	};
146
147	return refresh_time_ps[spd_refresh & 0x7];
148	}
149
150	/*
151	* The purpose of this function is to compute a suitable
152	* CAS latency given the DRAM clock period. The SPD only
153	* defines at most 3 CAS latencies. Typically the slower in
154	* frequency the DIMM runs at, the shorter its CAS latency can.
155	* be. If the DIMM is operating at a sufficiently low frequency,
156	* it may be able to run at a CAS latency shorter than the
157	* shortest SPD-defined CAS latency.
158	*
159	* If a CAS latency is not found, 0 is returned.
160	*
161	* Do this by finding in the standard speed bin table the longest
162	* tCKmin that doesn't exceed the value of mclk_ps (tCK).
163	*
164	* An assumption made is that the SDRAM device allows the
165	* CL to be programmed for a value that is lower than those
166	* advertised by the SPD. This is not always the case,
167	* as those modes not defined in the SPD are optional.
168	*
169	* CAS latency de-rating based upon values JEDEC Standard No. 79-2C
170	* Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS,
171	* and tRC for corresponding bin"
172	*
173	* ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
174	* Not certain if any good value exists for CL=2
175	*/
bcb6c2bb YS	176	/* CL2 CL3 CL4 CL5 CL6 CL7*/
bcb6c2bb YS	177	unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 };
233fdd50 KG	178
	179	unsigned int
	180	compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
	181	{
	182	const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins);
	183	unsigned int lowest_tCKmin_found = 0;
	184	unsigned int lowest_tCKmin_CL = 0;
	185	unsigned int i;
	186
	187	debug("mclk_ps = %u\n", mclk_ps);
	188
	189	for (i = 0; i < num_speed_bins; i++) {
	190	unsigned int x = ddr2_speed_bins[i];
	191	debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
	192	i, x, lowest_tCKmin_found);
	193	if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) {
	194	lowest_tCKmin_found = x;
	195	lowest_tCKmin_CL = i + 2;
	196	}
	197	}
	198
	199	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
	200
	201	return lowest_tCKmin_CL;
	202	}
	203
	204	/*
	205	* ddr_compute_dimm_parameters for DDR2 SPD
	206	*
	207	* Compute DIMM parameters based upon the SPD information in spd.
	208	* Writes the results to the dimm_params_t structure pointed by pdimm.
	209	*
	210	* FIXME: use #define for the retvals
	211	*/
03e664d8 YS	212	unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
	213	const ddr2_spd_eeprom_t *spd,
	214	dimm_params_t *pdimm,
	215	unsigned int dimm_number)
233fdd50 KG	216	{
	217	unsigned int retval;
	218
	219	if (spd->mem_type) {
	220	if (spd->mem_type != SPD_MEMTYPE_DDR2) {
	221	printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number);
	222	return 1;
	223	}
	224	} else {
	225	memset(pdimm, 0, sizeof(dimm_params_t));
	226	return 1;
	227	}
	228
	229	retval = ddr2_spd_check(spd);
	230	if (retval) {
	231	printf("DIMM %u: failed checksum\n", dimm_number);
	232	return 2;
	233	}
	234
	235	/*
	236	* The part name in ASCII in the SPD EEPROM is not null terminated.
	237	* Guarantee null termination here by presetting all bytes to 0
	238	* and copying the part name in ASCII from the SPD onto it
	239	*/
	240	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
	241	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
	242
	243	/* DIMM organization parameters */
	244	pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1;
	245	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens);
	246	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
	247	pdimm->data_width = spd->dataw;
	248	pdimm->primary_sdram_width = spd->primw;
	249	pdimm->ec_sdram_width = spd->ecw;
	250
c7fd27cc	251	/* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */
233fdd50	252	switch (spd->dimm_type) {
c7fd27cc KM	253	case DDR2_SPD_DIMMTYPE_RDIMM:
	254	case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM:
	255	case DDR2_SPD_DIMMTYPE_MINI_RDIMM:
	256	/* Registered/buffered DIMMs */
	257	pdimm->registered_dimm = 1;
233fdd50 KG	258	break;
233fdd50 KG	259
c7fd27cc KM	260	case DDR2_SPD_DIMMTYPE_UDIMM:
	261	case DDR2_SPD_DIMMTYPE_SO_DIMM:
	262	case DDR2_SPD_DIMMTYPE_MICRO_DIMM:
	263	case DDR2_SPD_DIMMTYPE_MINI_UDIMM:
	264	/* Unbuffered DIMMs */
	265	pdimm->registered_dimm = 0;
233fdd50 KG	266	break;
233fdd50 KG	267
c7fd27cc	268	case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM:
233fdd50 KG	269	default:
	270	printf("unknown dimm_type 0x%02X\n", spd->dimm_type);
	271	return 1;
233fdd50 KG	272	}
	273
	274	/* SDRAM device parameters */
	275	pdimm->n_row_addr = spd->nrow_addr;
	276	pdimm->n_col_addr = spd->ncol_addr;
	277	pdimm->n_banks_per_sdram_device = spd->nbanks;
	278	pdimm->edc_config = spd->config;
	279	pdimm->burst_lengths_bitmask = spd->burstl;
	280	pdimm->row_density = spd->rank_dens;
	281
	282	/*
	283	* Calculate the Maximum Data Rate based on the Minimum Cycle time.
	284	* The SPD clk_cycle field (tCKmin) is measured in tenths of
	285	* nanoseconds and represented as BCD.
	286	*/
0dd38a35	287	pdimm->tckmin_x_ps
233fdd50	288	= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
0dd38a35	289	pdimm->tckmin_x_minus_1_ps
233fdd50	290	= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
0dd38a35	291	pdimm->tckmin_x_minus_2_ps
233fdd50 KG	292	= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
233fdd50 KG	293
0dd38a35	294	pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
233fdd50 KG	295
	296	/*
	297	* Compute CAS latencies defined by SPD
0dd38a35	298	* The SPD caslat_x should have at least 1 and at most 3 bits set.
233fdd50 KG	299	*
	300	* If cas_lat after masking is 0, the __ilog2 function returns
	301	* 255 into the variable. This behavior is abused once.
	302	*/
0dd38a35 PJ	303	pdimm->caslat_x = __ilog2(spd->cas_lat);
	304	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
	305	& ~(1 << pdimm->caslat_x));
	306	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
	307	& ~(1 << pdimm->caslat_x)
	308	& ~(1 << pdimm->caslat_x_minus_1));
233fdd50 KG	309
233fdd50 KG	310	/* Compute CAS latencies below that defined by SPD */
03e664d8 YS	311	pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(
03e664d8 YS	312	get_memory_clk_period_ps(ctrl_num));
233fdd50 KG	313
233fdd50 KG	314	/* Compute timing parameters */
0dd38a35 PJ	315	pdimm->trcd_ps = spd->trcd * 250;
	316	pdimm->trp_ps = spd->trp * 250;
	317	pdimm->tras_ps = spd->tras * 1000;
233fdd50	318
0dd38a35 PJ	319	pdimm->twr_ps = spd->twr * 250;
	320	pdimm->twtr_ps = spd->twtr * 250;
	321	pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
233fdd50	322
0dd38a35 PJ	323	pdimm->trrd_ps = spd->trrd * 250;
0dd38a35 PJ	324	pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
233fdd50 KG	325
	326	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
	327
0dd38a35 PJ	328	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
	329	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
	330	pdimm->tds_ps
233fdd50	331	= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
0dd38a35	332	pdimm->tdh_ps
233fdd50 KG	333	= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
233fdd50 KG	334
0dd38a35 PJ	335	pdimm->trtp_ps = spd->trtp * 250;
	336	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
	337	pdimm->tqhs_ps = spd->tqhs * 10;
233fdd50 KG	338
	339	return 0;
	340	}