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79b2d0bb | 1 | /* |
eb5eb2b0 | 2 | * (C) Copyright 2007-2009 |
79b2d0bb SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr> | |
6 | * | |
7 | * (C) Copyright 2001 | |
8 | * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
28527096 SG |
11 | * |
12 | * NOTE: This driver should be converted to driver model before June 2017. | |
13 | * Please see doc/driver-model/i2c-howto.txt for instructions. | |
79b2d0bb | 14 | */ |
c609719b WD |
15 | |
16 | #include <common.h> | |
b36df561 SR |
17 | #include <asm/ppc4xx.h> |
18 | #include <asm/ppc4xx-i2c.h> | |
c609719b | 19 | #include <i2c.h> |
61f2b38a | 20 | #include <asm/io.h> |
c609719b | 21 | |
d87080b7 WD |
22 | DECLARE_GLOBAL_DATA_PTR; |
23 | ||
880540de DE |
24 | static inline struct ppc4xx_i2c *ppc4xx_get_i2c(int hwadapnr) |
25 | { | |
26 | unsigned long base; | |
27 | ||
28 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
29 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
30 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
31 | base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + (hwadapnr * 0x100); | |
32 | #elif defined(CONFIG_440) || defined(CONFIG_405EX) | |
33 | /* all remaining 440 variants */ | |
34 | base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + (hwadapnr * 0x100); | |
35 | #else | |
36 | /* all 405 variants */ | |
37 | base = 0xEF600500 + (hwadapnr * 0x100); | |
79b2d0bb | 38 | #endif |
880540de DE |
39 | return (struct ppc4xx_i2c *)base; |
40 | } | |
c609719b | 41 | |
880540de | 42 | static void _i2c_bus_reset(struct i2c_adapter *adap) |
c609719b | 43 | { |
880540de | 44 | struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr); |
79b2d0bb SR |
45 | int i; |
46 | u8 dc; | |
c609719b WD |
47 | |
48 | /* Reset status register */ | |
49 | /* write 1 in SCMP and IRQA to clear these fields */ | |
eb5eb2b0 | 50 | out_8(&i2c->sts, 0x0A); |
c609719b WD |
51 | |
52 | /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ | |
eb5eb2b0 | 53 | out_8(&i2c->extsts, 0x8F); |
79b2d0bb | 54 | |
53677ef1 | 55 | /* Place chip in the reset state */ |
eb5eb2b0 | 56 | out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); |
79b2d0bb SR |
57 | |
58 | /* Check if bus is free */ | |
eb5eb2b0 | 59 | dc = in_8(&i2c->directcntl); |
79b2d0bb SR |
60 | if (!DIRCTNL_FREE(dc)){ |
61 | /* Try to set bus free state */ | |
eb5eb2b0 | 62 | out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC); |
79b2d0bb SR |
63 | |
64 | /* Wait until we regain bus control */ | |
65 | for (i = 0; i < 100; ++i) { | |
eb5eb2b0 | 66 | dc = in_8(&i2c->directcntl); |
79b2d0bb SR |
67 | if (DIRCTNL_FREE(dc)) |
68 | break; | |
69 | ||
70 | /* Toggle SCL line */ | |
71 | dc ^= IIC_DIRCNTL_SCC; | |
eb5eb2b0 | 72 | out_8(&i2c->directcntl, dc); |
79b2d0bb SR |
73 | udelay(10); |
74 | dc ^= IIC_DIRCNTL_SCC; | |
eb5eb2b0 | 75 | out_8(&i2c->directcntl, dc); |
c609719b WD |
76 | } |
77 | } | |
79b2d0bb SR |
78 | |
79 | /* Remove reset */ | |
eb5eb2b0 | 80 | out_8(&i2c->xtcntlss, 0); |
c609719b WD |
81 | } |
82 | ||
880540de | 83 | static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) |
c609719b | 84 | { |
880540de | 85 | struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr); |
c609719b WD |
86 | int val, divisor; |
87 | ||
6d0f6bcf | 88 | #ifdef CONFIG_SYS_I2C_INIT_BOARD |
eb5eb2b0 SR |
89 | /* |
90 | * Call board specific i2c bus reset routine before accessing the | |
91 | * environment, which might be in a chip on that bus. For details | |
92 | * about this problem see doc/I2C_Edge_Conditions. | |
93 | */ | |
47cd00fa WD |
94 | i2c_init_board(); |
95 | #endif | |
96 | ||
880540de DE |
97 | /* Handle possible failed I2C state */ |
98 | /* FIXME: put this into i2c_init_board()? */ | |
99 | _i2c_bus_reset(adap); | |
c609719b | 100 | |
880540de DE |
101 | /* clear lo master address */ |
102 | out_8(&i2c->lmadr, 0); | |
c609719b | 103 | |
880540de DE |
104 | /* clear hi master address */ |
105 | out_8(&i2c->hmadr, 0); | |
c609719b | 106 | |
880540de DE |
107 | /* clear lo slave address */ |
108 | out_8(&i2c->lsadr, 0); | |
c609719b | 109 | |
880540de DE |
110 | /* clear hi slave address */ |
111 | out_8(&i2c->hsadr, 0); | |
c609719b | 112 | |
880540de DE |
113 | /* Clock divide Register */ |
114 | /* set divisor according to freq_opb */ | |
115 | divisor = (get_OPB_freq() - 1) / 10000000; | |
116 | if (divisor == 0) | |
117 | divisor = 1; | |
118 | out_8(&i2c->clkdiv, divisor); | |
c609719b | 119 | |
880540de DE |
120 | /* no interrupts */ |
121 | out_8(&i2c->intrmsk, 0); | |
c609719b | 122 | |
880540de DE |
123 | /* clear transfer count */ |
124 | out_8(&i2c->xfrcnt, 0); | |
c609719b | 125 | |
880540de DE |
126 | /* clear extended control & stat */ |
127 | /* write 1 in SRC SRS SWC SWS to clear these fields */ | |
128 | out_8(&i2c->xtcntlss, 0xF0); | |
c609719b | 129 | |
880540de DE |
130 | /* Mode Control Register |
131 | Flush Slave/Master data buffer */ | |
132 | out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); | |
c609719b | 133 | |
880540de | 134 | val = in_8(&i2c->mdcntl); |
c609719b | 135 | |
880540de DE |
136 | /* Ignore General Call, slave transfers are ignored, |
137 | * disable interrupts, exit unknown bus state, enable hold | |
138 | * SCL 100kHz normaly or FastMode for 400kHz and above | |
139 | */ | |
c609719b | 140 | |
880540de DE |
141 | val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL; |
142 | if (speed >= 400000) | |
143 | val |= IIC_MDCNTL_FSM; | |
144 | out_8(&i2c->mdcntl, val); | |
c609719b | 145 | |
880540de DE |
146 | /* clear control reg */ |
147 | out_8(&i2c->cntl, 0x00); | |
c609719b WD |
148 | } |
149 | ||
150 | /* | |
79b2d0bb SR |
151 | * This code tries to use the features of the 405GP i2c |
152 | * controller. It will transfer up to 4 bytes in one pass | |
153 | * on the loop. It only does out_8((u8 *)lbz) to the buffer when it | |
154 | * is possible to do out16(lhz) transfers. | |
155 | * | |
156 | * cmd_type is 0 for write 1 for read. | |
157 | * | |
158 | * addr_len can take any value from 0-255, it is only limited | |
159 | * by the char, we could make it larger if needed. If it is | |
160 | * 0 we skip the address write cycle. | |
161 | * | |
162 | * Typical case is a Write of an addr followd by a Read. The | |
163 | * IBM FAQ does not cover this. On the last byte of the write | |
7e78f7ad | 164 | * we don't set the creg CHT bit but the RPST bit. |
79b2d0bb SR |
165 | * |
166 | * It does not support address only transfers, there must be | |
167 | * a data part. If you want to write the address yourself, put | |
168 | * it in the data pointer. | |
169 | * | |
170 | * It does not support transfer to/from address 0. | |
171 | * | |
172 | * It does not check XFRCNT. | |
173 | */ | |
880540de DE |
174 | static int _i2c_transfer(struct i2c_adapter *adap, |
175 | unsigned char cmd_type, | |
79b2d0bb SR |
176 | unsigned char chip, |
177 | unsigned char addr[], | |
178 | unsigned char addr_len, | |
179 | unsigned char data[], | |
180 | unsigned short data_len) | |
c609719b | 181 | { |
880540de | 182 | struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr); |
eb5eb2b0 | 183 | u8 *ptr; |
8bde7f77 | 184 | int reading; |
eb5eb2b0 | 185 | int tran, cnt; |
8bde7f77 WD |
186 | int result; |
187 | int status; | |
188 | int i; | |
eb5eb2b0 | 189 | u8 creg; |
8bde7f77 | 190 | |
79b2d0bb SR |
191 | if (data == 0 || data_len == 0) { |
192 | /* Don't support data transfer of no length or to address 0 */ | |
8bde7f77 WD |
193 | printf( "i2c_transfer: bad call\n" ); |
194 | return IIC_NOK; | |
195 | } | |
79b2d0bb | 196 | if (addr && addr_len) { |
8bde7f77 WD |
197 | ptr = addr; |
198 | cnt = addr_len; | |
199 | reading = 0; | |
79b2d0bb | 200 | } else { |
8bde7f77 WD |
201 | ptr = data; |
202 | cnt = data_len; | |
203 | reading = cmd_type; | |
204 | } | |
205 | ||
79b2d0bb | 206 | /* Clear Stop Complete Bit */ |
eb5eb2b0 SR |
207 | out_8(&i2c->sts, IIC_STS_SCMP); |
208 | ||
8bde7f77 | 209 | /* Check init */ |
79b2d0bb | 210 | i = 10; |
8bde7f77 WD |
211 | do { |
212 | /* Get status */ | |
eb5eb2b0 | 213 | status = in_8(&i2c->sts); |
8bde7f77 | 214 | i--; |
79b2d0bb | 215 | } while ((status & IIC_STS_PT) && (i > 0)); |
8bde7f77 WD |
216 | |
217 | if (status & IIC_STS_PT) { | |
218 | result = IIC_NOK_TOUT; | |
219 | return(result); | |
220 | } | |
eb5eb2b0 | 221 | |
79b2d0bb | 222 | /* flush the Master/Slave Databuffers */ |
eb5eb2b0 SR |
223 | out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) | |
224 | IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB); | |
225 | ||
79b2d0bb | 226 | /* need to wait 4 OPB clocks? code below should take that long */ |
8bde7f77 WD |
227 | |
228 | /* 7-bit adressing */ | |
eb5eb2b0 SR |
229 | out_8(&i2c->hmadr, 0); |
230 | out_8(&i2c->lmadr, chip); | |
8bde7f77 WD |
231 | |
232 | tran = 0; | |
233 | result = IIC_OK; | |
234 | creg = 0; | |
235 | ||
79b2d0bb | 236 | while (tran != cnt && (result == IIC_OK)) { |
8bde7f77 WD |
237 | int bc,j; |
238 | ||
eb5eb2b0 SR |
239 | /* |
240 | * Control register = | |
241 | * Normal transfer, 7-bits adressing, Transfer up to | |
242 | * bc bytes, Normal start, Transfer is a sequence of transfers | |
79b2d0bb | 243 | */ |
8bde7f77 WD |
244 | creg |= IIC_CNTL_PT; |
245 | ||
79b2d0bb SR |
246 | bc = (cnt - tran) > 4 ? 4 : cnt - tran; |
247 | creg |= (bc - 1) << 4; | |
248 | /* if the real cmd type is write continue trans */ | |
249 | if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) | |
8bde7f77 WD |
250 | creg |= IIC_CNTL_CHT; |
251 | ||
7e78f7ad DE |
252 | /* last part of address, prepare for repeated start on read */ |
253 | if (cmd_type && (ptr == addr) && ((tran + bc) == cnt)) | |
254 | creg |= IIC_CNTL_RPST; | |
255 | ||
eb5eb2b0 | 256 | if (reading) { |
8bde7f77 | 257 | creg |= IIC_CNTL_READ; |
eb5eb2b0 SR |
258 | } else { |
259 | for(j = 0; j < bc; j++) { | |
8bde7f77 | 260 | /* Set buffer */ |
eb5eb2b0 SR |
261 | out_8(&i2c->mdbuf, ptr[tran + j]); |
262 | } | |
263 | } | |
264 | out_8(&i2c->cntl, creg); | |
8bde7f77 | 265 | |
eb5eb2b0 SR |
266 | /* |
267 | * Transfer is in progress | |
79b2d0bb SR |
268 | * we have to wait for upto 5 bytes of data |
269 | * 1 byte chip address+r/w bit then bc bytes | |
270 | * of data. | |
271 | * udelay(10) is 1 bit time at 100khz | |
272 | * Doubled for slop. 20 is too small. | |
273 | */ | |
eb5eb2b0 | 274 | i = 2 * 5 * 8; |
8bde7f77 WD |
275 | do { |
276 | /* Get status */ | |
eb5eb2b0 | 277 | status = in_8(&i2c->sts); |
79b2d0bb | 278 | udelay(10); |
8bde7f77 | 279 | i--; |
eb5eb2b0 SR |
280 | } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && |
281 | (i > 0)); | |
c609719b | 282 | |
8bde7f77 WD |
283 | if (status & IIC_STS_ERR) { |
284 | result = IIC_NOK; | |
eb5eb2b0 | 285 | status = in_8(&i2c->extsts); |
8bde7f77 WD |
286 | /* Lost arbitration? */ |
287 | if (status & IIC_EXTSTS_LA) | |
288 | result = IIC_NOK_LA; | |
289 | /* Incomplete transfer? */ | |
290 | if (status & IIC_EXTSTS_ICT) | |
291 | result = IIC_NOK_ICT; | |
292 | /* Transfer aborted? */ | |
293 | if (status & IIC_EXTSTS_XFRA) | |
294 | result = IIC_NOK_XFRA; | |
b97cd681 DE |
295 | /* Is bus free? |
296 | * If error happened during combined xfer | |
297 | * IIC interface is usually stuck in some strange | |
298 | * state without a valid stop condition. | |
299 | * Brute, but working: generate stop, then soft reset. | |
300 | */ | |
301 | if ((status & IIC_EXTSTS_BCS_MASK) | |
302 | != IIC_EXTSTS_BCS_FREE){ | |
303 | u8 mdcntl = in_8(&i2c->mdcntl); | |
304 | ||
305 | /* Generate valid stop condition */ | |
306 | out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); | |
307 | out_8(&i2c->directcntl, IIC_DIRCNTL_SCC); | |
308 | udelay(10); | |
309 | out_8(&i2c->directcntl, | |
310 | IIC_DIRCNTL_SCC | IIC_DIRCNTL_SDAC); | |
311 | out_8(&i2c->xtcntlss, 0); | |
312 | ||
313 | ppc4xx_i2c_init(adap, (mdcntl & IIC_MDCNTL_FSM) | |
314 | ? 400000 : 100000, 0); | |
315 | } | |
8bde7f77 WD |
316 | } else if ( status & IIC_STS_PT) { |
317 | result = IIC_NOK_TOUT; | |
318 | } | |
eb5eb2b0 | 319 | |
8bde7f77 WD |
320 | /* Command is reading => get buffer */ |
321 | if ((reading) && (result == IIC_OK)) { | |
322 | /* Are there data in buffer */ | |
323 | if (status & IIC_STS_MDBS) { | |
324 | /* | |
eb5eb2b0 SR |
325 | * even if we have data we have to wait 4OPB |
326 | * clocks for it to hit the front of the FIFO, | |
327 | * after that we can just read. We should check | |
328 | * XFCNT here and if the FIFO is full there is | |
329 | * no need to wait. | |
79b2d0bb SR |
330 | */ |
331 | udelay(1); | |
eb5eb2b0 SR |
332 | for (j = 0; j < bc; j++) |
333 | ptr[tran + j] = in_8(&i2c->mdbuf); | |
8bde7f77 WD |
334 | } else |
335 | result = IIC_NOK_DATA; | |
336 | } | |
337 | creg = 0; | |
79b2d0bb SR |
338 | tran += bc; |
339 | if (ptr == addr && tran == cnt) { | |
8bde7f77 WD |
340 | ptr = data; |
341 | cnt = data_len; | |
342 | tran = 0; | |
343 | reading = cmd_type; | |
8bde7f77 WD |
344 | } |
345 | } | |
eb5eb2b0 | 346 | return result; |
c609719b WD |
347 | } |
348 | ||
880540de | 349 | static int ppc4xx_i2c_probe(struct i2c_adapter *adap, uchar chip) |
c609719b WD |
350 | { |
351 | uchar buf[1]; | |
352 | ||
353 | buf[0] = 0; | |
354 | ||
8bde7f77 WD |
355 | /* |
356 | * What is needed is to send the chip address and verify that the | |
357 | * address was <ACK>ed (i.e. there was a chip at that address which | |
358 | * drove the data line low). | |
359 | */ | |
880540de | 360 | return (_i2c_transfer(adap, 1, chip << 1, 0, 0, buf, 1) != 0); |
c609719b WD |
361 | } |
362 | ||
880540de DE |
363 | static int ppc4xx_i2c_transfer(struct i2c_adapter *adap, uchar chip, uint addr, |
364 | int alen, uchar *buffer, int len, int read) | |
c609719b | 365 | { |
8bde7f77 WD |
366 | uchar xaddr[4]; |
367 | int ret; | |
c609719b | 368 | |
79b2d0bb | 369 | if (alen > 4) { |
eb5eb2b0 | 370 | printf("I2C: addr len %d not supported\n", alen); |
c609719b WD |
371 | return 1; |
372 | } | |
373 | ||
79b2d0bb | 374 | if (alen > 0) { |
8bde7f77 WD |
375 | xaddr[0] = (addr >> 24) & 0xFF; |
376 | xaddr[1] = (addr >> 16) & 0xFF; | |
377 | xaddr[2] = (addr >> 8) & 0xFF; | |
378 | xaddr[3] = addr & 0xFF; | |
379 | } | |
c609719b WD |
380 | |
381 | ||
6d0f6bcf | 382 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
c609719b | 383 | /* |
8bde7f77 WD |
384 | * EEPROM chips that implement "address overflow" are ones |
385 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of | |
386 | * address and the extra bits end up in the "chip address" | |
387 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like | |
388 | * four 256 byte chips. | |
c609719b | 389 | * |
8bde7f77 WD |
390 | * Note that we consider the length of the address field to |
391 | * still be one byte because the extra address bits are | |
392 | * hidden in the chip address. | |
c609719b | 393 | */ |
79b2d0bb | 394 | if (alen > 0) |
eb5eb2b0 SR |
395 | chip |= ((addr >> (alen * 8)) & |
396 | CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); | |
c609719b | 397 | #endif |
880540de DE |
398 | ret = _i2c_transfer(adap, read, chip << 1, &xaddr[4 - alen], alen, |
399 | buffer, len); | |
400 | if (ret) { | |
e3e454cd | 401 | printf("I2C %s: failed %d\n", read ? "read" : "write", ret); |
8bde7f77 WD |
402 | return 1; |
403 | } | |
eb5eb2b0 | 404 | |
8bde7f77 | 405 | return 0; |
c609719b WD |
406 | } |
407 | ||
880540de DE |
408 | static int ppc4xx_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, |
409 | int alen, uchar *buffer, int len) | |
c609719b | 410 | { |
880540de | 411 | return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 1); |
eb5eb2b0 | 412 | } |
c609719b | 413 | |
880540de DE |
414 | static int ppc4xx_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, |
415 | int alen, uchar *buffer, int len) | |
eb5eb2b0 | 416 | { |
880540de | 417 | return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 0); |
c609719b WD |
418 | } |
419 | ||
880540de DE |
420 | static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter *adap, |
421 | unsigned int speed) | |
79b2d0bb | 422 | { |
880540de | 423 | if (speed != adap->speed) |
79b2d0bb | 424 | return -1; |
880540de | 425 | return speed; |
79b2d0bb | 426 | } |
880540de DE |
427 | |
428 | /* | |
429 | * Register ppc4xx i2c adapters | |
430 | */ | |
431 | #ifdef CONFIG_SYS_I2C_PPC4XX_CH0 | |
432 | U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0, ppc4xx_i2c_init, ppc4xx_i2c_probe, | |
433 | ppc4xx_i2c_read, ppc4xx_i2c_write, | |
434 | ppc4xx_i2c_set_bus_speed, | |
435 | CONFIG_SYS_I2C_PPC4XX_SPEED_0, | |
436 | CONFIG_SYS_I2C_PPC4XX_SLAVE_0, 0) | |
437 | #endif | |
438 | #ifdef CONFIG_SYS_I2C_PPC4XX_CH1 | |
439 | U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1, ppc4xx_i2c_init, ppc4xx_i2c_probe, | |
440 | ppc4xx_i2c_read, ppc4xx_i2c_write, | |
441 | ppc4xx_i2c_set_bus_speed, | |
442 | CONFIG_SYS_I2C_PPC4XX_SPEED_1, | |
443 | CONFIG_SYS_I2C_PPC4XX_SLAVE_1, 1) | |
444 | #endif |