[people/ms/u-boot.git] / drivers / i2c / tegra_i2c.c

/*
 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
 * Copyright (c) 2010-2011 NVIDIA Corporation
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/tegra_i2c.h>

DECLARE_GLOBAL_DATA_PTR;

enum i2c_type {
	TYPE_114,
	TYPE_STD,
	TYPE_DVC,
};

/* Information about i2c controller */
struct i2c_bus {
	int			id;
	enum periph_id		periph_id;
	int			speed;
	int			pinmux_config;
	struct i2c_control	*control;
	struct i2c_ctlr		*regs;
	enum i2c_type		type;
	int			inited;	/* bus is inited */
};

static void set_packet_mode(struct i2c_bus *i2c_bus)
{
	u32 config;

	config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;

	if (i2c_bus->type == TYPE_DVC) {
		struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;

		writel(config, &dvc->cnfg);
	} else {
		writel(config, &i2c_bus->regs->cnfg);
		/*
		 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
		 * issues, i.e., some slaves may be wrongly detected.
		 */
		setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
	}
}

static void i2c_reset_controller(struct i2c_bus *i2c_bus)
{
	/* Reset I2C controller. */
	reset_periph(i2c_bus->periph_id, 1);

	/* re-program config register to packet mode */
	set_packet_mode(i2c_bus);
}

static void i2c_init_controller(struct i2c_bus *i2c_bus)
{
	if (!i2c_bus->speed)
		return;
	debug("%s: speed=%d\n", __func__, i2c_bus->speed);
	/*
	 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
	 * here, in section 23.3.1, but in fact we seem to need a factor of
	 * 16 to get the right frequency.
	 */
	clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
		i2c_bus->speed * 2 * 8);

	if (i2c_bus->type == TYPE_114) {
		/*
		 * T114 I2C went to a single clock source for standard/fast and
		 * HS clock speeds. The new clock rate setting calculation is:
		 *  SCL = CLK_SOURCE.I2C /
		 *   (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
		 *   I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
		 *
		 * NOTE: We do this here, after the initial clock/pll start,
		 * because if we read the clk_div reg before the controller
		 * is running, we hang, and we need it for the new calc.
		 */
		int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
		debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
			clk_div_stdfst_mode);

		clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
			CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
			i2c_bus->speed * 2);
	}

	/* Reset I2C controller. */
	i2c_reset_controller(i2c_bus);

	/* Configure I2C controller. */
	if (i2c_bus->type == TYPE_DVC) {	/* only for DVC I2C */
		struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;

		setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
	}

	funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
}

static void send_packet_headers(
	struct i2c_bus *i2c_bus,
	struct i2c_trans_info *trans,
	u32 packet_id,
	bool end_with_repeated_start)
{
	u32 data;

	/* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
	data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
	data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
	data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
	writel(data, &i2c_bus->control->tx_fifo);
	debug("pkt header 1 sent (0x%x)\n", data);

	/* prepare header2 */
	data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
	writel(data, &i2c_bus->control->tx_fifo);
	debug("pkt header 2 sent (0x%x)\n", data);

	/* prepare IO specific header: configure the slave address */
	data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;

	/* Enable Read if it is not a write transaction */
	if (!(trans->flags & I2C_IS_WRITE))
		data |= PKT_HDR3_READ_MODE_MASK;
	if (end_with_repeated_start)
		data |= PKT_HDR3_REPEAT_START_MASK;

	/* Write I2C specific header */
	writel(data, &i2c_bus->control->tx_fifo);
	debug("pkt header 3 sent (0x%x)\n", data);
}

static int wait_for_tx_fifo_empty(struct i2c_control *control)
{
	u32 count;
	int timeout_us = I2C_TIMEOUT_USEC;

	while (timeout_us >= 0) {
		count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
				>> TX_FIFO_EMPTY_CNT_SHIFT;
		if (count == I2C_FIFO_DEPTH)
			return 1;
		udelay(10);
		timeout_us -= 10;
	}

	return 0;
}

static int wait_for_rx_fifo_notempty(struct i2c_control *control)
{
	u32 count;
	int timeout_us = I2C_TIMEOUT_USEC;

	while (timeout_us >= 0) {
		count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
				>> TX_FIFO_FULL_CNT_SHIFT;
		if (count)
			return 1;
		udelay(10);
		timeout_us -= 10;
	}

	return 0;
}

static int wait_for_transfer_complete(struct i2c_control *control)
{
	int int_status;
	int timeout_us = I2C_TIMEOUT_USEC;

	while (timeout_us >= 0) {
		int_status = readl(&control->int_status);
		if (int_status & I2C_INT_NO_ACK_MASK)
			return -int_status;
		if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
			return -int_status;
		if (int_status & I2C_INT_XFER_COMPLETE_MASK)
			return 0;

		udelay(10);
		timeout_us -= 10;
	}

	return -1;
}

static int send_recv_packets(struct i2c_bus *i2c_bus,
			     struct i2c_trans_info *trans)
{
	struct i2c_control *control = i2c_bus->control;
	u32 int_status;
	u32 words;
	u8 *dptr;
	u32 local;
	uchar last_bytes;
	int error = 0;
	int is_write = trans->flags & I2C_IS_WRITE;

	/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
	int_status = readl(&control->int_status);
	writel(int_status, &control->int_status);

	send_packet_headers(i2c_bus, trans, 1,
			    trans->flags & I2C_USE_REPEATED_START);

	words = DIV_ROUND_UP(trans->num_bytes, 4);
	last_bytes = trans->num_bytes & 3;
	dptr = trans->buf;

	while (words) {
		u32 *wptr = (u32 *)dptr;

		if (is_write) {
			/* deal with word alignment */
			if ((words == 1) && last_bytes) {
				local = 0;
				memcpy(&local, dptr, last_bytes);
			} else if ((unsigned long)dptr & 3) {
				memcpy(&local, dptr, sizeof(u32));
			} else {
				local = *wptr;
			}
			writel(local, &control->tx_fifo);
			debug("pkt data sent (0x%x)\n", local);
			if (!wait_for_tx_fifo_empty(control)) {
				error = -1;
				goto exit;
			}
		} else {
			if (!wait_for_rx_fifo_notempty(control)) {
				error = -1;
				goto exit;
			}
			/*
			 * for the last word, we read into our local buffer,
			 * in case that caller did not provide enough buffer.
			 */
			local = readl(&control->rx_fifo);
			if ((words == 1) && last_bytes)
				memcpy(dptr, (char *)&local, last_bytes);
			else if ((unsigned long)dptr & 3)
				memcpy(dptr, &local, sizeof(u32));
			else
				*wptr = local;
			debug("pkt data received (0x%x)\n", local);
		}
		words--;
		dptr += sizeof(u32);
	}

	if (wait_for_transfer_complete(control)) {
		error = -1;
		goto exit;
	}
	return 0;
exit:
	/* error, reset the controller. */
	i2c_reset_controller(i2c_bus);

	return error;
}

static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
				u32 len, bool end_with_repeated_start)
{
	int error;
	struct i2c_trans_info trans_info;

	trans_info.address = addr;
	trans_info.buf = data;
	trans_info.flags = I2C_IS_WRITE;
	if (end_with_repeated_start)
		trans_info.flags |= I2C_USE_REPEATED_START;
	trans_info.num_bytes = len;
	trans_info.is_10bit_address = 0;

	error = send_recv_packets(i2c_bus, &trans_info);
	if (error)
		debug("tegra_i2c_write_data: Error (%d) !!!\n", error);

	return error;
}

static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
			       u32 len)
{
	int error;
	struct i2c_trans_info trans_info;

	trans_info.address = addr | 1;
	trans_info.buf = data;
	trans_info.flags = 0;
	trans_info.num_bytes = len;
	trans_info.is_10bit_address = 0;

	error = send_recv_packets(i2c_bus, &trans_info);
	if (error)
		debug("tegra_i2c_read_data: Error (%d) !!!\n", error);

	return error;
}

static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
	struct i2c_bus *i2c_bus = dev_get_priv(dev);

	i2c_bus->speed = speed;
	i2c_init_controller(i2c_bus);

	return 0;
}

static int tegra_i2c_probe(struct udevice *dev)
{
	struct i2c_bus *i2c_bus = dev_get_priv(dev);
	const void *blob = gd->fdt_blob;
	int node = dev->of_offset;
	bool is_dvc;

	i2c_bus->id = dev->seq;
	i2c_bus->type = dev_get_driver_data(dev);
	i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev);

	/*
	 * We don't have a binding for pinmux yet. Leave it out for now. So
	 * far no one needs anything other than the default.
	 */
	i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
	i2c_bus->periph_id = clock_decode_periph_id(blob, node);

	/*
	 * We can't specify the pinmux config in the fdt, so I2C2 will not
	 * work on Seaboard. It normally has no devices on it anyway.
	 * You could add in this little hack if you need to use it.
	 * The correct solution is a pinmux binding in the fdt.
	 *
	 *	if (i2c_bus->periph_id == PERIPH_ID_I2C2)
	 *		i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
	 */
	if (i2c_bus->periph_id == -1)
		return -EINVAL;

	is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
	if (is_dvc) {
		i2c_bus->control =
			&((struct dvc_ctlr *)i2c_bus->regs)->control;
	} else {
		i2c_bus->control = &i2c_bus->regs->control;
	}
	i2c_init_controller(i2c_bus);
	debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
	      is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs,
	      i2c_bus->periph_id, i2c_bus->speed);

	return 0;
}

/* i2c write version without the register address */
static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
			  int len, bool end_with_repeated_start)
{
	int rc;

	debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
	debug("write_data: ");
	/* use rc for counter */
	for (rc = 0; rc < len; ++rc)
		debug(" 0x%02x", buffer[rc]);
	debug("\n");

	/* Shift 7-bit address over for lower-level i2c functions */
	rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
				  end_with_repeated_start);
	if (rc)
		debug("i2c_write_data(): rc=%d\n", rc);

	return rc;
}

/* i2c read version without the register address */
static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
			 int len)
{
	int rc;

	debug("inside i2c_read_data():\n");
	/* Shift 7-bit address over for lower-level i2c functions */
	rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
	if (rc) {
		debug("i2c_read_data(): rc=%d\n", rc);
		return rc;
	}

	debug("i2c_read_data: ");
	/* reuse rc for counter*/
	for (rc = 0; rc < len; ++rc)
		debug(" 0x%02x", buffer[rc]);
	debug("\n");

	return 0;
}

/* Probe to see if a chip is present. */
static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
				uint chip_flags)
{
	struct i2c_bus *i2c_bus = dev_get_priv(bus);
	int rc;
	u8 reg;

	/* Shift 7-bit address over for lower-level i2c functions */
	rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
				  false);

	return rc;
}

static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
			  int nmsgs)
{
	struct i2c_bus *i2c_bus = dev_get_priv(bus);
	int ret;

	debug("i2c_xfer: %d messages\n", nmsgs);
	for (; nmsgs > 0; nmsgs--, msg++) {
		bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);

		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD) {
			ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
					    msg->len);
		} else {
			ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
					     msg->len, next_is_read);
		}
		if (ret) {
			debug("i2c_write: error sending\n");
			return -EREMOTEIO;
		}
	}

	return 0;
}

int tegra_i2c_get_dvc_bus(struct udevice **busp)
{
	struct udevice *bus;

	for (uclass_first_device(UCLASS_I2C, &bus);
	     bus;
	     uclass_next_device(&bus)) {
		if (dev_get_driver_data(bus) == TYPE_DVC) {
			*busp = bus;
			return 0;
		}
	}

	return -ENODEV;
}

static const struct dm_i2c_ops tegra_i2c_ops = {
	.xfer		= tegra_i2c_xfer,
	.probe_chip	= tegra_i2c_probe_chip,
	.set_bus_speed	= tegra_i2c_set_bus_speed,
};

static const struct udevice_id tegra_i2c_ids[] = {
	{ .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
	{ .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
	{ .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
	{ }
};

U_BOOT_DRIVER(i2c_tegra) = {
	.name	= "i2c_tegra",
	.id	= UCLASS_I2C,
	.of_match = tegra_i2c_ids,
	.probe	= tegra_i2c_probe,
	.priv_auto_alloc_size = sizeof(struct i2c_bus),
	.ops	= &tegra_i2c_ops,
};
Commit	Line	Data
96a78ac0 YL	1	/*
	2	* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
	3	* Copyright (c) 2010-2011 NVIDIA Corporation
	4	* NVIDIA Corporation <www.nvidia.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
96a78ac0 YL	7	*/
	8
	9	#include <common.h>
b0e6ef46 SG	10	#include <dm.h>
b0e6ef46 SG	11	#include <errno.h>
96a78ac0 YL	12	#include <fdtdec.h>
	13	#include <i2c.h>
	14	#include <asm/io.h>
96a78ac0 YL	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/funcmux.h>
	17	#include <asm/arch/gpio.h>
	18	#include <asm/arch/pinmux.h>
150c2493 TW	19	#include <asm/arch-tegra/clk_rst.h>
150c2493 TW	20	#include <asm/arch-tegra/tegra_i2c.h>
96a78ac0 YL	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
b0e6ef46 SG	24	enum i2c_type {
	25	TYPE_114,
	26	TYPE_STD,
	27	TYPE_DVC,
	28	};
	29
96a78ac0 YL	30	/* Information about i2c controller */
	31	struct i2c_bus {
	32	int id;
	33	enum periph_id periph_id;
	34	int speed;
	35	int pinmux_config;
	36	struct i2c_control *control;
	37	struct i2c_ctlr *regs;
b0e6ef46	38	enum i2c_type type;
96a78ac0 YL	39	int inited; /* bus is inited */
	40	};
	41
96a78ac0 YL	42	static void set_packet_mode(struct i2c_bus *i2c_bus)
	43	{
	44	u32 config;
	45
	46	config = I2C_CNFG_NEW_MASTER_FSM_MASK \| I2C_CNFG_PACKET_MODE_MASK;
	47
b0e6ef46	48	if (i2c_bus->type == TYPE_DVC) {
96a78ac0 YL	49	struct dvc_ctlr dvc = (struct dvc_ctlr )i2c_bus->regs;
	50
	51	writel(config, &dvc->cnfg);
	52	} else {
	53	writel(config, &i2c_bus->regs->cnfg);
	54	/*
	55	* program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
	56	* issues, i.e., some slaves may be wrongly detected.
	57	*/
	58	setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
	59	}
	60	}
	61
	62	static void i2c_reset_controller(struct i2c_bus *i2c_bus)
	63	{
	64	/* Reset I2C controller. */
	65	reset_periph(i2c_bus->periph_id, 1);
	66
	67	/* re-program config register to packet mode */
	68	set_packet_mode(i2c_bus);
	69	}
	70
	71	static void i2c_init_controller(struct i2c_bus *i2c_bus)
	72	{
b0e6ef46 SG	73	if (!i2c_bus->speed)
	74	return;
	75	debug("%s: speed=%d\n", __func__, i2c_bus->speed);
96a78ac0 YL	76	/*
	77	* Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
	78	* here, in section 23.3.1, but in fact we seem to need a factor of
	79	* 16 to get the right frequency.
	80	*/
	81	clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
e32624ef TW	82	i2c_bus->speed * 2 * 8);
e32624ef TW	83
b0e6ef46	84	if (i2c_bus->type == TYPE_114) {
e32624ef TW	85	/*
	86	* T114 I2C went to a single clock source for standard/fast and
	87	* HS clock speeds. The new clock rate setting calculation is:
	88	* SCL = CLK_SOURCE.I2C /
	89	* (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
	90	* I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
	91	*
	92	* NOTE: We do this here, after the initial clock/pll start,
	93	* because if we read the clk_div reg before the controller
	94	* is running, we hang, and we need it for the new calc.
	95	*/
	96	int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
	97	debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
	98	clk_div_stdfst_mode);
	99
	100	clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
	101	CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
	102	i2c_bus->speed * 2);
	103	}
96a78ac0 YL	104
	105	/* Reset I2C controller. */
	106	i2c_reset_controller(i2c_bus);
	107
	108	/* Configure I2C controller. */
b0e6ef46	109	if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
96a78ac0 YL	110	struct dvc_ctlr dvc = (struct dvc_ctlr )i2c_bus->regs;
	111
	112	setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
	113	}
	114
	115	funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
	116	}
	117
	118	static void send_packet_headers(
	119	struct i2c_bus *i2c_bus,
	120	struct i2c_trans_info *trans,
68049a08 SW	121	u32 packet_id,
68049a08 SW	122	bool end_with_repeated_start)
96a78ac0 YL	123	{
	124	u32 data;
	125
	126	/* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
	127	data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
	128	data \|= packet_id << PKT_HDR1_PKT_ID_SHIFT;
	129	data \|= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
	130	writel(data, &i2c_bus->control->tx_fifo);
	131	debug("pkt header 1 sent (0x%x)\n", data);
	132
	133	/* prepare header2 */
	134	data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
	135	writel(data, &i2c_bus->control->tx_fifo);
	136	debug("pkt header 2 sent (0x%x)\n", data);
	137
	138	/* prepare IO specific header: configure the slave address */
	139	data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
	140
	141	/* Enable Read if it is not a write transaction */
	142	if (!(trans->flags & I2C_IS_WRITE))
	143	data \|= PKT_HDR3_READ_MODE_MASK;
68049a08 SW	144	if (end_with_repeated_start)
68049a08 SW	145	data \|= PKT_HDR3_REPEAT_START_MASK;
96a78ac0 YL	146
	147	/* Write I2C specific header */
	148	writel(data, &i2c_bus->control->tx_fifo);
	149	debug("pkt header 3 sent (0x%x)\n", data);
	150	}
	151
	152	static int wait_for_tx_fifo_empty(struct i2c_control *control)
	153	{
	154	u32 count;
	155	int timeout_us = I2C_TIMEOUT_USEC;
	156
	157	while (timeout_us >= 0) {
	158	count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
	159	>> TX_FIFO_EMPTY_CNT_SHIFT;
	160	if (count == I2C_FIFO_DEPTH)
	161	return 1;
	162	udelay(10);
	163	timeout_us -= 10;
	164	}
	165
	166	return 0;
	167	}
	168
	169	static int wait_for_rx_fifo_notempty(struct i2c_control *control)
	170	{
	171	u32 count;
	172	int timeout_us = I2C_TIMEOUT_USEC;
	173
	174	while (timeout_us >= 0) {
	175	count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
	176	>> TX_FIFO_FULL_CNT_SHIFT;
	177	if (count)
	178	return 1;
	179	udelay(10);
	180	timeout_us -= 10;
	181	}
	182
	183	return 0;
	184	}
	185
	186	static int wait_for_transfer_complete(struct i2c_control *control)
	187	{
	188	int int_status;
	189	int timeout_us = I2C_TIMEOUT_USEC;
	190
	191	while (timeout_us >= 0) {
	192	int_status = readl(&control->int_status);
	193	if (int_status & I2C_INT_NO_ACK_MASK)
	194	return -int_status;
	195	if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
	196	return -int_status;
	197	if (int_status & I2C_INT_XFER_COMPLETE_MASK)
	198	return 0;
	199
	200	udelay(10);
	201	timeout_us -= 10;
	202	}
	203
	204	return -1;
	205	}
	206
	207	static int send_recv_packets(struct i2c_bus *i2c_bus,
	208	struct i2c_trans_info *trans)
	209	{
210	struct i2c_control *control = i2c_bus->control;
211	u32 int_status;
212	u32 words;
213	u8 *dptr;
214	u32 local;
215	uchar last_bytes;
216	int error = 0;
217	int is_write = trans->flags & I2C_IS_WRITE;
218
219	/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
220	int_status = readl(&control->int_status);
221	writel(int_status, &control->int_status);
222
68049a08 SW	223	send_packet_headers(i2c_bus, trans, 1,
68049a08 SW	224	trans->flags & I2C_USE_REPEATED_START);
96a78ac0 YL	225
	226	words = DIV_ROUND_UP(trans->num_bytes, 4);
	227	last_bytes = trans->num_bytes & 3;
	228	dptr = trans->buf;
	229
	230	while (words) {
	231	u32 wptr = (u32 )dptr;
	232
	233	if (is_write) {
	234	/* deal with word alignment */
981b14f0 SW	235	if ((words == 1) && last_bytes) {
	236	local = 0;
	237	memcpy(&local, dptr, last_bytes);
8e67c5d0	238	} else if ((unsigned long)dptr & 3) {
96a78ac0	239	memcpy(&local, dptr, sizeof(u32));
96a78ac0	240	} else {
981b14f0	241	local = *wptr;
96a78ac0	242	}
981b14f0 SW	243	writel(local, &control->tx_fifo);
981b14f0 SW	244	debug("pkt data sent (0x%x)\n", local);
96a78ac0 YL	245	if (!wait_for_tx_fifo_empty(control)) {
	246	error = -1;
	247	goto exit;
	248	}
	249	} else {
	250	if (!wait_for_rx_fifo_notempty(control)) {
	251	error = -1;
	252	goto exit;
	253	}
	254	/*
	255	* for the last word, we read into our local buffer,
	256	* in case that caller did not provide enough buffer.
	257	*/
	258	local = readl(&control->rx_fifo);
	259	if ((words == 1) && last_bytes)
	260	memcpy(dptr, (char *)&local, last_bytes);
8e67c5d0	261	else if ((unsigned long)dptr & 3)
96a78ac0 YL	262	memcpy(dptr, &local, sizeof(u32));
	263	else
	264	*wptr = local;
	265	debug("pkt data received (0x%x)\n", local);
	266	}
	267	words--;
	268	dptr += sizeof(u32);
	269	}
	270
	271	if (wait_for_transfer_complete(control)) {
	272	error = -1;
	273	goto exit;
	274	}
	275	return 0;
	276	exit:
	277	/* error, reset the controller. */
	278	i2c_reset_controller(i2c_bus);
	279
	280	return error;
	281	}
	282
b0e6ef46	283	static int tegra_i2c_write_data(struct i2c_bus i2c_bus, u32 addr, u8 data,
68049a08	284	u32 len, bool end_with_repeated_start)
96a78ac0 YL	285	{
	286	int error;
	287	struct i2c_trans_info trans_info;
	288
	289	trans_info.address = addr;
	290	trans_info.buf = data;
	291	trans_info.flags = I2C_IS_WRITE;
68049a08 SW	292	if (end_with_repeated_start)
68049a08 SW	293	trans_info.flags \|= I2C_USE_REPEATED_START;
96a78ac0 YL	294	trans_info.num_bytes = len;
	295	trans_info.is_10bit_address = 0;
	296
b0e6ef46	297	error = send_recv_packets(i2c_bus, &trans_info);
96a78ac0	298	if (error)
29f3e3f2	299	debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
96a78ac0 YL	300
	301	return error;
	302	}
	303
b0e6ef46	304	static int tegra_i2c_read_data(struct i2c_bus i2c_bus, u32 addr, u8 data,
d84eb856	305	u32 len)
96a78ac0 YL	306	{
	307	int error;
	308	struct i2c_trans_info trans_info;
	309
	310	trans_info.address = addr \| 1;
	311	trans_info.buf = data;
	312	trans_info.flags = 0;
	313	trans_info.num_bytes = len;
	314	trans_info.is_10bit_address = 0;
	315
b0e6ef46	316	error = send_recv_packets(i2c_bus, &trans_info);
96a78ac0	317	if (error)
29f3e3f2	318	debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
96a78ac0 YL	319
	320	return error;
	321	}
	322
b0e6ef46	323	static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
96a78ac0	324	{
b0e6ef46	325	struct i2c_bus *i2c_bus = dev_get_priv(dev);
d84eb856	326
b0e6ef46 SG	327	i2c_bus->speed = speed;
b0e6ef46 SG	328	i2c_init_controller(i2c_bus);
96a78ac0 YL	329
	330	return 0;
	331	}
	332
b0e6ef46	333	static int tegra_i2c_probe(struct udevice *dev)
96a78ac0	334	{
b0e6ef46 SG	335	struct i2c_bus *i2c_bus = dev_get_priv(dev);
	336	const void *blob = gd->fdt_blob;
	337	int node = dev->of_offset;
	338	bool is_dvc;
	339
	340	i2c_bus->id = dev->seq;
39de8433	341	i2c_bus->type = dev_get_driver_data(dev);
4e9838c1	342	i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev);
96a78ac0 YL	343
	344	/*
	345	* We don't have a binding for pinmux yet. Leave it out for now. So
	346	* far no one needs anything other than the default.
	347	*/
	348	i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
96a78ac0 YL	349	i2c_bus->periph_id = clock_decode_periph_id(blob, node);
	350
	351	/*
	352	* We can't specify the pinmux config in the fdt, so I2C2 will not
	353	* work on Seaboard. It normally has no devices on it anyway.
	354	* You could add in this little hack if you need to use it.
	355	* The correct solution is a pinmux binding in the fdt.
	356	*
	357	* if (i2c_bus->periph_id == PERIPH_ID_I2C2)
	358	* i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
	359	*/
	360	if (i2c_bus->periph_id == -1)
b0e6ef46	361	return -EINVAL;
96a78ac0	362
39de8433	363	is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
b0e6ef46 SG	364	if (is_dvc) {
	365	i2c_bus->control =
	366	&((struct dvc_ctlr *)i2c_bus->regs)->control;
	367	} else {
	368	i2c_bus->control = &i2c_bus->regs->control;
96a78ac0	369	}
b0e6ef46 SG	370	i2c_init_controller(i2c_bus);
	371	debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
	372	is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs,
	373	i2c_bus->periph_id, i2c_bus->speed);
96a78ac0 YL	374
	375	return 0;
	376	}
	377
96a78ac0	378	/* i2c write version without the register address */
b0e6ef46	379	static int i2c_write_data(struct i2c_bus i2c_bus, uchar chip, uchar buffer,
19d7bf3d	380	int len, bool end_with_repeated_start)
96a78ac0 YL	381	{
	382	int rc;
	383
	384	debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
	385	debug("write_data: ");
	386	/* use rc for counter */
	387	for (rc = 0; rc < len; ++rc)
	388	debug(" 0x%02x", buffer[rc]);
	389	debug("\n");
	390
	391	/* Shift 7-bit address over for lower-level i2c functions */
b0e6ef46	392	rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
68049a08	393	end_with_repeated_start);
96a78ac0 YL	394	if (rc)
	395	debug("i2c_write_data(): rc=%d\n", rc);
	396
	397	return rc;
	398	}
	399
	400	/* i2c read version without the register address */
b0e6ef46 SG	401	static int i2c_read_data(struct i2c_bus i2c_bus, uchar chip, uchar buffer,
b0e6ef46 SG	402	int len)
96a78ac0 YL	403	{
	404	int rc;
	405
	406	debug("inside i2c_read_data():\n");
	407	/* Shift 7-bit address over for lower-level i2c functions */
b0e6ef46	408	rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
96a78ac0 YL	409	if (rc) {
	410	debug("i2c_read_data(): rc=%d\n", rc);
	411	return rc;
	412	}
	413
	414	debug("i2c_read_data: ");
	415	/* reuse rc for counter*/
	416	for (rc = 0; rc < len; ++rc)
	417	debug(" 0x%02x", buffer[rc]);
	418	debug("\n");
	419
	420	return 0;
	421	}
	422
	423	/* Probe to see if a chip is present. */
b0e6ef46 SG	424	static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
b0e6ef46 SG	425	uint chip_flags)
96a78ac0	426	{
b0e6ef46	427	struct i2c_bus *i2c_bus = dev_get_priv(bus);
96a78ac0	428	int rc;
b0e6ef46	429	u8 reg;
96a78ac0	430
b0e6ef46 SG	431	/* Shift 7-bit address over for lower-level i2c functions */
	432	rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
	433	false);
	434
	435	return rc;
96a78ac0 YL	436	}
96a78ac0 YL	437
b0e6ef46 SG	438	static int tegra_i2c_xfer(struct udevice bus, struct i2c_msg msg,
b0e6ef46 SG	439	int nmsgs)
96a78ac0	440	{
b0e6ef46 SG	441	struct i2c_bus *i2c_bus = dev_get_priv(bus);
	442	int ret;
	443
	444	debug("i2c_xfer: %d messages\n", nmsgs);
	445	for (; nmsgs > 0; nmsgs--, msg++) {
	446	bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
	447
	448	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	449	if (msg->flags & I2C_M_RD) {
	450	ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
	451	msg->len);
	452	} else {
	453	ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
	454	msg->len, next_is_read);
96a78ac0	455	}
b0e6ef46 SG	456	if (ret) {
	457	debug("i2c_write: error sending\n");
	458	return -EREMOTEIO;
96a78ac0 YL	459	}
	460	}
	461
	462	return 0;
	463	}
	464
b0e6ef46	465	int tegra_i2c_get_dvc_bus(struct udevice **busp)
96a78ac0	466	{
b0e6ef46 SG	467	struct udevice *bus;
	468
	469	for (uclass_first_device(UCLASS_I2C, &bus);
	470	bus;
	471	uclass_next_device(&bus)) {
39de8433	472	if (dev_get_driver_data(bus) == TYPE_DVC) {
b0e6ef46 SG	473	*busp = bus;
b0e6ef46 SG	474	return 0;
96a78ac0 YL	475	}
	476	}
	477
b0e6ef46	478	return -ENODEV;
96a78ac0 YL	479	}
96a78ac0 YL	480
b0e6ef46 SG	481	static const struct dm_i2c_ops tegra_i2c_ops = {
	482	.xfer = tegra_i2c_xfer,
	483	.probe_chip = tegra_i2c_probe_chip,
	484	.set_bus_speed = tegra_i2c_set_bus_speed,
	485	};
e31c1e50	486
b0e6ef46 SG	487	static const struct udevice_id tegra_i2c_ids[] = {
	488	{ .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
	489	{ .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
	490	{ .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
	491	{ }
	492	};
	493
	494	U_BOOT_DRIVER(i2c_tegra) = {
	495	.name = "i2c_tegra",
	496	.id = UCLASS_I2C,
	497	.of_match = tegra_i2c_ids,
b0e6ef46	498	.probe = tegra_i2c_probe,
b0e6ef46 SG	499	.priv_auto_alloc_size = sizeof(struct i2c_bus),
	500	.ops = &tegra_i2c_ops,
	501	};