[people/ms/u-boot.git] / drivers / i2c / zynq_i2c.c

/*
 * Driver for the Zynq-7000 PS I2C controller
 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
 *
 * Author: Joe Hershberger <joe.hershberger@ni.com>
 * Copyright (c) 2012 Joe Hershberger.
 *
 * Copyright (c) 2012-2013 Xilinx, Michal Simek
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * NOTE: This driver should be converted to driver model before June 2017.
 * Please see doc/driver-model/i2c-howto.txt for instructions.
 */

#include <common.h>
#include <asm/io.h>
#include <i2c.h>
#include <linux/errno.h>
#include <asm/arch/hardware.h>

/* i2c register set */
struct zynq_i2c_registers {
	u32 control;
	u32 status;
	u32 address;
	u32 data;
	u32 interrupt_status;
	u32 transfer_size;
	u32 slave_mon_pause;
	u32 time_out;
	u32 interrupt_mask;
	u32 interrupt_enable;
	u32 interrupt_disable;
};

/* Control register fields */
#define ZYNQ_I2C_CONTROL_RW		0x00000001
#define ZYNQ_I2C_CONTROL_MS		0x00000002
#define ZYNQ_I2C_CONTROL_NEA		0x00000004
#define ZYNQ_I2C_CONTROL_ACKEN		0x00000008
#define ZYNQ_I2C_CONTROL_HOLD		0x00000010
#define ZYNQ_I2C_CONTROL_SLVMON		0x00000020
#define ZYNQ_I2C_CONTROL_CLR_FIFO	0x00000040
#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT	8
#define ZYNQ_I2C_CONTROL_DIV_B_MASK	0x00003F00
#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT	14
#define ZYNQ_I2C_CONTROL_DIV_A_MASK	0x0000C000

/* Status register values */
#define ZYNQ_I2C_STATUS_RXDV	0x00000020
#define ZYNQ_I2C_STATUS_TXDV	0x00000040
#define ZYNQ_I2C_STATUS_RXOVF	0x00000080
#define ZYNQ_I2C_STATUS_BA	0x00000100

/* Interrupt register fields */
#define ZYNQ_I2C_INTERRUPT_COMP		0x00000001
#define ZYNQ_I2C_INTERRUPT_DATA		0x00000002
#define ZYNQ_I2C_INTERRUPT_NACK		0x00000004
#define ZYNQ_I2C_INTERRUPT_TO		0x00000008
#define ZYNQ_I2C_INTERRUPT_SLVRDY	0x00000010
#define ZYNQ_I2C_INTERRUPT_RXOVF	0x00000020
#define ZYNQ_I2C_INTERRUPT_TXOVF	0x00000040
#define ZYNQ_I2C_INTERRUPT_RXUNF	0x00000080
#define ZYNQ_I2C_INTERRUPT_ARBLOST	0x00000200

#define ZYNQ_I2C_FIFO_DEPTH		16
#define ZYNQ_I2C_TRANSFERT_SIZE_MAX	255 /* Controller transfer limit */

static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
{
	return adap->hwadapnr ?
		/* Zynq PS I2C1 */
		(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
		/* Zynq PS I2C0 */
		(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
}

/* I2C init called by cmd_i2c when doing 'i2c reset'. */
static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
			  int slaveadd)
{
	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);

	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
	writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
		(2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);

	/* Enable master mode, ack, and 7-bit addressing */
	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
		ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
}

#ifdef DEBUG
static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
{
	int int_status;
	int status;
	int_status = readl(&zynq_i2c->interrupt_status);

	status = readl(&zynq_i2c->status);
	if (int_status || status) {
		debug("Status: ");
		if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
			debug("COMP ");
		if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
			debug("DATA ");
		if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
			debug("NACK ");
		if (int_status & ZYNQ_I2C_INTERRUPT_TO)
			debug("TO ");
		if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
			debug("SLVRDY ");
		if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
			debug("RXOVF ");
		if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
			debug("TXOVF ");
		if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
			debug("RXUNF ");
		if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
			debug("ARBLOST ");
		if (status & ZYNQ_I2C_STATUS_RXDV)
			debug("RXDV ");
		if (status & ZYNQ_I2C_STATUS_TXDV)
			debug("TXDV ");
		if (status & ZYNQ_I2C_STATUS_RXOVF)
			debug("RXOVF ");
		if (status & ZYNQ_I2C_STATUS_BA)
			debug("BA ");
		debug("TS%d ", readl(&zynq_i2c->transfer_size));
		debug("\n");
	}
}
#endif

/* Wait for an interrupt */
static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
{
	int timeout, int_status;

	for (timeout = 0; timeout < 100; timeout++) {
		udelay(100);
		int_status = readl(&zynq_i2c->interrupt_status);
		if (int_status & mask)
			break;
	}
#ifdef DEBUG
	zynq_i2c_debug_status(zynq_i2c);
#endif
	/* Clear interrupt status flags */
	writel(int_status & mask, &zynq_i2c->interrupt_status);

	return int_status & mask;
}

/*
 * I2C probe called by cmd_i2c when doing 'i2c probe'.
 * Begin read, nak data byte, end.
 */
static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);

	/* Attempt to read a byte */
	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
		ZYNQ_I2C_CONTROL_RW);
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	writel(0xFF, &zynq_i2c->interrupt_status);
	writel(dev, &zynq_i2c->address);
	writel(1, &zynq_i2c->transfer_size);

	return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
		ZYNQ_I2C_INTERRUPT_NACK) &
		ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
}

/*
 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 * Begin write, send address byte(s), begin read, receive data bytes, end.
 */
static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
			 int alen, u8 *data, int length)
{
	u32 status;
	u32 i = 0;
	u8 *cur_data = data;
	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);

	/* Check the hardware can handle the requested bytes */
	if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
		return -EINVAL;

	/* Write the register address */
	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
		ZYNQ_I2C_CONTROL_HOLD);
	/*
	 * Temporarily disable restart (by clearing hold)
	 * It doesn't seem to work.
	 */
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	writel(0xFF, &zynq_i2c->interrupt_status);
	if (alen) {
		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
		writel(dev, &zynq_i2c->address);
		while (alen--)
			writel(addr >> (8 * alen), &zynq_i2c->data);

		/* Wait for the address to be sent */
		if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
			/* Release the bus */
			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
			return -ETIMEDOUT;
		}
		debug("Device acked address\n");
	}

	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
		ZYNQ_I2C_CONTROL_RW);
	/* Start reading data */
	writel(dev, &zynq_i2c->address);
	writel(length, &zynq_i2c->transfer_size);

	/* Wait for data */
	do {
		status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
			ZYNQ_I2C_INTERRUPT_DATA);
		if (!status) {
			/* Release the bus */
			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
			return -ETIMEDOUT;
		}
		debug("Read %d bytes\n",
		      length - readl(&zynq_i2c->transfer_size));
		for (; i < length - readl(&zynq_i2c->transfer_size); i++)
			*(cur_data++) = readl(&zynq_i2c->data);
	} while (readl(&zynq_i2c->transfer_size) != 0);
	/* All done... release the bus */
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);

#ifdef DEBUG
	zynq_i2c_debug_status(zynq_i2c);
#endif
	return 0;
}

/*
 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 * Begin write, send address byte(s), send data bytes, end.
 */
static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			  int alen, u8 *data, int length)
{
	u8 *cur_data = data;
	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);

	/* Write the register address */
	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
		ZYNQ_I2C_CONTROL_HOLD);
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
	writel(0xFF, &zynq_i2c->interrupt_status);
	writel(dev, &zynq_i2c->address);
	if (alen) {
		while (alen--)
			writel(addr >> (8 * alen), &zynq_i2c->data);
		/* Start the tranfer */
		if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
			/* Release the bus */
			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
			return -ETIMEDOUT;
		}
		debug("Device acked address\n");
	}

	while (length--) {
		writel(*(cur_data++), &zynq_i2c->data);
		if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
			if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
				/* Release the bus */
				clrbits_le32(&zynq_i2c->control,
					     ZYNQ_I2C_CONTROL_HOLD);
				return -ETIMEDOUT;
			}
		}
	}

	/* All done... release the bus */
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	/* Wait for the address and data to be sent */
	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
		return -ETIMEDOUT;
	return 0;
}

static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
			unsigned int speed)
{
	if (speed != 1000000)
		return -EINVAL;

	return 0;
}

#ifdef CONFIG_ZYNQ_I2C0
U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
			 zynq_i2c_write, zynq_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
			 0)
#endif
#ifdef CONFIG_ZYNQ_I2C1
U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
			 zynq_i2c_write, zynq_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
			 1)
#endif
Commit	Line	Data
8934f784 MS	1	/*
	2	* Driver for the Zynq-7000 PS I2C controller
	3	* IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
	4	*
	5	* Author: Joe Hershberger <joe.hershberger@ni.com>
	6	* Copyright (c) 2012 Joe Hershberger.
	7	*
	8	* Copyright (c) 2012-2013 Xilinx, Michal Simek
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
28527096 SG	11	*
	12	* NOTE: This driver should be converted to driver model before June 2017.
	13	* Please see doc/driver-model/i2c-howto.txt for instructions.
8934f784 MS	14	*/
	15
	16	#include <common.h>
	17	#include <asm/io.h>
	18	#include <i2c.h>
1221ce45	19	#include <linux/errno.h>
8934f784 MS	20	#include <asm/arch/hardware.h>
	21
	22	/* i2c register set */
	23	struct zynq_i2c_registers {
	24	u32 control;
	25	u32 status;
	26	u32 address;
	27	u32 data;
	28	u32 interrupt_status;
	29	u32 transfer_size;
	30	u32 slave_mon_pause;
	31	u32 time_out;
	32	u32 interrupt_mask;
	33	u32 interrupt_enable;
	34	u32 interrupt_disable;
	35	};
	36
	37	/* Control register fields */
	38	#define ZYNQ_I2C_CONTROL_RW 0x00000001
	39	#define ZYNQ_I2C_CONTROL_MS 0x00000002
	40	#define ZYNQ_I2C_CONTROL_NEA 0x00000004
	41	#define ZYNQ_I2C_CONTROL_ACKEN 0x00000008
	42	#define ZYNQ_I2C_CONTROL_HOLD 0x00000010
	43	#define ZYNQ_I2C_CONTROL_SLVMON 0x00000020
	44	#define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040
	45	#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8
	46	#define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00
	47	#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14
	48	#define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000
	49
	50	/* Status register values */
	51	#define ZYNQ_I2C_STATUS_RXDV 0x00000020
	52	#define ZYNQ_I2C_STATUS_TXDV 0x00000040
	53	#define ZYNQ_I2C_STATUS_RXOVF 0x00000080
	54	#define ZYNQ_I2C_STATUS_BA 0x00000100
	55
	56	/* Interrupt register fields */
	57	#define ZYNQ_I2C_INTERRUPT_COMP 0x00000001
	58	#define ZYNQ_I2C_INTERRUPT_DATA 0x00000002
	59	#define ZYNQ_I2C_INTERRUPT_NACK 0x00000004
	60	#define ZYNQ_I2C_INTERRUPT_TO 0x00000008
	61	#define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010
	62	#define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020
	63	#define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040
	64	#define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080
	65	#define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200
	66
	67	#define ZYNQ_I2C_FIFO_DEPTH 16
	68	#define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */
	69
18948632 MB	70	static struct zynq_i2c_registers i2c_select(struct i2c_adapter adap)
	71	{
	72	return adap->hwadapnr ?
	73	/* Zynq PS I2C1 */
	74	(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
	75	/* Zynq PS I2C0 */
	76	(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
	77	}
8934f784 MS	78
8934f784 MS	79	/* I2C init called by cmd_i2c when doing 'i2c reset'. */
0bdffe71 HS	80	static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
0bdffe71 HS	81	int slaveadd)
8934f784	82	{
18948632 MB	83	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
18948632 MB	84
8934f784 MS	85	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
	86	writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) \|
	87	(2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
	88
	89	/* Enable master mode, ack, and 7-bit addressing */
	90	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS \|
	91	ZYNQ_I2C_CONTROL_ACKEN \| ZYNQ_I2C_CONTROL_NEA);
	92	}
	93
	94	#ifdef DEBUG
18948632	95	static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
8934f784 MS	96	{
	97	int int_status;
	98	int status;
	99	int_status = readl(&zynq_i2c->interrupt_status);
	100
	101	status = readl(&zynq_i2c->status);
	102	if (int_status \|\| status) {
	103	debug("Status: ");
	104	if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
	105	debug("COMP ");
	106	if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
	107	debug("DATA ");
	108	if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
	109	debug("NACK ");
	110	if (int_status & ZYNQ_I2C_INTERRUPT_TO)
	111	debug("TO ");
	112	if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
	113	debug("SLVRDY ");
	114	if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
	115	debug("RXOVF ");
	116	if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
	117	debug("TXOVF ");
	118	if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
	119	debug("RXUNF ");
	120	if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
	121	debug("ARBLOST ");
	122	if (status & ZYNQ_I2C_STATUS_RXDV)
	123	debug("RXDV ");
	124	if (status & ZYNQ_I2C_STATUS_TXDV)
	125	debug("TXDV ");
	126	if (status & ZYNQ_I2C_STATUS_RXOVF)
	127	debug("RXOVF ");
	128	if (status & ZYNQ_I2C_STATUS_BA)
	129	debug("BA ");
	130	debug("TS%d ", readl(&zynq_i2c->transfer_size));
	131	debug("\n");
	132	}
	133	}
	134	#endif
	135
	136	/* Wait for an interrupt */
18948632	137	static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
8934f784 MS	138	{
	139	int timeout, int_status;
	140
	141	for (timeout = 0; timeout < 100; timeout++) {
	142	udelay(100);
	143	int_status = readl(&zynq_i2c->interrupt_status);
	144	if (int_status & mask)
	145	break;
	146	}
	147	#ifdef DEBUG
5146fc2b	148	zynq_i2c_debug_status(zynq_i2c);
8934f784 MS	149	#endif
	150	/* Clear interrupt status flags */
	151	writel(int_status & mask, &zynq_i2c->interrupt_status);
	152
	153	return int_status & mask;
	154	}
	155
	156	/*
	157	* I2C probe called by cmd_i2c when doing 'i2c probe'.
	158	* Begin read, nak data byte, end.
	159	*/
0bdffe71	160	static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
8934f784	161	{
18948632 MB	162	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
18948632 MB	163
8934f784 MS	164	/* Attempt to read a byte */
	165	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO \|
	166	ZYNQ_I2C_CONTROL_RW);
	167	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	168	writel(0xFF, &zynq_i2c->interrupt_status);
	169	writel(dev, &zynq_i2c->address);
	170	writel(1, &zynq_i2c->transfer_size);
	171
18948632	172	return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP \|
8934f784 MS	173	ZYNQ_I2C_INTERRUPT_NACK) &
	174	ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
	175	}
	176
	177	/*
	178	* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
	179	* Begin write, send address byte(s), begin read, receive data bytes, end.
	180	*/
0bdffe71 HS	181	static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
0bdffe71 HS	182	int alen, u8 *data, int length)
8934f784 MS	183	{
	184	u32 status;
	185	u32 i = 0;
	186	u8 *cur_data = data;
18948632	187	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
8934f784 MS	188
	189	/* Check the hardware can handle the requested bytes */
	190	if ((length < 0) \|\| (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
	191	return -EINVAL;
	192
	193	/* Write the register address */
	194	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO \|
	195	ZYNQ_I2C_CONTROL_HOLD);
	196	/*
	197	* Temporarily disable restart (by clearing hold)
	198	* It doesn't seem to work.
	199	*/
9e901071	200	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
8934f784	201	writel(0xFF, &zynq_i2c->interrupt_status);
9e901071 MB	202	if (alen) {
	203	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
	204	writel(dev, &zynq_i2c->address);
	205	while (alen--)
	206	writel(addr >> (8 * alen), &zynq_i2c->data);
8934f784	207
9e901071	208	/* Wait for the address to be sent */
18948632	209	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
9e901071 MB	210	/* Release the bus */
	211	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	212	return -ETIMEDOUT;
	213	}
	214	debug("Device acked address\n");
8934f784	215	}
8934f784 MS	216
	217	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO \|
	218	ZYNQ_I2C_CONTROL_RW);
	219	/* Start reading data */
	220	writel(dev, &zynq_i2c->address);
	221	writel(length, &zynq_i2c->transfer_size);
	222
	223	/* Wait for data */
	224	do {
18948632	225	status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP \|
8934f784 MS	226	ZYNQ_I2C_INTERRUPT_DATA);
	227	if (!status) {
	228	/* Release the bus */
	229	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	230	return -ETIMEDOUT;
	231	}
	232	debug("Read %d bytes\n",
	233	length - readl(&zynq_i2c->transfer_size));
	234	for (; i < length - readl(&zynq_i2c->transfer_size); i++)
	235	*(cur_data++) = readl(&zynq_i2c->data);
	236	} while (readl(&zynq_i2c->transfer_size) != 0);
	237	/* All done... release the bus */
	238	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	239
	240	#ifdef DEBUG
5146fc2b	241	zynq_i2c_debug_status(zynq_i2c);
8934f784 MS	242	#endif
	243	return 0;
	244	}
	245
	246	/*
	247	* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
	248	* Begin write, send address byte(s), send data bytes, end.
	249	*/
0bdffe71 HS	250	static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
0bdffe71 HS	251	int alen, u8 *data, int length)
8934f784 MS	252	{
8934f784 MS	253	u8 *cur_data = data;
18948632	254	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
8934f784 MS	255
	256	/* Write the register address */
	257	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO \|
	258	ZYNQ_I2C_CONTROL_HOLD);
	259	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
	260	writel(0xFF, &zynq_i2c->interrupt_status);
8934f784	261	writel(dev, &zynq_i2c->address);
9e901071 MB	262	if (alen) {
	263	while (alen--)
	264	writel(addr >> (8 * alen), &zynq_i2c->data);
	265	/* Start the tranfer */
18948632	266	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
9e901071 MB	267	/* Release the bus */
	268	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	269	return -ETIMEDOUT;
	270	}
	271	debug("Device acked address\n");
8934f784 MS	272	}
8934f784 MS	273
8934f784 MS	274	while (length--) {
	275	writel(*(cur_data++), &zynq_i2c->data);
	276	if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
18948632	277	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
8934f784 MS	278	/* Release the bus */
	279	clrbits_le32(&zynq_i2c->control,
	280	ZYNQ_I2C_CONTROL_HOLD);
	281	return -ETIMEDOUT;
	282	}
	283	}
	284	}
	285
	286	/* All done... release the bus */
	287	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	288	/* Wait for the address and data to be sent */
18948632	289	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
8934f784 MS	290	return -ETIMEDOUT;
	291	return 0;
	292	}
	293
0bdffe71 HS	294	static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
0bdffe71 HS	295	unsigned int speed)
8934f784	296	{
0bdffe71 HS	297	if (speed != 1000000)
0bdffe71 HS	298	return -EINVAL;
8934f784	299
8934f784 MS	300	return 0;
8934f784 MS	301	}
0bdffe71	302
009902a8	303	#ifdef CONFIG_ZYNQ_I2C0
0bdffe71 HS	304	U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
	305	zynq_i2c_write, zynq_i2c_set_bus_speed,
	306	CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
	307	0)
009902a8 MS	308	#endif
009902a8 MS	309	#ifdef CONFIG_ZYNQ_I2C1
18948632 MB	310	U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
	311	zynq_i2c_write, zynq_i2c_set_bus_speed,
	312	CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
	313	1)
009902a8	314	#endif