[people/ms/u-boot.git] / drivers / mmc / exynos_dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <jh80.chung@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dwmmc.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <errno.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/gpio.h>

#define	DWMMC_MAX_CH_NUM		4
#define	DWMMC_MAX_FREQ			52000000
#define	DWMMC_MIN_FREQ			400000
#define	DWMMC_MMC0_SDR_TIMING_VAL	0x03030001
#define	DWMMC_MMC2_SDR_TIMING_VAL	0x03020001

#ifdef CONFIG_DM_MMC
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;

struct exynos_mmc_plat {
	struct mmc_config cfg;
	struct mmc mmc;
};
#endif

/* Exynos implmentation specific drver private data */
struct dwmci_exynos_priv_data {
#ifdef CONFIG_DM_MMC
	struct dwmci_host host;
#endif
	u32 sdr_timing;
};

/*
 * Function used as callback function to initialise the
 * CLKSEL register for every mmc channel.
 */
static void exynos_dwmci_clksel(struct dwmci_host *host)
{
	struct dwmci_exynos_priv_data *priv = host->priv;

	dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
}

unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
{
	unsigned long sclk;
	int8_t clk_div;

	/*
	 * Since SDCLKIN is divided inside controller by the DIVRATIO
	 * value set in the CLKSEL register, we need to use the same output
	 * clock value to calculate the CLKDIV value.
	 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
	 */
	clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
			& DWMCI_DIVRATIO_MASK) + 1;
	sclk = get_mmc_clk(host->dev_index);

	/*
	 * Assume to know divider value.
	 * When clock unit is broken, need to set "host->div"
	 */
	return sclk / clk_div / (host->div + 1);
}

static void exynos_dwmci_board_init(struct dwmci_host *host)
{
	struct dwmci_exynos_priv_data *priv = host->priv;

	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
		dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
		dwmci_writel(host, EMMCP_SEND0, 0);
		dwmci_writel(host, EMMCP_CTRL0,
			     MPSCTRL_SECURE_READ_BIT |
			     MPSCTRL_SECURE_WRITE_BIT |
			     MPSCTRL_NON_SECURE_READ_BIT |
			     MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
	}

	/* Set to timing value at initial time */
	if (priv->sdr_timing)
		exynos_dwmci_clksel(host);
}

static int exynos_dwmci_core_init(struct dwmci_host *host)
{
	unsigned int div;
	unsigned long freq, sclk;

	if (host->bus_hz)
		freq = host->bus_hz;
	else
		freq = DWMMC_MAX_FREQ;

	/* request mmc clock vlaue of 52MHz.  */
	sclk = get_mmc_clk(host->dev_index);
	div = DIV_ROUND_UP(sclk, freq);
	/* set the clock divisor for mmc */
	set_mmc_clk(host->dev_index, div);

	host->name = "EXYNOS DWMMC";
#ifdef CONFIG_EXYNOS5420
	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
#endif
	host->board_init = exynos_dwmci_board_init;

	host->caps = MMC_MODE_DDR_52MHz;
	host->clksel = exynos_dwmci_clksel;
	host->get_mmc_clk = exynos_dwmci_get_clk;

#ifndef CONFIG_DM_MMC
	/* Add the mmc channel to be registered with mmc core */
	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
		printf("DWMMC%d registration failed\n", host->dev_index);
		return -1;
	}
#endif

	return 0;
}

static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];

static int do_dwmci_init(struct dwmci_host *host)
{
	int flag, err;

	flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
	err = exynos_pinmux_config(host->dev_id, flag);
	if (err) {
		printf("DWMMC%d not configure\n", host->dev_index);
		return err;
	}

	return exynos_dwmci_core_init(host);
}

static int exynos_dwmci_get_config(const void *blob, int node,
					struct dwmci_host *host)
{
	int err = 0;
	u32 base, timing[3];
	struct dwmci_exynos_priv_data *priv;

	priv = malloc(sizeof(struct dwmci_exynos_priv_data));
	if (!priv) {
		pr_err("dwmci_exynos_priv_data malloc fail!\n");
		return -ENOMEM;
	}

	/* Extract device id for each mmc channel */
	host->dev_id = pinmux_decode_periph_id(blob, node);

	host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
	if (host->dev_index == host->dev_id)
		host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;

	if (host->dev_index > 4) {
		printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
		free(priv);
		return -EINVAL;
	}

	/* Get the bus width from the device node (Default is 4bit buswidth) */
	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);

	/* Set the base address from the device node */
	base = fdtdec_get_addr(blob, node, "reg");
	if (!base) {
		printf("DWMMC%d: Can't get base address\n", host->dev_index);
		free(priv);
		return -EINVAL;
	}
	host->ioaddr = (void *)base;

	/* Extract the timing info from the node */
	err =  fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
	if (err) {
		printf("DWMMC%d: Can't get sdr-timings for devider\n",
				host->dev_index);
		free(priv);
		return -EINVAL;
	}

	priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
			DWMCI_SET_DRV_CLK(timing[1]) |
			DWMCI_SET_DIV_RATIO(timing[2]));

	/* sdr_timing didn't assigned anything, use the default value */
	if (!priv->sdr_timing) {
		if (host->dev_index == 0)
			priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
		else if (host->dev_index == 2)
			priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
	}

	host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
	host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
	host->div = fdtdec_get_int(blob, node, "div", 0);

	host->priv = priv;

	return 0;
}

static int exynos_dwmci_process_node(const void *blob,
					int node_list[], int count)
{
	struct dwmci_host *host;
	int i, node, err;

	for (i = 0; i < count; i++) {
		node = node_list[i];
		if (node <= 0)
			continue;
		host = &dwmci_host[i];
		err = exynos_dwmci_get_config(blob, node, host);
		if (err) {
			printf("%s: failed to decode dev %d\n", __func__, i);
			return err;
		}

		do_dwmci_init(host);
	}
	return 0;
}

int exynos_dwmmc_init(const void *blob)
{
	int node_list[DWMMC_MAX_CH_NUM];
	int boot_dev_node;
	int err = 0, count;

	count = fdtdec_find_aliases_for_id(blob, "mmc",
			COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list,
			DWMMC_MAX_CH_NUM);

	/* For DWMMC always set boot device as mmc 0 */
	if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
		boot_dev_node = node_list[2];
		node_list[2] = node_list[0];
		node_list[0] = boot_dev_node;
	}

	err = exynos_dwmci_process_node(blob, node_list, count);

	return err;
}

#ifdef CONFIG_DM_MMC
static int exynos_dwmmc_probe(struct udevice *dev)
{
	struct exynos_mmc_plat *plat = dev_get_platdata(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
	struct dwmci_host *host = &priv->host;
	int err;

	err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
	if (err)
		return err;
	err = do_dwmci_init(host);
	if (err)
		return err;

	dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
	host->mmc = &plat->mmc;
	host->mmc->priv = &priv->host;
	host->priv = dev;
	upriv->mmc = host->mmc;

	return dwmci_probe(dev);
}

static int exynos_dwmmc_bind(struct udevice *dev)
{
	struct exynos_mmc_plat *plat = dev_get_platdata(dev);

	return dwmci_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id exynos_dwmmc_ids[] = {
	{ .compatible = "samsung,exynos4412-dw-mshc" },
	{ }
};

U_BOOT_DRIVER(exynos_dwmmc_drv) = {
	.name		= "exynos_dwmmc",
	.id		= UCLASS_MMC,
	.of_match	= exynos_dwmmc_ids,
	.bind		= exynos_dwmmc_bind,
	.ops		= &dm_dwmci_ops,
	.probe		= exynos_dwmmc_probe,
	.priv_auto_alloc_size	= sizeof(struct dwmci_exynos_priv_data),
	.platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat),
};
#endif
Commit	Line	Data
d0ebbb8d JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <jh80.chung@samsung.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
d0ebbb8d JC	6	*/
	7
	8	#include <common.h>
d0ebbb8d	9	#include <dwmmc.h>
a082a2dd A	10	#include <fdtdec.h>
	11	#include <libfdt.h>
	12	#include <malloc.h>
ccd60a85	13	#include <errno.h>
d0ebbb8d JC	14	#include <asm/arch/dwmmc.h>
d0ebbb8d JC	15	#include <asm/arch/clk.h>
a082a2dd	16	#include <asm/arch/pinmux.h>
64029f7a	17	#include <asm/arch/power.h>
959198f7	18	#include <asm/gpio.h>
d0ebbb8d	19
a082a2dd A	20	#define DWMMC_MAX_CH_NUM 4
	21	#define DWMMC_MAX_FREQ 52000000
	22	#define DWMMC_MIN_FREQ 400000
5dab81ce JC	23	#define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
	24	#define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
	25
3537ee87 JC	26	#ifdef CONFIG_DM_MMC
	27	#include <dm.h>
	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	struct exynos_mmc_plat {
	31	struct mmc_config cfg;
	32	struct mmc mmc;
	33	};
	34	#endif
	35
5dab81ce JC	36	/* Exynos implmentation specific drver private data */
5dab81ce JC	37	struct dwmci_exynos_priv_data {
3537ee87 JC	38	#ifdef CONFIG_DM_MMC
	39	struct dwmci_host host;
	40	#endif
5dab81ce JC	41	u32 sdr_timing;
5dab81ce JC	42	};
d0ebbb8d	43
a082a2dd A	44	/*
	45	* Function used as callback function to initialise the
	46	* CLKSEL register for every mmc channel.
	47	*/
d0ebbb8d JC	48	static void exynos_dwmci_clksel(struct dwmci_host *host)
d0ebbb8d JC	49	{
5dab81ce JC	50	struct dwmci_exynos_priv_data *priv = host->priv;
	51
	52	dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
a082a2dd	53	}
d0ebbb8d	54
e3563f2e	55	unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
a082a2dd	56	{
d3e016cc RS	57	unsigned long sclk;
	58	int8_t clk_div;
	59
	60	/*
	61	* Since SDCLKIN is divided inside controller by the DIVRATIO
	62	* value set in the CLKSEL register, we need to use the same output
	63	* clock value to calculate the CLKDIV value.
	64	* as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
	65	*/
	66	clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
	67	& DWMCI_DIVRATIO_MASK) + 1;
	68	sclk = get_mmc_clk(host->dev_index);
	69
959198f7 JC	70	/*
	71	* Assume to know divider value.
	72	* When clock unit is broken, need to set "host->div"
	73	*/
	74	return sclk / clk_div / (host->div + 1);
d0ebbb8d JC	75	}
d0ebbb8d JC	76
18ab6755 JC	77	static void exynos_dwmci_board_init(struct dwmci_host *host)
18ab6755 JC	78	{
5dab81ce JC	79	struct dwmci_exynos_priv_data *priv = host->priv;
5dab81ce JC	80
18ab6755 JC	81	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
	82	dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
	83	dwmci_writel(host, EMMCP_SEND0, 0);
	84	dwmci_writel(host, EMMCP_CTRL0,
	85	MPSCTRL_SECURE_READ_BIT \|
	86	MPSCTRL_SECURE_WRITE_BIT \|
	87	MPSCTRL_NON_SECURE_READ_BIT \|
	88	MPSCTRL_NON_SECURE_WRITE_BIT \| MPSCTRL_VALID);
	89	}
3a33bb18	90
5dab81ce JC	91	/* Set to timing value at initial time */
5dab81ce JC	92	if (priv->sdr_timing)
3a33bb18	93	exynos_dwmci_clksel(host);
18ab6755 JC	94	}
18ab6755 JC	95
d956a67e	96	static int exynos_dwmci_core_init(struct dwmci_host *host)
d0ebbb8d	97	{
a082a2dd A	98	unsigned int div;
a082a2dd A	99	unsigned long freq, sclk;
959198f7 JC	100
	101	if (host->bus_hz)
	102	freq = host->bus_hz;
	103	else
	104	freq = DWMMC_MAX_FREQ;
	105
a082a2dd	106	/* request mmc clock vlaue of 52MHz. */
d956a67e	107	sclk = get_mmc_clk(host->dev_index);
a082a2dd A	108	div = DIV_ROUND_UP(sclk, freq);
a082a2dd A	109	/* set the clock divisor for mmc */
d956a67e	110	set_mmc_clk(host->dev_index, div);
d0ebbb8d	111
a082a2dd	112	host->name = "EXYNOS DWMMC";
6f0b7caa RS	113	#ifdef CONFIG_EXYNOS5420
	114	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
	115	#endif
18ab6755	116	host->board_init = exynos_dwmci_board_init;
a082a2dd	117
e09bd853	118	host->caps = MMC_MODE_DDR_52MHz;
d0ebbb8d	119	host->clksel = exynos_dwmci_clksel;
b44fe83a	120	host->get_mmc_clk = exynos_dwmci_get_clk;
3537ee87 JC	121
3537ee87 JC	122	#ifndef CONFIG_DM_MMC
a082a2dd A	123	/* Add the mmc channel to be registered with mmc core */
a082a2dd A	124	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
d956a67e	125	printf("DWMMC%d registration failed\n", host->dev_index);
a082a2dd A	126	return -1;
a082a2dd A	127	}
3537ee87 JC	128	#endif
3537ee87 JC	129
a082a2dd A	130	return 0;
	131	}
	132
959198f7 JC	133	static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
	134
	135	static int do_dwmci_init(struct dwmci_host *host)
a082a2dd	136	{
d956a67e	137	int flag, err;
a082a2dd	138
959198f7 JC	139	flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
	140	err = exynos_pinmux_config(host->dev_id, flag);
	141	if (err) {
d956a67e	142	printf("DWMMC%d not configure\n", host->dev_index);
959198f7 JC	143	return err;
959198f7 JC	144	}
a082a2dd	145
d956a67e	146	return exynos_dwmci_core_init(host);
959198f7	147	}
d0ebbb8d	148
959198f7 JC	149	static int exynos_dwmci_get_config(const void *blob, int node,
	150	struct dwmci_host *host)
	151	{
	152	int err = 0;
5dab81ce JC	153	u32 base, timing[3];
	154	struct dwmci_exynos_priv_data *priv;
	155
	156	priv = malloc(sizeof(struct dwmci_exynos_priv_data));
	157	if (!priv) {
9b643e31	158	pr_err("dwmci_exynos_priv_data malloc fail!\n");
5dab81ce JC	159	return -ENOMEM;
5dab81ce JC	160	}
d0ebbb8d	161
959198f7 JC	162	/* Extract device id for each mmc channel */
959198f7 JC	163	host->dev_id = pinmux_decode_periph_id(blob, node);
a082a2dd	164
dfcb683a JC	165	host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
	166	if (host->dev_index == host->dev_id)
	167	host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
	168
ce757b18 JC	169	if (host->dev_index > 4) {
ce757b18 JC	170	printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
0e1746ac	171	free(priv);
ce757b18 JC	172	return -EINVAL;
	173	}
	174
70f6d394 JC	175	/* Get the bus width from the device node (Default is 4bit buswidth) */
70f6d394 JC	176	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
a082a2dd	177
959198f7 JC	178	/* Set the base address from the device node */
	179	base = fdtdec_get_addr(blob, node, "reg");
	180	if (!base) {
dfcb683a	181	printf("DWMMC%d: Can't get base address\n", host->dev_index);
0e1746ac	182	free(priv);
959198f7 JC	183	return -EINVAL;
	184	}
	185	host->ioaddr = (void *)base;
	186
	187	/* Extract the timing info from the node */
	188	err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
	189	if (err) {
dfcb683a JC	190	printf("DWMMC%d: Can't get sdr-timings for devider\n",
dfcb683a JC	191	host->dev_index);
0e1746ac	192	free(priv);
959198f7 JC	193	return -EINVAL;
	194	}
	195
5dab81ce	196	priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) \|
959198f7 JC	197	DWMCI_SET_DRV_CLK(timing[1]) \|
959198f7 JC	198	DWMCI_SET_DIV_RATIO(timing[2]));
5dab81ce JC	199
	200	/* sdr_timing didn't assigned anything, use the default value */
	201	if (!priv->sdr_timing) {
	202	if (host->dev_index == 0)
	203	priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
	204	else if (host->dev_index == 2)
	205	priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
	206	}
959198f7 JC	207
	208	host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
	209	host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
	210	host->div = fdtdec_get_int(blob, node, "div", 0);
	211
5dab81ce JC	212	host->priv = priv;
5dab81ce JC	213
959198f7 JC	214	return 0;
	215	}
	216
	217	static int exynos_dwmci_process_node(const void *blob,
	218	int node_list[], int count)
	219	{
	220	struct dwmci_host *host;
	221	int i, node, err;
	222
	223	for (i = 0; i < count; i++) {
	224	node = node_list[i];
	225	if (node <= 0)
	226	continue;
	227	host = &dwmci_host[i];
	228	err = exynos_dwmci_get_config(blob, node, host);
a082a2dd	229	if (err) {
dfcb683a	230	printf("%s: failed to decode dev %d\n", __func__, i);
959198f7	231	return err;
a082a2dd A	232	}
a082a2dd A	233
959198f7	234	do_dwmci_init(host);
a082a2dd	235	}
d0ebbb8d JC	236	return 0;
d0ebbb8d JC	237	}
959198f7 JC	238
	239	int exynos_dwmmc_init(const void *blob)
	240	{
959198f7	241	int node_list[DWMMC_MAX_CH_NUM];
64029f7a	242	int boot_dev_node;
959198f7 JC	243	int err = 0, count;
959198f7 JC	244
959198f7	245	count = fdtdec_find_aliases_for_id(blob, "mmc",
d956a67e JC	246	COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list,
d956a67e JC	247	DWMMC_MAX_CH_NUM);
64029f7a PM	248
	249	/* For DWMMC always set boot device as mmc 0 */
	250	if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
	251	boot_dev_node = node_list[2];
	252	node_list[2] = node_list[0];
	253	node_list[0] = boot_dev_node;
	254	}
	255
959198f7 JC	256	err = exynos_dwmci_process_node(blob, node_list, count);
	257
	258	return err;
	259	}
3537ee87 JC	260
	261	#ifdef CONFIG_DM_MMC
	262	static int exynos_dwmmc_probe(struct udevice *dev)
	263	{
	264	struct exynos_mmc_plat *plat = dev_get_platdata(dev);
	265	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	266	struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
	267	struct dwmci_host *host = &priv->host;
	268	int err;
	269
e160f7d4	270	err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
3537ee87 JC	271	if (err)
	272	return err;
	273	err = do_dwmci_init(host);
	274	if (err)
	275	return err;
	276
e5113c33	277	dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
3537ee87 JC	278	host->mmc = &plat->mmc;
	279	host->mmc->priv = &priv->host;
	280	host->priv = dev;
	281	upriv->mmc = host->mmc;
	282
	283	return dwmci_probe(dev);
	284	}
	285
	286	static int exynos_dwmmc_bind(struct udevice *dev)
	287	{
	288	struct exynos_mmc_plat *plat = dev_get_platdata(dev);
3537ee87	289
24f5aec3	290	return dwmci_bind(dev, &plat->mmc, &plat->cfg);
3537ee87 JC	291	}
	292
	293	static const struct udevice_id exynos_dwmmc_ids[] = {
	294	{ .compatible = "samsung,exynos4412-dw-mshc" },
	295	{ }
	296	};
	297
	298	U_BOOT_DRIVER(exynos_dwmmc_drv) = {
	299	.name = "exynos_dwmmc",
	300	.id = UCLASS_MMC,
	301	.of_match = exynos_dwmmc_ids,
	302	.bind = exynos_dwmmc_bind,
	303	.ops = &dm_dwmci_ops,
	304	.probe = exynos_dwmmc_probe,
	305	.priv_auto_alloc_size = sizeof(struct dwmci_exynos_priv_data),
	306	.platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat),
	307	};
	308	#endif