drivers/mmc/exynos_dw_mmc.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dwmmc.h>
  10 #include <fdtdec.h>
  11 #include <libfdt.h>
  12 #include <malloc.h>
  13 #include <errno.h>
  14 #include <asm/arch/dwmmc.h>
  15 #include <asm/arch/clk.h>
  16 #include <asm/arch/pinmux.h>
  17 #include <asm/arch/power.h>
  18 #include <asm/gpio.h>
  19
  20 #define DWMMC_MAX_CH_NUM                4
  21 #define DWMMC_MAX_FREQ                  52000000
  22 #define DWMMC_MIN_FREQ                  400000
  23 #define DWMMC_MMC0_SDR_TIMING_VAL       0x03030001
  24 #define DWMMC_MMC2_SDR_TIMING_VAL       0x03020001
  25
  26 #ifdef CONFIG_DM_MMC
  27 #include <dm.h>
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 struct exynos_mmc_plat {
  31         struct mmc_config cfg;
  32         struct mmc mmc;
  33 };
  34 #endif
  35
  36 /* Exynos implmentation specific drver private data */
  37 struct dwmci_exynos_priv_data {
  38 #ifdef CONFIG_DM_MMC
  39         struct dwmci_host host;
  40 #endif
  41         u32 sdr_timing;
  42 };
  43
  44 /*
  45  * Function used as callback function to initialise the
  46  * CLKSEL register for every mmc channel.
  47  */
  48 static void exynos_dwmci_clksel(struct dwmci_host *host)
  49 {
  50         struct dwmci_exynos_priv_data *priv = host->priv;
  51
  52         dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
  53 }
  54
  55 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
  56 {
  57         unsigned long sclk;
  58         int8_t clk_div;
  59
  60         /*
  61          * Since SDCLKIN is divided inside controller by the DIVRATIO
  62          * value set in the CLKSEL register, we need to use the same output
  63          * clock value to calculate the CLKDIV value.
  64          * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
  65          */
  66         clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
  67                         & DWMCI_DIVRATIO_MASK) + 1;
  68         sclk = get_mmc_clk(host->dev_index);
  69
  70         /*
  71          * Assume to know divider value.
  72          * When clock unit is broken, need to set "host->div"
  73          */
  74         return sclk / clk_div / (host->div + 1);
  75 }
  76
  77 static void exynos_dwmci_board_init(struct dwmci_host *host)
  78 {
  79         struct dwmci_exynos_priv_data *priv = host->priv;
  80
  81         if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
  82                 dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
  83                 dwmci_writel(host, EMMCP_SEND0, 0);
  84                 dwmci_writel(host, EMMCP_CTRL0,
  85                              MPSCTRL_SECURE_READ_BIT |
  86                              MPSCTRL_SECURE_WRITE_BIT |
  87                              MPSCTRL_NON_SECURE_READ_BIT |
  88                              MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
  89         }
  90
  91         /* Set to timing value at initial time */
  92         if (priv->sdr_timing)
  93                 exynos_dwmci_clksel(host);
  94 }
  95
  96 static int exynos_dwmci_core_init(struct dwmci_host *host)
  97 {
  98         unsigned int div;
  99         unsigned long freq, sclk;
 100
 101         if (host->bus_hz)
 102                 freq = host->bus_hz;
 103         else
 104                 freq = DWMMC_MAX_FREQ;
 105
 106         /* request mmc clock vlaue of 52MHz.  */
 107         sclk = get_mmc_clk(host->dev_index);
 108         div = DIV_ROUND_UP(sclk, freq);
 109         /* set the clock divisor for mmc */
 110         set_mmc_clk(host->dev_index, div);
 111
 112         host->name = "EXYNOS DWMMC";
 113 #ifdef CONFIG_EXYNOS5420
 114         host->quirks = DWMCI_QUIRK_DISABLE_SMU;
 115 #endif
 116         host->board_init = exynos_dwmci_board_init;
 117
 118         host->caps = MMC_MODE_DDR_52MHz;
 119         host->clksel = exynos_dwmci_clksel;
 120         host->get_mmc_clk = exynos_dwmci_get_clk;
 121
 122 #ifndef CONFIG_DM_MMC
 123         /* Add the mmc channel to be registered with mmc core */
 124         if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
 125                 printf("DWMMC%d registration failed\n", host->dev_index);
 126                 return -1;
 127         }
 128 #endif
 129
 130         return 0;
 131 }
 132
 133 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
 134
 135 static int do_dwmci_init(struct dwmci_host *host)
 136 {
 137         int flag, err;
 138
 139         flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
 140         err = exynos_pinmux_config(host->dev_id, flag);
 141         if (err) {
 142                 printf("DWMMC%d not configure\n", host->dev_index);
 143                 return err;
 144         }
 145
 146         return exynos_dwmci_core_init(host);
 147 }
 148
 149 static int exynos_dwmci_get_config(const void *blob, int node,
 150                                         struct dwmci_host *host)
 151 {
 152         int err = 0;
 153         u32 base, timing[3];
 154         struct dwmci_exynos_priv_data *priv;
 155
 156         priv = malloc(sizeof(struct dwmci_exynos_priv_data));
 157         if (!priv) {
 158                 pr_err("dwmci_exynos_priv_data malloc fail!\n");
 159                 return -ENOMEM;
 160         }
 161
 162         /* Extract device id for each mmc channel */
 163         host->dev_id = pinmux_decode_periph_id(blob, node);
 164
 165         host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
 166         if (host->dev_index == host->dev_id)
 167                 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
 168
 169         if (host->dev_index > 4) {
 170                 printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
 171                 free(priv);
 172                 return -EINVAL;
 173         }
 174
 175         /* Get the bus width from the device node (Default is 4bit buswidth) */
 176         host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
 177
 178         /* Set the base address from the device node */
 179         base = fdtdec_get_addr(blob, node, "reg");
 180         if (!base) {
 181                 printf("DWMMC%d: Can't get base address\n", host->dev_index);
 182                 free(priv);
 183                 return -EINVAL;
 184         }
 185         host->ioaddr = (void *)base;
 186
 187         /* Extract the timing info from the node */
 188         err =  fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
 189         if (err) {
 190                 printf("DWMMC%d: Can't get sdr-timings for devider\n",
 191                                 host->dev_index);
 192                 free(priv);
 193                 return -EINVAL;
 194         }
 195
 196         priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
 197                         DWMCI_SET_DRV_CLK(timing[1]) |
 198                         DWMCI_SET_DIV_RATIO(timing[2]));
 199
 200         /* sdr_timing didn't assigned anything, use the default value */
 201         if (!priv->sdr_timing) {
 202                 if (host->dev_index == 0)
 203                         priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
 204                 else if (host->dev_index == 2)
 205                         priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
 206         }
 207
 208         host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
 209         host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
 210         host->div = fdtdec_get_int(blob, node, "div", 0);
 211
 212         host->priv = priv;
 213
 214         return 0;
 215 }
 216
 217 static int exynos_dwmci_process_node(const void *blob,
 218                                         int node_list[], int count)
 219 {
 220         struct dwmci_host *host;
 221         int i, node, err;
 222
 223         for (i = 0; i < count; i++) {
 224                 node = node_list[i];
 225                 if (node <= 0)
 226                         continue;
 227                 host = &dwmci_host[i];
 228                 err = exynos_dwmci_get_config(blob, node, host);
 229                 if (err) {
 230                         printf("%s: failed to decode dev %d\n", __func__, i);
 231                         return err;
 232                 }
 233
 234                 do_dwmci_init(host);
 235         }
 236         return 0;
 237 }
 238
 239 int exynos_dwmmc_init(const void *blob)
 240 {
 241         int node_list[DWMMC_MAX_CH_NUM];
 242         int boot_dev_node;
 243         int err = 0, count;
 244
 245         count = fdtdec_find_aliases_for_id(blob, "mmc",
 246                         COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list,
 247                         DWMMC_MAX_CH_NUM);
 248
 249         /* For DWMMC always set boot device as mmc 0 */
 250         if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
 251                 boot_dev_node = node_list[2];
 252                 node_list[2] = node_list[0];
 253                 node_list[0] = boot_dev_node;
 254         }
 255
 256         err = exynos_dwmci_process_node(blob, node_list, count);
 257
 258         return err;
 259 }
 260
 261 #ifdef CONFIG_DM_MMC
 262 static int exynos_dwmmc_probe(struct udevice *dev)
 263 {
 264         struct exynos_mmc_plat *plat = dev_get_platdata(dev);
 265         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 266         struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
 267         struct dwmci_host *host = &priv->host;
 268         int err;
 269
 270         err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
 271         if (err)
 272                 return err;
 273         err = do_dwmci_init(host);
 274         if (err)
 275                 return err;
 276
 277         dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
 278         host->mmc = &plat->mmc;
 279         host->mmc->priv = &priv->host;
 280         host->priv = dev;
 281         upriv->mmc = host->mmc;
 282
 283         return dwmci_probe(dev);
 284 }
 285
 286 static int exynos_dwmmc_bind(struct udevice *dev)
 287 {
 288         struct exynos_mmc_plat *plat = dev_get_platdata(dev);
 289
 290         return dwmci_bind(dev, &plat->mmc, &plat->cfg);
 291 }
 292
 293 static const struct udevice_id exynos_dwmmc_ids[] = {
 294         { .compatible = "samsung,exynos4412-dw-mshc" },
 295         { }
 296 };
 297
 298 U_BOOT_DRIVER(exynos_dwmmc_drv) = {
 299         .name           = "exynos_dwmmc",
 300         .id             = UCLASS_MMC,
 301         .of_match       = exynos_dwmmc_ids,
 302         .bind           = exynos_dwmmc_bind,
 303         .ops            = &dm_dwmci_ops,
 304         .probe          = exynos_dwmmc_probe,
 305         .priv_auto_alloc_size   = sizeof(struct dwmci_exynos_priv_data),
 306         .platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat),
 307 };
 308 #endif