[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c

/*
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 * Sukumar Ghorai <s-ghorai@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation's version 2 of
 * the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
#include <twl4030.h>
#include <twl6030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>

/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS	1000

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
			unsigned int siz);
static struct mmc hsmmc_dev[2];

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
	u32 value = 0;
	struct omap4_sys_ctrl_regs *const ctrl =
		(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;


	value = readl(&ctrl->control_pbiaslite);
	value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
	writel(value, &ctrl->control_pbiaslite);
	/* set VMMC to 3V */
	twl6030_power_mmc_init();
	value = readl(&ctrl->control_pbiaslite);
	value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
	writel(value, &ctrl->control_pbiaslite);
}
#endif

unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_OMAP34XX)
	t2_t *t2_base = (t2_t *)T2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
	u32 pbias_lite;

	pbias_lite = readl(&t2_base->pbias_lite);
	pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
	writel(pbias_lite, &t2_base->pbias_lite);
#endif
#if defined(CONFIG_TWL4030_POWER)
	twl4030_power_mmc_init();
	mdelay(100);	/* ramp-up delay from Linux code */
#endif
#if defined(CONFIG_OMAP34XX)
	writel(pbias_lite | PBIASLITEPWRDNZ1 |
		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
		&t2_base->pbias_lite);

	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
		&t2_base->devconf0);

	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
		&t2_base->devconf1);

	writel(readl(&prcm_base->fclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->fclken1_core);

	writel(readl(&prcm_base->iclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->iclken1_core);
#endif

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	/* PBIAS config needed for MMC1 only */
	if (mmc->block_dev.dev == 0)
		omap4_vmmc_pbias_config(mmc);
#endif

	return 0;
}

void mmc_init_stream(struct hsmmc *mmc_base)
{
	ulong start;

	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);

	writel(MMC_CMD0, &mmc_base->cmd);
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc!\n", __func__);
			return;
		}
	}
	writel(CC_MASK, &mmc_base->stat)
		;
	writel(MMC_CMD0, &mmc_base->cmd)
		;
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}


static int mmc_init_setup(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int reg_val;
	unsigned int dsor;
	ulong start;

	mmc_board_init(mmc);

	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
		&mmc_base->sysconfig);
	start = get_timer(0);
	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for softresetall!\n",
				__func__);
			return TIMEOUT;
		}
	}
	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
		&mmc_base->capa);

	reg_val = readl(&mmc_base->con) & RESERVED_MASK;

	writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
		MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);

	dsor = 240;
	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
		(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
		(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);

	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);

	writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
		IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
		&mmc_base->ie);

	mmc_init_stream(mmc_base);

	return 0;
}


static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
			struct mmc_data *data)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int flags, mmc_stat;
	ulong start;

	start = get_timer(0);
	while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting on cmd inhibit to clear\n",
					__func__);
			return TIMEOUT;
		}
	}
	writel(0xFFFFFFFF, &mmc_base->stat);
	start = get_timer(0);
	while (readl(&mmc_base->stat)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for STAT (%x) to clear\n",
				__func__, readl(&mmc_base->stat));
			return TIMEOUT;
		}
	}
	/*
	 * CMDREG
	 * CMDIDX[13:8]	: Command index
	 * DATAPRNT[5]	: Data Present Select
	 * ENCMDIDX[4]	: Command Index Check Enable
	 * ENCMDCRC[3]	: Command CRC Check Enable
	 * RSPTYP[1:0]
	 *	00 = No Response
	 *	01 = Length 136
	 *	10 = Length 48
	 *	11 = Length 48 Check busy after response
	 */
	/* Delay added before checking the status of frq change
	 * retry not supported by mmc.c(core file)
	 */
	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
		udelay(50000); /* wait 50 ms */

	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = 0;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		flags = RSP_TYPE_LGHT48B;
	else
		flags = RSP_TYPE_LGHT48;

	/* enable default flags */
	flags =	flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
			MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= CCCE_CHECK;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= CICE_CHECK;

	if (data) {
		if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
			 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
			flags |= (MSBS_MULTIBLK | BCE_ENABLE);
			data->blocksize = 512;
			writel(data->blocksize | (data->blocks << 16),
							&mmc_base->blk);
		} else
			writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);

		if (data->flags & MMC_DATA_READ)
			flags |= (DP_DATA | DDIR_READ);
		else
			flags |= (DP_DATA | DDIR_WRITE);
	}

	writel(cmd->cmdarg, &mmc_base->arg);
	writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);

	start = get_timer(0);
	do {
		mmc_stat = readl(&mmc_base->stat);
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s : timeout: No status update\n", __func__);
			return TIMEOUT;
		}
	} while (!mmc_stat);

	if ((mmc_stat & IE_CTO) != 0)
		return TIMEOUT;
	else if ((mmc_stat & ERRI_MASK) != 0)
		return -1;

	if (mmc_stat & CC_MASK) {
		writel(CC_MASK, &mmc_base->stat);
		if (cmd->resp_type & MMC_RSP_PRESENT) {
			if (cmd->resp_type & MMC_RSP_136) {
				/* response type 2 */
				cmd->response[3] = readl(&mmc_base->rsp10);
				cmd->response[2] = readl(&mmc_base->rsp32);
				cmd->response[1] = readl(&mmc_base->rsp54);
				cmd->response[0] = readl(&mmc_base->rsp76);
			} else
				/* response types 1, 1b, 3, 4, 5, 6 */
				cmd->response[0] = readl(&mmc_base->rsp10);
		}
	}

	if (data && (data->flags & MMC_DATA_READ)) {
		mmc_read_data(mmc_base,	data->dest,
				data->blocksize * data->blocks);
	} else if (data && (data->flags & MMC_DATA_WRITE)) {
		mmc_write_data(mmc_base, data->src,
				data->blocksize * data->blocks);
	}
	return 0;
}

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
	unsigned int *output_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BRR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);
			for (k = 0; k < count; k++) {
				*output_buf = readl(&mmc_base->data);
				output_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BWR_MASK)
			writel(readl(&mmc_base->stat) | BWR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
				unsigned int size)
{
	unsigned int *input_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BWR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BWR_MASK,
					&mmc_base->stat);
			for (k = 0; k < count; k++) {
				writel(*input_buf, &mmc_base->data);
				input_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BRR_MASK)
			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static void mmc_set_ios(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int dsor = 0;
	ulong start;

	/* configue bus width */
	switch (mmc->bus_width) {
	case 8:
		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
			&mmc_base->con);
		break;

	case 4:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
			&mmc_base->hctl);
		break;

	case 1:
	default:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
			&mmc_base->hctl);
		break;
	}

	/* configure clock with 96Mhz system clock.
	 */
	if (mmc->clock != 0) {
		dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
		if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
			dsor++;
	}

	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
				(ICE_STOP | DTO_15THDTO | CEN_DISABLE));

	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
				(dsor << CLKD_OFFSET) | ICE_OSCILLATE);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}

int omap_mmc_init(int dev_index)
{
	struct mmc *mmc;

	mmc = &hsmmc_dev[dev_index];

	sprintf(mmc->name, "OMAP SD/MMC");
	mmc->send_cmd = mmc_send_cmd;
	mmc->set_ios = mmc_set_ios;
	mmc->init = mmc_init_setup;
	mmc->getcd = NULL;

	switch (dev_index) {
	case 0:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		break;
#ifdef OMAP_HSMMC2_BASE
	case 1:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
		break;
#endif
#ifdef OMAP_HSMMC3_BASE
	case 2:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
		break;
#endif
	default:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		return 1;
	}
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
				MMC_MODE_HC;

	mmc->f_min = 400000;
	mmc->f_max = 52000000;

	mmc->b_max = 0;

#if defined(CONFIG_OMAP34XX)
	/*
	 * Silicon revs 2.1 and older do not support multiblock transfers.
	 */
	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
		mmc->b_max = 1;
#endif

	mmc_register(mmc);

	return 0;
}
Commit	Line	Data
de941241 SG	1	/*
	2	* (C) Copyright 2008
	3	* Texas Instruments, <www.ti.com>
	4	* Sukumar Ghorai <s-ghorai@ti.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation's version 2 of
	12	* the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <config.h>
	26	#include <common.h>
	27	#include <mmc.h>
	28	#include <part.h>
	29	#include <i2c.h>
	30	#include <twl4030.h>
14fa2dd0	31	#include <twl6030.h>
de941241 SG	32	#include <asm/io.h>
de941241 SG	33	#include <asm/arch/mmc_host_def.h>
96e0e7b3	34	#include <asm/arch/sys_proto.h>
de941241	35
eb9a28f6 NM	36	/* If we fail after 1 second wait, something is really bad */
	37	#define MAX_RETRY_MS 1000
	38
933efe64 S	39	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size);
	40	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
	41	unsigned int siz);
de941241	42	static struct mmc hsmmc_dev[2];
14fa2dd0 B	43
	44	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	45	static void omap4_vmmc_pbias_config(struct mmc *mmc)
	46	{
	47	u32 value = 0;
	48	struct omap4_sys_ctrl_regs *const ctrl =
	49	(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
	50
	51
	52	value = readl(&ctrl->control_pbiaslite);
	53	value &= ~(MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ);
	54	writel(value, &ctrl->control_pbiaslite);
	55	/* set VMMC to 3V */
	56	twl6030_power_mmc_init();
	57	value = readl(&ctrl->control_pbiaslite);
	58	value \|= MMC1_PBIASLITE_VMODE \| MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ;
	59	writel(value, &ctrl->control_pbiaslite);
	60	}
	61	#endif
	62
	63	unsigned char mmc_board_init(struct mmc *mmc)
de941241	64	{
de941241 SG	65	#if defined(CONFIG_OMAP34XX)
	66	t2_t t2_base = (t2_t )T2_BASE;
	67	struct prcm prcm_base = (struct prcm )PRCM_BASE;
b1e725f2	68	u32 pbias_lite;
de941241	69
b1e725f2 GI	70	pbias_lite = readl(&t2_base->pbias_lite);
	71	pbias_lite &= ~(PBIASLITEPWRDNZ1 \| PBIASLITEPWRDNZ0);
	72	writel(pbias_lite, &t2_base->pbias_lite);
	73	#endif
	74	#if defined(CONFIG_TWL4030_POWER)
	75	twl4030_power_mmc_init();
	76	mdelay(100); /* ramp-up delay from Linux code */
	77	#endif
	78	#if defined(CONFIG_OMAP34XX)
	79	writel(pbias_lite \| PBIASLITEPWRDNZ1 \|
de941241 SG	80	PBIASSPEEDCTRL0 \| PBIASLITEPWRDNZ0,
	81	&t2_base->pbias_lite);
	82
	83	writel(readl(&t2_base->devconf0) \| MMCSDIO1ADPCLKISEL,
	84	&t2_base->devconf0);
	85
	86	writel(readl(&t2_base->devconf1) \| MMCSDIO2ADPCLKISEL,
	87	&t2_base->devconf1);
	88
	89	writel(readl(&prcm_base->fclken1_core) \|
	90	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	91	&prcm_base->fclken1_core);
	92
	93	writel(readl(&prcm_base->iclken1_core) \|
	94	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	95	&prcm_base->iclken1_core);
	96	#endif
	97
14fa2dd0 B	98	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	99	/* PBIAS config needed for MMC1 only */
	100	if (mmc->block_dev.dev == 0)
	101	omap4_vmmc_pbias_config(mmc);
	102	#endif
de941241 SG	103
	104	return 0;
	105	}
	106
933efe64	107	void mmc_init_stream(struct hsmmc *mmc_base)
de941241	108	{
eb9a28f6	109	ulong start;
de941241 SG	110
	111	writel(readl(&mmc_base->con) \| INIT_INITSTREAM, &mmc_base->con);
	112
	113	writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6 NM	114	start = get_timer(0);
	115	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	116	if (get_timer(0) - start > MAX_RETRY_MS) {
	117	printf("%s: timedout waiting for cc!\n", __func__);
	118	return;
	119	}
	120	}
de941241 SG	121	writel(CC_MASK, &mmc_base->stat)
	122	;
	123	writel(MMC_CMD0, &mmc_base->cmd)
	124	;
eb9a28f6 NM	125	start = get_timer(0);
	126	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	127	if (get_timer(0) - start > MAX_RETRY_MS) {
	128	printf("%s: timedout waiting for cc2!\n", __func__);
	129	return;
	130	}
	131	}
de941241 SG	132	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
	133	}
	134
	135
	136	static int mmc_init_setup(struct mmc *mmc)
	137	{
933efe64	138	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241 SG	139	unsigned int reg_val;
de941241 SG	140	unsigned int dsor;
eb9a28f6	141	ulong start;
de941241	142
14fa2dd0	143	mmc_board_init(mmc);
de941241 SG	144
	145	writel(readl(&mmc_base->sysconfig) \| MMC_SOFTRESET,
	146	&mmc_base->sysconfig);
eb9a28f6 NM	147	start = get_timer(0);
	148	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
	149	if (get_timer(0) - start > MAX_RETRY_MS) {
	150	printf("%s: timedout waiting for cc2!\n", __func__);
	151	return TIMEOUT;
	152	}
	153	}
de941241	154	writel(readl(&mmc_base->sysctl) \| SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6 NM	155	start = get_timer(0);
	156	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
	157	if (get_timer(0) - start > MAX_RETRY_MS) {
	158	printf("%s: timedout waiting for softresetall!\n",
	159	__func__);
	160	return TIMEOUT;
	161	}
	162	}
de941241 SG	163	writel(DTW_1_BITMODE \| SDBP_PWROFF \| SDVS_3V0, &mmc_base->hctl);
	164	writel(readl(&mmc_base->capa) \| VS30_3V0SUP \| VS18_1V8SUP,
	165	&mmc_base->capa);
	166
	167	reg_val = readl(&mmc_base->con) & RESERVED_MASK;
	168
	169	writel(CTPL_MMC_SD \| reg_val \| WPP_ACTIVEHIGH \| CDP_ACTIVEHIGH \|
	170	MIT_CTO \| DW8_1_4BITMODE \| MODE_FUNC \| STR_BLOCK \|
	171	HR_NOHOSTRESP \| INIT_NOINIT \| NOOPENDRAIN, &mmc_base->con);
	172
	173	dsor = 240;
	174	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	175	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	176	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	177	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
eb9a28f6 NM	178	start = get_timer(0);
	179	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	180	if (get_timer(0) - start > MAX_RETRY_MS) {
	181	printf("%s: timedout waiting for ics!\n", __func__);
	182	return TIMEOUT;
	183	}
	184	}
de941241 SG	185	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	186
	187	writel(readl(&mmc_base->hctl) \| SDBP_PWRON, &mmc_base->hctl);
	188
	189	writel(IE_BADA \| IE_CERR \| IE_DEB \| IE_DCRC \| IE_DTO \| IE_CIE \|
	190	IE_CEB \| IE_CCRC \| IE_CTO \| IE_BRR \| IE_BWR \| IE_TC \| IE_CC,
	191	&mmc_base->ie);
	192
	193	mmc_init_stream(mmc_base);
	194
	195	return 0;
	196	}
	197
	198
	199	static int mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	200	struct mmc_data *data)
	201	{
933efe64	202	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	203	unsigned int flags, mmc_stat;
eb9a28f6	204	ulong start;
de941241	205
eb9a28f6	206	start = get_timer(0);
a7778f8f	207	while ((readl(&mmc_base->pstate) & (DATI_MASK \| CMDI_MASK)) != 0) {
eb9a28f6	208	if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f TR	209	printf("%s: timedout waiting on cmd inhibit to clear\n",
a7778f8f TR	210	__func__);
eb9a28f6 NM	211	return TIMEOUT;
	212	}
	213	}
de941241	214	writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6 NM	215	start = get_timer(0);
	216	while (readl(&mmc_base->stat)) {
	217	if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de GI	218	printf("%s: timedout waiting for STAT (%x) to clear\n",
15ceb1de GI	219	__func__, readl(&mmc_base->stat));
eb9a28f6 NM	220	return TIMEOUT;
	221	}
	222	}
de941241 SG	223	/*
	224	* CMDREG
	225	* CMDIDX[13:8] : Command index
	226	* DATAPRNT[5] : Data Present Select
	227	* ENCMDIDX[4] : Command Index Check Enable
	228	* ENCMDCRC[3] : Command CRC Check Enable
	229	* RSPTYP[1:0]
	230	* 00 = No Response
	231	* 01 = Length 136
	232	* 10 = Length 48
	233	* 11 = Length 48 Check busy after response
	234	*/
	235	/* Delay added before checking the status of frq change
	236	* retry not supported by mmc.c(core file)
	237	*/
	238	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
	239	udelay(50000); /* wait 50 ms */
	240
	241	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	242	flags = 0;
	243	else if (cmd->resp_type & MMC_RSP_136)
	244	flags = RSP_TYPE_LGHT136 \| CICE_NOCHECK;
	245	else if (cmd->resp_type & MMC_RSP_BUSY)
	246	flags = RSP_TYPE_LGHT48B;
	247	else
	248	flags = RSP_TYPE_LGHT48;
	249
	250	/* enable default flags */
	251	flags = flags \| (CMD_TYPE_NORMAL \| CICE_NOCHECK \| CCCE_NOCHECK \|
	252	MSBS_SGLEBLK \| ACEN_DISABLE \| BCE_DISABLE \| DE_DISABLE);
	253
	254	if (cmd->resp_type & MMC_RSP_CRC)
	255	flags \|= CCCE_CHECK;
	256	if (cmd->resp_type & MMC_RSP_OPCODE)
	257	flags \|= CICE_CHECK;
	258
	259	if (data) {
	260	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) \|\|
	261	(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
	262	flags \|= (MSBS_MULTIBLK \| BCE_ENABLE);
	263	data->blocksize = 512;
	264	writel(data->blocksize \| (data->blocks << 16),
	265	&mmc_base->blk);
	266	} else
	267	writel(data->blocksize \| NBLK_STPCNT, &mmc_base->blk);
	268
	269	if (data->flags & MMC_DATA_READ)
	270	flags \|= (DP_DATA \| DDIR_READ);
	271	else
	272	flags \|= (DP_DATA \| DDIR_WRITE);
	273	}
	274
	275	writel(cmd->cmdarg, &mmc_base->arg);
	276	writel((cmd->cmdidx << 24) \| flags, &mmc_base->cmd);
	277
eb9a28f6	278	start = get_timer(0);
de941241 SG	279	do {
de941241 SG	280	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	281	if (get_timer(0) - start > MAX_RETRY_MS) {
	282	printf("%s : timeout: No status update\n", __func__);
	283	return TIMEOUT;
	284	}
	285	} while (!mmc_stat);
de941241 SG	286
	287	if ((mmc_stat & IE_CTO) != 0)
	288	return TIMEOUT;
	289	else if ((mmc_stat & ERRI_MASK) != 0)
	290	return -1;
	291
	292	if (mmc_stat & CC_MASK) {
	293	writel(CC_MASK, &mmc_base->stat);
	294	if (cmd->resp_type & MMC_RSP_PRESENT) {
	295	if (cmd->resp_type & MMC_RSP_136) {
	296	/* response type 2 */
	297	cmd->response[3] = readl(&mmc_base->rsp10);
	298	cmd->response[2] = readl(&mmc_base->rsp32);
	299	cmd->response[1] = readl(&mmc_base->rsp54);
	300	cmd->response[0] = readl(&mmc_base->rsp76);
	301	} else
	302	/* response types 1, 1b, 3, 4, 5, 6 */
	303	cmd->response[0] = readl(&mmc_base->rsp10);
	304	}
	305	}
	306
	307	if (data && (data->flags & MMC_DATA_READ)) {
	308	mmc_read_data(mmc_base, data->dest,
	309	data->blocksize * data->blocks);
	310	} else if (data && (data->flags & MMC_DATA_WRITE)) {
	311	mmc_write_data(mmc_base, data->src,
	312	data->blocksize * data->blocks);
	313	}
	314	return 0;
	315	}
	316
933efe64	317	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size)
de941241 SG	318	{
	319	unsigned int output_buf = (unsigned int )buf;
	320	unsigned int mmc_stat;
	321	unsigned int count;
	322
	323	/*
	324	* Start Polled Read
	325	*/
	326	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	327	count /= 4;
	328
	329	while (size) {
eb9a28f6	330	ulong start = get_timer(0);
de941241 SG	331	do {
de941241 SG	332	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	333	if (get_timer(0) - start > MAX_RETRY_MS) {
	334	printf("%s: timedout waiting for status!\n",
	335	__func__);
	336	return TIMEOUT;
	337	}
de941241 SG	338	} while (mmc_stat == 0);
	339
	340	if ((mmc_stat & ERRI_MASK) != 0)
	341	return 1;
	342
	343	if (mmc_stat & BRR_MASK) {
	344	unsigned int k;
	345
	346	writel(readl(&mmc_base->stat) \| BRR_MASK,
	347	&mmc_base->stat);
	348	for (k = 0; k < count; k++) {
	349	*output_buf = readl(&mmc_base->data);
	350	output_buf++;
	351	}
	352	size -= (count*4);
	353	}
	354
	355	if (mmc_stat & BWR_MASK)
	356	writel(readl(&mmc_base->stat) \| BWR_MASK,
	357	&mmc_base->stat);
	358
	359	if (mmc_stat & TC_MASK) {
	360	writel(readl(&mmc_base->stat) \| TC_MASK,
	361	&mmc_base->stat);
	362	break;
	363	}
	364	}
	365	return 0;
	366	}
	367
933efe64 S	368	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
933efe64 S	369	unsigned int size)
de941241 SG	370	{
	371	unsigned int input_buf = (unsigned int )buf;
	372	unsigned int mmc_stat;
	373	unsigned int count;
	374
	375	/*
	376	* Start Polled Read
	377	*/
	378	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	379	count /= 4;
	380
	381	while (size) {
eb9a28f6	382	ulong start = get_timer(0);
de941241 SG	383	do {
de941241 SG	384	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	385	if (get_timer(0) - start > MAX_RETRY_MS) {
	386	printf("%s: timedout waiting for status!\n",
	387	__func__);
	388	return TIMEOUT;
	389	}
de941241 SG	390	} while (mmc_stat == 0);
	391
	392	if ((mmc_stat & ERRI_MASK) != 0)
	393	return 1;
	394
	395	if (mmc_stat & BWR_MASK) {
	396	unsigned int k;
	397
	398	writel(readl(&mmc_base->stat) \| BWR_MASK,
	399	&mmc_base->stat);
	400	for (k = 0; k < count; k++) {
	401	writel(*input_buf, &mmc_base->data);
	402	input_buf++;
	403	}
	404	size -= (count*4);
	405	}
	406
	407	if (mmc_stat & BRR_MASK)
	408	writel(readl(&mmc_base->stat) \| BRR_MASK,
	409	&mmc_base->stat);
	410
	411	if (mmc_stat & TC_MASK) {
	412	writel(readl(&mmc_base->stat) \| TC_MASK,
	413	&mmc_base->stat);
	414	break;
	415	}
	416	}
	417	return 0;
	418	}
	419
	420	static void mmc_set_ios(struct mmc *mmc)
	421	{
933efe64	422	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	423	unsigned int dsor = 0;
eb9a28f6	424	ulong start;
de941241 SG	425
	426	/* configue bus width */
	427	switch (mmc->bus_width) {
	428	case 8:
	429	writel(readl(&mmc_base->con) \| DTW_8_BITMODE,
	430	&mmc_base->con);
	431	break;
	432
	433	case 4:
	434	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	435	&mmc_base->con);
	436	writel(readl(&mmc_base->hctl) \| DTW_4_BITMODE,
	437	&mmc_base->hctl);
	438	break;
	439
	440	case 1:
	441	default:
	442	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	443	&mmc_base->con);
	444	writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
	445	&mmc_base->hctl);
	446	break;
	447	}
	448
	449	/* configure clock with 96Mhz system clock.
	450	*/
	451	if (mmc->clock != 0) {
	452	dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
	453	if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
	454	dsor++;
	455	}
	456
	457	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	458	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	459
	460	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	461	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
	462
eb9a28f6 NM	463	start = get_timer(0);
	464	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	465	if (get_timer(0) - start > MAX_RETRY_MS) {
	466	printf("%s: timedout waiting for ics!\n", __func__);
	467	return;
	468	}
	469	}
de941241 SG	470	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	471	}
	472
	473	int omap_mmc_init(int dev_index)
	474	{
	475	struct mmc *mmc;
	476
	477	mmc = &hsmmc_dev[dev_index];
	478
	479	sprintf(mmc->name, "OMAP SD/MMC");
	480	mmc->send_cmd = mmc_send_cmd;
	481	mmc->set_ios = mmc_set_ios;
	482	mmc->init = mmc_init_setup;
48972d90	483	mmc->getcd = NULL;
de941241 SG	484
	485	switch (dev_index) {
	486	case 0:
933efe64	487	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241	488	break;
1037d585	489	#ifdef OMAP_HSMMC2_BASE
de941241	490	case 1:
933efe64	491	mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
de941241	492	break;
1037d585 TR	493	#endif
1037d585 TR	494	#ifdef OMAP_HSMMC3_BASE
de941241	495	case 2:
933efe64	496	mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
de941241	497	break;
1037d585	498	#endif
de941241	499	default:
933efe64	500	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 SG	501	return 1;
	502	}
	503	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
ecd9af88 B	504	mmc->host_caps = MMC_MODE_4BIT \| MMC_MODE_HS_52MHz \| MMC_MODE_HS \|
ecd9af88 B	505	MMC_MODE_HC;
de941241 SG	506
	507	mmc->f_min = 400000;
	508	mmc->f_max = 52000000;
	509
8feafcc4 JR	510	mmc->b_max = 0;
8feafcc4 JR	511
4ca9244d JR	512	#if defined(CONFIG_OMAP34XX)
	513	/*
	514	* Silicon revs 2.1 and older do not support multiblock transfers.
	515	*/
	516	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
	517	mmc->b_max = 1;
	518	#endif
	519
de941241 SG	520	mmc_register(mmc);
	521
	522	return 0;
	523	}