[people/ms/u-boot.git] / drivers / mmc / sdhci.c

/*
 * Copyright 2011, Marvell Semiconductor Inc.
 * Lei Wen <leiwen@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Back ported to the 8xx platform (from the 8260 platform) by
 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
 */

#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
#else
void *aligned_buffer;
#endif

static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
	unsigned long timeout;

	/* Wait max 100 ms */
	timeout = 100;
	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
		if (timeout == 0) {
			printf("%s: Reset 0x%x never completed.\n",
			       __func__, (int)mask);
			return;
		}
		timeout--;
		udelay(1000);
	}
}

static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
{
	int i;
	if (cmd->resp_type & MMC_RSP_136) {
		/* CRC is stripped so we need to do some shifting. */
		for (i = 0; i < 4; i++) {
			cmd->response[i] = sdhci_readl(host,
					SDHCI_RESPONSE + (3-i)*4) << 8;
			if (i != 3)
				cmd->response[i] |= sdhci_readb(host,
						SDHCI_RESPONSE + (3-i)*4-1);
		}
	} else {
		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	}
}

static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
{
	int i;
	char *offs;
	for (i = 0; i < data->blocksize; i += 4) {
		offs = data->dest + i;
		if (data->flags == MMC_DATA_READ)
			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
		else
			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
	}
}

static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
				unsigned int start_addr)
{
	unsigned int stat, rdy, mask, timeout, block = 0;
#ifdef CONFIG_MMC_SDHCI_SDMA
	unsigned char ctrl;
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	ctrl &= ~SDHCI_CTRL_DMA_MASK;
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif

	timeout = 1000000;
	rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR) {
			printf("%s: Error detected in status(0x%X)!\n",
			       __func__, stat);
			return -EIO;
		}
		if (stat & rdy) {
			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
				continue;
			sdhci_writel(host, rdy, SDHCI_INT_STATUS);
			sdhci_transfer_pio(host, data);
			data->dest += data->blocksize;
			if (++block >= data->blocks)
				break;
		}
#ifdef CONFIG_MMC_SDHCI_SDMA
		if (stat & SDHCI_INT_DMA_END) {
			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
			start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		}
#endif
		if (timeout-- > 0)
			udelay(10);
		else {
			printf("%s: Transfer data timeout\n", __func__);
			return -ETIMEDOUT;
		}
	} while (!(stat & SDHCI_INT_DATA_END));
	return 0;
}

/*
 * No command will be sent by driver if card is busy, so driver must wait
 * for card ready state.
 * Every time when card is busy after timeout then (last) timeout value will be
 * increased twice but only if it doesn't exceed global defined maximum.
 * Each function call will use last timeout value.
 */
#define SDHCI_CMD_MAX_TIMEOUT			3200
#define SDHCI_CMD_DEFAULT_TIMEOUT		100
#define SDHCI_READ_STATUS_TIMEOUT		1000

#ifdef CONFIG_DM_MMC_OPS
static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

#else
static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
#endif
	struct sdhci_host *host = mmc->priv;
	unsigned int stat = 0;
	int ret = 0;
	int trans_bytes = 0, is_aligned = 1;
	u32 mask, flags, mode;
	unsigned int time = 0, start_addr = 0;
	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
	unsigned start = get_timer(0);

	/* Timeout unit - ms */
	static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;

	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		mask &= ~SDHCI_DATA_INHIBIT;

	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
		if (time >= cmd_timeout) {
			printf("%s: MMC: %d busy ", __func__, mmc_dev);
			if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
				cmd_timeout += cmd_timeout;
				printf("timeout increasing to: %u ms.\n",
				       cmd_timeout);
			} else {
				puts("timeout.\n");
				return -ECOMM;
			}
		}
		time++;
		udelay(1000);
	}

	mask = SDHCI_INT_RESPONSE;
	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->resp_type & MMC_RSP_BUSY) {
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
		if (data)
			mask |= SDHCI_INT_DATA_END;
	} else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
	if (data)
		flags |= SDHCI_CMD_DATA;

	/* Set Transfer mode regarding to data flag */
	if (data != 0) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
		mode = SDHCI_TRNS_BLK_CNT_EN;
		trans_bytes = data->blocks * data->blocksize;
		if (data->blocks > 1)
			mode |= SDHCI_TRNS_MULTI;

		if (data->flags == MMC_DATA_READ)
			mode |= SDHCI_TRNS_READ;

#ifdef CONFIG_MMC_SDHCI_SDMA
		if (data->flags == MMC_DATA_READ)
			start_addr = (unsigned long)data->dest;
		else
			start_addr = (unsigned long)data->src;
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				(start_addr & 0x7) != 0x0) {
			is_aligned = 0;
			start_addr = (unsigned long)aligned_buffer;
			if (data->flags != MMC_DATA_READ)
				memcpy(aligned_buffer, data->src, trans_bytes);
		}

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
		/*
		 * Always use this bounce-buffer when
		 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
		 */
		is_aligned = 0;
		start_addr = (unsigned long)aligned_buffer;
		if (data->flags != MMC_DATA_READ)
			memcpy(aligned_buffer, data->src, trans_bytes);
#endif

		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		mode |= SDHCI_TRNS_DMA;
#endif
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
				data->blocksize),
				SDHCI_BLOCK_SIZE);
		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
	} else if (cmd->resp_type & MMC_RSP_BUSY) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	}

	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDHCI_SDMA
	trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
	flush_cache(start_addr, trans_bytes);
#endif
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
	start = get_timer(0);
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR)
			break;

		if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
			if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
				return 0;
			} else {
				printf("%s: Timeout for status update!\n",
				       __func__);
				return -ETIMEDOUT;
			}
		}
	} while ((stat & mask) != mask);

	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
		sdhci_cmd_done(host, cmd);
		sdhci_writel(host, mask, SDHCI_INT_STATUS);
	} else
		ret = -1;

	if (!ret && data)
		ret = sdhci_transfer_data(host, data, start_addr);

	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
		udelay(1000);

	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	if (!ret) {
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				!is_aligned && (data->flags == MMC_DATA_READ))
			memcpy(data->dest, aligned_buffer, trans_bytes);
		return 0;
	}

	sdhci_reset(host, SDHCI_RESET_CMD);
	sdhci_reset(host, SDHCI_RESET_DATA);
	if (stat & SDHCI_INT_TIMEOUT)
		return -ETIMEDOUT;
	else
		return -ECOMM;
}

static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
	struct sdhci_host *host = mmc->priv;
	unsigned int div, clk = 0, timeout, reg;

	/* Wait max 20 ms */
	timeout = 200;
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
			   (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
		if (timeout == 0) {
			printf("%s: Timeout to wait cmd & data inhibit\n",
			       __func__);
			return -EBUSY;
		}

		timeout--;
		udelay(100);
	}

	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return 0;

	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		/*
		 * Check if the Host Controller supports Programmable Clock
		 * Mode.
		 */
		if (host->clk_mul) {
			for (div = 1; div <= 1024; div++) {
				if ((mmc->cfg->f_max * host->clk_mul / div)
					<= clock)
					break;
			}

			/*
			 * Set Programmable Clock Mode in the Clock
			 * Control register.
			 */
			clk = SDHCI_PROG_CLOCK_MODE;
			div--;
		} else {
			/* Version 3.00 divisors must be a multiple of 2. */
			if (mmc->cfg->f_max <= clock) {
				div = 1;
			} else {
				for (div = 2;
				     div < SDHCI_MAX_DIV_SPEC_300;
				     div += 2) {
					if ((mmc->cfg->f_max / div) <= clock)
						break;
				}
			}
			div >>= 1;
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
			if ((mmc->cfg->f_max / div) <= clock)
				break;
		}
		div >>= 1;
	}

	if (host->set_clock)
		host->set_clock(host->index, div);

	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
	clk |= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Wait max 20 ms */
	timeout = 20;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			printf("%s: Internal clock never stabilised.\n",
			       __func__);
			return -EBUSY;
		}
		timeout--;
		udelay(1000);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	return 0;
}

static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
	u8 pwr = 0;

	if (power != (unsigned short)-1) {
		switch (1 << power) {
		case MMC_VDD_165_195:
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		}
	}

	if (pwr == 0) {
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
		return;
	}

	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);

	pwr |= SDHCI_POWER_ON;

	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}

#ifdef CONFIG_DM_MMC_OPS
static int sdhci_set_ios(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static void sdhci_set_ios(struct mmc *mmc)
{
#endif
	u32 ctrl;
	struct sdhci_host *host = mmc->priv;

	if (host->set_control_reg)
		host->set_control_reg(host);

	if (mmc->clock != host->clock)
		sdhci_set_clock(mmc, mmc->clock);

	/* Set bus width */
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if (mmc->bus_width == 8) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (mmc->bus_width == 4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}

	if (mmc->clock > 26000000)
		ctrl |= SDHCI_CTRL_HISPD;
	else
		ctrl &= ~SDHCI_CTRL_HISPD;

	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
		ctrl &= ~SDHCI_CTRL_HISPD;

	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#ifdef CONFIG_DM_MMC_OPS
	return 0;
#endif
}

static int sdhci_init(struct mmc *mmc)
{
	struct sdhci_host *host = mmc->priv;

	sdhci_reset(host, SDHCI_RESET_ALL);

	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
		aligned_buffer = memalign(8, 512*1024);
		if (!aligned_buffer) {
			printf("%s: Aligned buffer alloc failed!!!\n",
			       __func__);
			return -ENOMEM;
		}
	}

	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);

	if (host->ops->get_cd)
		host->ops->get_cd(host);

	/* Enable only interrupts served by the SD controller */
	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
		     SDHCI_INT_ENABLE);
	/* Mask all sdhci interrupt sources */
	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);

	return 0;
}

#ifdef CONFIG_DM_MMC_OPS
int sdhci_probe(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	return sdhci_init(mmc);
}

const struct dm_mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
};
#else
static const struct mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
	.init		= sdhci_init,
};
#endif

int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
		u32 max_clk, u32 min_clk)
{
	u32 caps, caps_1;

	caps = sdhci_readl(host, SDHCI_CAPABILITIES);

#ifdef CONFIG_MMC_SDHCI_SDMA
	if (!(caps & SDHCI_CAN_DO_SDMA)) {
		printf("%s: Your controller doesn't support SDMA!!\n",
		       __func__);
		return -EINVAL;
	}
#endif
	if (host->quirks & SDHCI_QUIRK_REG32_RW)
		host->version =
			sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
	else
		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);

	cfg->name = host->name;
#ifndef CONFIG_DM_MMC_OPS
	cfg->ops = &sdhci_ops;
#endif
	if (max_clk)
		cfg->f_max = max_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
				SDHCI_CLOCK_BASE_SHIFT;
		else
			cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
				SDHCI_CLOCK_BASE_SHIFT;
		cfg->f_max *= 1000000;
	}
	if (cfg->f_max == 0) {
		printf("%s: Hardware doesn't specify base clock frequency\n",
		       __func__);
		return -EINVAL;
	}
	if (min_clk)
		cfg->f_min = min_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
		else
			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
	}
	cfg->voltages = 0;
	if (caps & SDHCI_CAN_VDD_330)
		cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
	if (caps & SDHCI_CAN_VDD_300)
		cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & SDHCI_CAN_VDD_180)
		cfg->voltages |= MMC_VDD_165_195;

	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
		cfg->voltages |= host->voltages;

	cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		if (!(caps & SDHCI_CAN_DO_8BIT))
			cfg->host_caps &= ~MMC_MODE_8BIT;
	}

	if (host->host_caps)
		cfg->host_caps |= host->host_caps;

	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	/*
	 * In case of Host Controller v3.00, find out whether clock
	 * multiplier is supported.
	 */
	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
		host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
				SDHCI_CLOCK_MUL_SHIFT;
	}

	return 0;
}

#ifdef CONFIG_BLK
int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
{
	return mmc_bind(dev, mmc, cfg);
}
#else
int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
{
	int ret;

	ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
	if (ret)
		return ret;

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL) {
		printf("%s: mmc create fail!\n", __func__);
		return -ENOMEM;
	}

	return 0;
}
#endif
Commit	Line	Data
af62a557 LW	1	/*
	2	* Copyright 2011, Marvell Semiconductor Inc.
	3	* Lei Wen <leiwen@marvell.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
af62a557 LW	6	*
	7	* Back ported to the 8xx platform (from the 8260 platform) by
	8	* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
	9	*/
	10
	11	#include <common.h>
2a809093	12	#include <errno.h>
af62a557 LW	13	#include <malloc.h>
	14	#include <mmc.h>
	15	#include <sdhci.h>
	16
492d3223 SR	17	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	18	void aligned_buffer = (void )CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
	19	#else
af62a557	20	void *aligned_buffer;
492d3223	21	#endif
af62a557 LW	22
	23	static void sdhci_reset(struct sdhci_host *host, u8 mask)
	24	{
	25	unsigned long timeout;
	26
	27	/* Wait max 100 ms */
	28	timeout = 100;
	29	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	30	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
	31	if (timeout == 0) {
30e6d979 DR	32	printf("%s: Reset 0x%x never completed.\n",
30e6d979 DR	33	__func__, (int)mask);
af62a557 LW	34	return;
	35	}
	36	timeout--;
	37	udelay(1000);
	38	}
	39	}
	40
	41	static void sdhci_cmd_done(struct sdhci_host host, struct mmc_cmd cmd)
	42	{
	43	int i;
	44	if (cmd->resp_type & MMC_RSP_136) {
	45	/* CRC is stripped so we need to do some shifting. */
	46	for (i = 0; i < 4; i++) {
	47	cmd->response[i] = sdhci_readl(host,
	48	SDHCI_RESPONSE + (3-i)*4) << 8;
	49	if (i != 3)
	50	cmd->response[i] \|= sdhci_readb(host,
	51	SDHCI_RESPONSE + (3-i)*4-1);
	52	}
	53	} else {
	54	cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	55	}
	56	}
	57
	58	static void sdhci_transfer_pio(struct sdhci_host host, struct mmc_data data)
	59	{
	60	int i;
	61	char *offs;
	62	for (i = 0; i < data->blocksize; i += 4) {
	63	offs = data->dest + i;
	64	if (data->flags == MMC_DATA_READ)
	65	(u32 )offs = sdhci_readl(host, SDHCI_BUFFER);
	66	else
	67	sdhci_writel(host, (u32 )offs, SDHCI_BUFFER);
	68	}
	69	}
	70
	71	static int sdhci_transfer_data(struct sdhci_host host, struct mmc_data data,
	72	unsigned int start_addr)
	73	{
a004abde	74	unsigned int stat, rdy, mask, timeout, block = 0;
45a68fe2	75	#ifdef CONFIG_MMC_SDHCI_SDMA
804c7f42	76	unsigned char ctrl;
2c011847	77	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
804c7f42	78	ctrl &= ~SDHCI_CTRL_DMA_MASK;
2c011847	79	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
804c7f42	80	#endif
af62a557	81
5d48e422	82	timeout = 1000000;
af62a557 LW	83	rdy = SDHCI_INT_SPACE_AVAIL \| SDHCI_INT_DATA_AVAIL;
	84	mask = SDHCI_DATA_AVAILABLE \| SDHCI_SPACE_AVAILABLE;
	85	do {
	86	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	87	if (stat & SDHCI_INT_ERROR) {
30e6d979 DR	88	printf("%s: Error detected in status(0x%X)!\n",
30e6d979 DR	89	__func__, stat);
2cb5d67c	90	return -EIO;
af62a557 LW	91	}
	92	if (stat & rdy) {
	93	if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
	94	continue;
	95	sdhci_writel(host, rdy, SDHCI_INT_STATUS);
	96	sdhci_transfer_pio(host, data);
	97	data->dest += data->blocksize;
	98	if (++block >= data->blocks)
	99	break;
	100	}
45a68fe2	101	#ifdef CONFIG_MMC_SDHCI_SDMA
af62a557 LW	102	if (stat & SDHCI_INT_DMA_END) {
af62a557 LW	103	sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
3e81c772	104	start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
af62a557 LW	105	start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
	106	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	107	}
	108	#endif
a004abde LW	109	if (timeout-- > 0)
	110	udelay(10);
	111	else {
30e6d979	112	printf("%s: Transfer data timeout\n", __func__);
2cb5d67c	113	return -ETIMEDOUT;
a004abde	114	}
af62a557 LW	115	} while (!(stat & SDHCI_INT_DATA_END));
	116	return 0;
	117	}
	118
56b34bc6 PM	119	/*
	120	* No command will be sent by driver if card is busy, so driver must wait
	121	* for card ready state.
	122	* Every time when card is busy after timeout then (last) timeout value will be
	123	* increased twice but only if it doesn't exceed global defined maximum.
65a25b20	124	* Each function call will use last timeout value.
56b34bc6	125	*/
65a25b20	126	#define SDHCI_CMD_MAX_TIMEOUT 3200
d8ce77b2	127	#define SDHCI_CMD_DEFAULT_TIMEOUT 100
d90bb439	128	#define SDHCI_READ_STATUS_TIMEOUT 1000
56b34bc6	129
ef1e4eda SG	130	#ifdef CONFIG_DM_MMC_OPS
	131	static int sdhci_send_command(struct udevice dev, struct mmc_cmd cmd,
	132	struct mmc_data *data)
	133	{
	134	struct mmc *mmc = mmc_get_mmc_dev(dev);
	135
	136	#else
6588c78b	137	static int sdhci_send_command(struct mmc mmc, struct mmc_cmd cmd,
ef1e4eda	138	struct mmc_data *data)
af62a557	139	{
ef1e4eda	140	#endif
93bfd616	141	struct sdhci_host *host = mmc->priv;
af62a557 LW	142	unsigned int stat = 0;
	143	int ret = 0;
	144	int trans_bytes = 0, is_aligned = 1;
	145	u32 mask, flags, mode;
56b34bc6	146	unsigned int time = 0, start_addr = 0;
19d2e342	147	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
29905a45	148	unsigned start = get_timer(0);
af62a557	149
56b34bc6	150	/* Timeout unit - ms */
d8ce77b2	151	static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
af62a557 LW	152
	153	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	154	mask = SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT;
	155
	156	/* We shouldn't wait for data inihibit for stop commands, even
	157	though they might use busy signaling */
	158	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	159	mask &= ~SDHCI_DATA_INHIBIT;
	160
	161	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
56b34bc6	162	if (time >= cmd_timeout) {
30e6d979	163	printf("%s: MMC: %d busy ", __func__, mmc_dev);
65a25b20	164	if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
56b34bc6 PM	165	cmd_timeout += cmd_timeout;
	166	printf("timeout increasing to: %u ms.\n",
	167	cmd_timeout);
	168	} else {
	169	puts("timeout.\n");
915ffa52	170	return -ECOMM;
56b34bc6	171	}
af62a557	172	}
56b34bc6	173	time++;
af62a557 LW	174	udelay(1000);
	175	}
	176
	177	mask = SDHCI_INT_RESPONSE;
	178	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	179	flags = SDHCI_CMD_RESP_NONE;
	180	else if (cmd->resp_type & MMC_RSP_136)
	181	flags = SDHCI_CMD_RESP_LONG;
	182	else if (cmd->resp_type & MMC_RSP_BUSY) {
	183	flags = SDHCI_CMD_RESP_SHORT_BUSY;
17ea3c86 JC	184	if (data)
17ea3c86 JC	185	mask \|= SDHCI_INT_DATA_END;
af62a557 LW	186	} else
	187	flags = SDHCI_CMD_RESP_SHORT;
	188
	189	if (cmd->resp_type & MMC_RSP_CRC)
	190	flags \|= SDHCI_CMD_CRC;
	191	if (cmd->resp_type & MMC_RSP_OPCODE)
	192	flags \|= SDHCI_CMD_INDEX;
	193	if (data)
	194	flags \|= SDHCI_CMD_DATA;
	195
30e6d979	196	/* Set Transfer mode regarding to data flag */
af62a557 LW	197	if (data != 0) {
	198	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	199	mode = SDHCI_TRNS_BLK_CNT_EN;
	200	trans_bytes = data->blocks * data->blocksize;
	201	if (data->blocks > 1)
	202	mode \|= SDHCI_TRNS_MULTI;
	203
	204	if (data->flags == MMC_DATA_READ)
	205	mode \|= SDHCI_TRNS_READ;
	206
45a68fe2	207	#ifdef CONFIG_MMC_SDHCI_SDMA
af62a557	208	if (data->flags == MMC_DATA_READ)
3c1fcb77	209	start_addr = (unsigned long)data->dest;
af62a557	210	else
3c1fcb77	211	start_addr = (unsigned long)data->src;
af62a557 LW	212	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	213	(start_addr & 0x7) != 0x0) {
	214	is_aligned = 0;
3c1fcb77	215	start_addr = (unsigned long)aligned_buffer;
af62a557 LW	216	if (data->flags != MMC_DATA_READ)
	217	memcpy(aligned_buffer, data->src, trans_bytes);
	218	}
	219
492d3223 SR	220	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	221	/*
	222	* Always use this bounce-buffer when
	223	* CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
	224	*/
	225	is_aligned = 0;
	226	start_addr = (unsigned long)aligned_buffer;
	227	if (data->flags != MMC_DATA_READ)
	228	memcpy(aligned_buffer, data->src, trans_bytes);
	229	#endif
	230
af62a557 LW	231	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	232	mode \|= SDHCI_TRNS_DMA;
	233	#endif
	234	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
	235	data->blocksize),
	236	SDHCI_BLOCK_SIZE);
	237	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
	238	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
5e1c23cd KL	239	} else if (cmd->resp_type & MMC_RSP_BUSY) {
5e1c23cd KL	240	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
af62a557 LW	241	}
	242
	243	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
45a68fe2	244	#ifdef CONFIG_MMC_SDHCI_SDMA
be256cbf	245	trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
2c2ec4c9	246	flush_cache(start_addr, trans_bytes);
af62a557 LW	247	#endif
af62a557 LW	248	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
29905a45	249	start = get_timer(0);
af62a557 LW	250	do {
	251	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	252	if (stat & SDHCI_INT_ERROR)
	253	break;
af62a557	254
bae4a1fd MY	255	if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
	256	if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
	257	return 0;
	258	} else {
	259	printf("%s: Timeout for status update!\n",
	260	__func__);
915ffa52	261	return -ETIMEDOUT;
bae4a1fd	262	}
3a638320	263	}
bae4a1fd	264	} while ((stat & mask) != mask);
3a638320	265
af62a557 LW	266	if ((stat & (SDHCI_INT_ERROR \| mask)) == mask) {
	267	sdhci_cmd_done(host, cmd);
	268	sdhci_writel(host, mask, SDHCI_INT_STATUS);
	269	} else
	270	ret = -1;
	271
	272	if (!ret && data)
	273	ret = sdhci_transfer_data(host, data, start_addr);
	274
13243f2e TB	275	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
	276	udelay(1000);
	277
af62a557 LW	278	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	279	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	280	if (!ret) {
	281	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	282	!is_aligned && (data->flags == MMC_DATA_READ))
	283	memcpy(data->dest, aligned_buffer, trans_bytes);
	284	return 0;
	285	}
	286
	287	sdhci_reset(host, SDHCI_RESET_CMD);
	288	sdhci_reset(host, SDHCI_RESET_DATA);
	289	if (stat & SDHCI_INT_TIMEOUT)
915ffa52	290	return -ETIMEDOUT;
af62a557	291	else
915ffa52	292	return -ECOMM;
af62a557 LW	293	}
	294
	295	static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
	296	{
93bfd616	297	struct sdhci_host *host = mmc->priv;
6dffdbc3	298	unsigned int div, clk = 0, timeout, reg;
af62a557	299
79667b7b WY	300	/* Wait max 20 ms */
	301	timeout = 200;
	302	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
	303	(SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT)) {
	304	if (timeout == 0) {
	305	printf("%s: Timeout to wait cmd & data inhibit\n",
	306	__func__);
2cb5d67c	307	return -EBUSY;
79667b7b WY	308	}
	309
	310	timeout--;
	311	udelay(100);
	312	}
	313
	314	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1d405e20	315	reg &= ~(SDHCI_CLOCK_CARD_EN \| SDHCI_CLOCK_INT_EN);
79667b7b	316	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
af62a557 LW	317
	318	if (clock == 0)
	319	return 0;
	320
113e5dfc	321	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
6dffdbc3 WY	322	/*
	323	* Check if the Host Controller supports Programmable Clock
	324	* Mode.
	325	*/
	326	if (host->clk_mul) {
	327	for (div = 1; div <= 1024; div++) {
	328	if ((mmc->cfg->f_max * host->clk_mul / div)
	329	<= clock)
af62a557 LW	330	break;
af62a557 LW	331	}
6dffdbc3 WY	332
	333	/*
	334	* Set Programmable Clock Mode in the Clock
	335	* Control register.
	336	*/
	337	clk = SDHCI_PROG_CLOCK_MODE;
	338	div--;
	339	} else {
	340	/* Version 3.00 divisors must be a multiple of 2. */
	341	if (mmc->cfg->f_max <= clock) {
	342	div = 1;
	343	} else {
	344	for (div = 2;
	345	div < SDHCI_MAX_DIV_SPEC_300;
	346	div += 2) {
	347	if ((mmc->cfg->f_max / div) <= clock)
	348	break;
	349	}
	350	}
	351	div >>= 1;
af62a557 LW	352	}
	353	} else {
	354	/* Version 2.00 divisors must be a power of 2. */
	355	for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
93bfd616	356	if ((mmc->cfg->f_max / div) <= clock)
af62a557 LW	357	break;
af62a557 LW	358	}
6dffdbc3	359	div >>= 1;
af62a557	360	}
af62a557	361
b09ed6e4 JC	362	if (host->set_clock)
	363	host->set_clock(host->index, div);
	364
6dffdbc3	365	clk \|= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
af62a557 LW	366	clk \|= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
	367	<< SDHCI_DIVIDER_HI_SHIFT;
	368	clk \|= SDHCI_CLOCK_INT_EN;
	369	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	370
	371	/* Wait max 20 ms */
	372	timeout = 20;
	373	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	374	& SDHCI_CLOCK_INT_STABLE)) {
	375	if (timeout == 0) {
30e6d979 DR	376	printf("%s: Internal clock never stabilised.\n",
30e6d979 DR	377	__func__);
2cb5d67c	378	return -EBUSY;
af62a557 LW	379	}
	380	timeout--;
	381	udelay(1000);
	382	}
	383
	384	clk \|= SDHCI_CLOCK_CARD_EN;
	385	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	386	return 0;
	387	}
	388
	389	static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
	390	{
	391	u8 pwr = 0;
	392
	393	if (power != (unsigned short)-1) {
	394	switch (1 << power) {
	395	case MMC_VDD_165_195:
	396	pwr = SDHCI_POWER_180;
	397	break;
	398	case MMC_VDD_29_30:
	399	case MMC_VDD_30_31:
	400	pwr = SDHCI_POWER_300;
	401	break;
	402	case MMC_VDD_32_33:
	403	case MMC_VDD_33_34:
	404	pwr = SDHCI_POWER_330;
	405	break;
	406	}
	407	}
	408
	409	if (pwr == 0) {
	410	sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
	411	return;
	412	}
	413
688c2d14 MC	414	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
	415	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	416
af62a557 LW	417	pwr \|= SDHCI_POWER_ON;
	418
	419	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	420	}
	421
ef1e4eda SG	422	#ifdef CONFIG_DM_MMC_OPS
	423	static int sdhci_set_ios(struct udevice *dev)
	424	{
	425	struct mmc *mmc = mmc_get_mmc_dev(dev);
	426	#else
6588c78b	427	static void sdhci_set_ios(struct mmc *mmc)
af62a557	428	{
ef1e4eda	429	#endif
af62a557	430	u32 ctrl;
93bfd616	431	struct sdhci_host *host = mmc->priv;
af62a557	432
236bfecf JC	433	if (host->set_control_reg)
	434	host->set_control_reg(host);
	435
af62a557 LW	436	if (mmc->clock != host->clock)
	437	sdhci_set_clock(mmc, mmc->clock);
	438
	439	/* Set bus width */
	440	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	441	if (mmc->bus_width == 8) {
	442	ctrl &= ~SDHCI_CTRL_4BITBUS;
113e5dfc JC	443	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
113e5dfc JC	444	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	445	ctrl \|= SDHCI_CTRL_8BITBUS;
af62a557 LW	446	} else {
f88a429f MR	447	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
f88a429f MR	448	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	449	ctrl &= ~SDHCI_CTRL_8BITBUS;
	450	if (mmc->bus_width == 4)
	451	ctrl \|= SDHCI_CTRL_4BITBUS;
	452	else
	453	ctrl &= ~SDHCI_CTRL_4BITBUS;
	454	}
	455
	456	if (mmc->clock > 26000000)
	457	ctrl \|= SDHCI_CTRL_HISPD;
	458	else
	459	ctrl &= ~SDHCI_CTRL_HISPD;
	460
236bfecf JC	461	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
	462	ctrl &= ~SDHCI_CTRL_HISPD;
	463
af62a557	464	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
ef1e4eda SG	465	#ifdef CONFIG_DM_MMC_OPS
	466	return 0;
	467	#endif
af62a557 LW	468	}
af62a557 LW	469
6588c78b	470	static int sdhci_init(struct mmc *mmc)
af62a557	471	{
93bfd616	472	struct sdhci_host *host = mmc->priv;
af62a557	473
8d549b61 MY	474	sdhci_reset(host, SDHCI_RESET_ALL);
8d549b61 MY	475
af62a557 LW	476	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
	477	aligned_buffer = memalign(8, 512*1024);
	478	if (!aligned_buffer) {
30e6d979 DR	479	printf("%s: Aligned buffer alloc failed!!!\n",
30e6d979 DR	480	__func__);
2cb5d67c	481	return -ENOMEM;
af62a557 LW	482	}
	483	}
	484
93bfd616	485	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
470dcc75	486
6f88a3a5 JC	487	if (host->ops->get_cd)
6f88a3a5 JC	488	host->ops->get_cd(host);
470dcc75	489
ce0c1bc1	490	/* Enable only interrupts served by the SD controller */
30e6d979 DR	491	sdhci_writel(host, SDHCI_INT_DATA_MASK \| SDHCI_INT_CMD_MASK,
30e6d979 DR	492	SDHCI_INT_ENABLE);
ce0c1bc1 ŁM	493	/* Mask all sdhci interrupt sources */
ce0c1bc1 ŁM	494	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
af62a557	495
af62a557 LW	496	return 0;
	497	}
	498
ef1e4eda SG	499	#ifdef CONFIG_DM_MMC_OPS
	500	int sdhci_probe(struct udevice *dev)
	501	{
	502	struct mmc *mmc = mmc_get_mmc_dev(dev);
	503
	504	return sdhci_init(mmc);
	505	}
ab769f22	506
ef1e4eda SG	507	const struct dm_mmc_ops sdhci_ops = {
	508	.send_cmd = sdhci_send_command,
	509	.set_ios = sdhci_set_ios,
	510	};
	511	#else
ab769f22 PA	512	static const struct mmc_ops sdhci_ops = {
	513	.send_cmd = sdhci_send_command,
	514	.set_ios = sdhci_set_ios,
	515	.init = sdhci_init,
	516	};
ef1e4eda	517	#endif
ab769f22	518
14bed52d JC	519	int sdhci_setup_cfg(struct mmc_config cfg, struct sdhci_host host,
14bed52d JC	520	u32 max_clk, u32 min_clk)
af62a557	521	{
6dffdbc3	522	u32 caps, caps_1;
14bed52d JC	523
14bed52d JC	524	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
15bd0995	525
45a68fe2	526	#ifdef CONFIG_MMC_SDHCI_SDMA
15bd0995 MY	527	if (!(caps & SDHCI_CAN_DO_SDMA)) {
	528	printf("%s: Your controller doesn't support SDMA!!\n",
	529	__func__);
	530	return -EINVAL;
	531	}
	532	#endif
895549a2 JC	533	if (host->quirks & SDHCI_QUIRK_REG32_RW)
	534	host->version =
	535	sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
	536	else
	537	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
14bed52d JC	538
14bed52d JC	539	cfg->name = host->name;
2a809093 SG	540	#ifndef CONFIG_DM_MMC_OPS
2a809093 SG	541	cfg->ops = &sdhci_ops;
af62a557	542	#endif
af62a557	543	if (max_clk)
2a809093	544	cfg->f_max = max_clk;
af62a557	545	else {
14bed52d	546	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
2a809093 SG	547	cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
2a809093 SG	548	SDHCI_CLOCK_BASE_SHIFT;
af62a557	549	else
2a809093 SG	550	cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
	551	SDHCI_CLOCK_BASE_SHIFT;
	552	cfg->f_max *= 1000000;
af62a557	553	}
6c67954c MY	554	if (cfg->f_max == 0) {
	555	printf("%s: Hardware doesn't specify base clock frequency\n",
	556	__func__);
2a809093	557	return -EINVAL;
6c67954c	558	}
af62a557	559	if (min_clk)
2a809093	560	cfg->f_min = min_clk;
af62a557	561	else {
14bed52d	562	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
2a809093	563	cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
af62a557	564	else
2a809093	565	cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
af62a557	566	}
2a809093	567	cfg->voltages = 0;
af62a557	568	if (caps & SDHCI_CAN_VDD_330)
2a809093	569	cfg->voltages \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
af62a557	570	if (caps & SDHCI_CAN_VDD_300)
2a809093	571	cfg->voltages \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
af62a557	572	if (caps & SDHCI_CAN_VDD_180)
2a809093	573	cfg->voltages \|= MMC_VDD_165_195;
236bfecf	574
3137e645 MY	575	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
	576	cfg->voltages \|= host->voltages;
	577
2a809093	578	cfg->host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT;
14bed52d	579	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
ecd7b246 JC	580	if (!(caps & SDHCI_CAN_DO_8BIT))
ecd7b246 JC	581	cfg->host_caps &= ~MMC_MODE_8BIT;
1695b29a	582	}
42979002	583
14bed52d JC	584	if (host->host_caps)
14bed52d JC	585	cfg->host_caps \|= host->host_caps;
42979002	586
2a809093	587	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
93bfd616	588
6dffdbc3 WY	589	/*
	590	* In case of Host Controller v3.00, find out whether clock
	591	* multiplier is supported.
	592	*/
2a1bedaa JC	593	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
	594	caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	595	host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
	596	SDHCI_CLOCK_MUL_SHIFT;
	597	}
6dffdbc3	598
2a809093 SG	599	return 0;
	600	}
	601
ef1e4eda SG	602	#ifdef CONFIG_BLK
	603	int sdhci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg)
	604	{
	605	return mmc_bind(dev, mmc, cfg);
	606	}
	607	#else
2a809093 SG	608	int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
2a809093 SG	609	{
6c67954c MY	610	int ret;
6c67954c MY	611
6c67954c MY	612	ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
	613	if (ret)
	614	return ret;
2a809093	615
93bfd616 PA	616	host->mmc = mmc_create(&host->cfg, host);
	617	if (host->mmc == NULL) {
	618	printf("%s: mmc create fail!\n", __func__);
2cb5d67c	619	return -ENOMEM;
93bfd616	620	}
af62a557 LW	621
	622	return 0;
	623	}
ef1e4eda	624	#endif