[people/ms/u-boot.git] / drivers / mtd / nand / davinci_nand.c

/*
 * NAND driver for TI DaVinci based boards.
 *
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
 */

/*
 *
 * linux/drivers/mtd/nand/nand_davinci.c
 *
 * NAND Flash Driver
 *
 * Copyright (C) 2006 Texas Instruments.
 *
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ----------------------------------------------------------------------------
 *
 *  Overview:
 *   This is a device driver for the NAND flash device found on the
 *   DaVinci board which utilizes the Samsung k9k2g08 part.
 *
 Modifications:
 ver. 1.0: Feb 2005, Vinod/Sudhakar
 -
 *
 */

#include <common.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/emif_defs.h>

/* Definitions for 4-bit hardware ECC */
#define NAND_TIMEOUT			10240
#define NAND_ECC_BUSY			0xC
#define NAND_4BITECC_MASK		0x03FF03FF
#define EMIF_NANDFSR_ECC_STATE_MASK  	0x00000F00
#define ECC_STATE_NO_ERR		0x0
#define ECC_STATE_TOO_MANY_ERRS		0x1
#define ECC_STATE_ERR_CORR_COMP_P	0x2
#define ECC_STATE_ERR_CORR_COMP_N	0x3

/*
 * Exploit the little endianness of the ARM to do multi-byte transfers
 * per device read. This can perform over twice as quickly as individual
 * byte transfers when buffer alignment is conducive.
 *
 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
 * the address bus. On Davinci EVM platforms this has always been true.
 */
static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct nand_chip *chip = mtd->priv;
	const u32 *nand = chip->IO_ADDR_R;

	/* Make sure that buf is 32 bit aligned */
	if (((int)buf & 0x3) != 0) {
		if (((int)buf & 0x1) != 0) {
			if (len) {
				*buf = readb(nand);
				buf += 1;
				len--;
			}
		}

		if (((int)buf & 0x3) != 0) {
			if (len >= 2) {
				*(u16 *)buf = readw(nand);
				buf += 2;
				len -= 2;
			}
		}
	}

	/* copy aligned data */
	while (len >= 4) {
		*(u32 *)buf = __raw_readl(nand);
		buf += 4;
		len -= 4;
	}

	/* mop up any remaining bytes */
	if (len) {
		if (len >= 2) {
			*(u16 *)buf = readw(nand);
			buf += 2;
			len -= 2;
		}

		if (len)
			*buf = readb(nand);
	}
}

static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
				   int len)
{
	struct nand_chip *chip = mtd->priv;
	const u32 *nand = chip->IO_ADDR_W;

	/* Make sure that buf is 32 bit aligned */
	if (((int)buf & 0x3) != 0) {
		if (((int)buf & 0x1) != 0) {
			if (len) {
				writeb(*buf, nand);
				buf += 1;
				len--;
			}
		}

		if (((int)buf & 0x3) != 0) {
			if (len >= 2) {
				writew(*(u16 *)buf, nand);
				buf += 2;
				len -= 2;
			}
		}
	}

	/* copy aligned data */
	while (len >= 4) {
		__raw_writel(*(u32 *)buf, nand);
		buf += 4;
		len -= 4;
	}

	/* mop up any remaining bytes */
	if (len) {
		if (len >= 2) {
			writew(*(u16 *)buf, nand);
			buf += 2;
			len -= 2;
		}

		if (len)
			writeb(*buf, nand);
	}
}

static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
		unsigned int ctrl)
{
	struct		nand_chip *this = mtd->priv;
	u_int32_t	IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;

	if (ctrl & NAND_CTRL_CHANGE) {
		IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);

		if (ctrl & NAND_CLE)
			IO_ADDR_W |= MASK_CLE;
		if (ctrl & NAND_ALE)
			IO_ADDR_W |= MASK_ALE;
		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
	}

	if (cmd != NAND_CMD_NONE)
		writeb(cmd, IO_ADDR_W);
}

#ifdef CONFIG_SYS_NAND_HW_ECC

static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
	u_int32_t	val;

	(void)__raw_readl(&(davinci_emif_regs->nandfecc[
				CONFIG_SYS_NAND_CS - 2]));

	val = __raw_readl(&davinci_emif_regs->nandfcr);
	val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
	__raw_writel(val, &davinci_emif_regs->nandfcr);
}

static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
{
	u_int32_t	ecc = 0;

	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));

	return ecc;
}

static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
		u_char *ecc_code)
{
	u_int32_t		tmp;
	const int region = 1;

	tmp = nand_davinci_readecc(mtd, region);

	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
	 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
	tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);

	/* Invert so that erased block ECC is correct */
	tmp = ~tmp;

	*ecc_code++ = tmp;
	*ecc_code++ = tmp >>  8;
	*ecc_code++ = tmp >> 16;

	/* NOTE:  the above code matches mainline Linux:
	 *	.PQR.stu ==> ~PQRstu
	 *
	 * MontaVista/TI kernels encode those bytes differently, use
	 * complicated (and allegedly sometimes-wrong) correction code,
	 * and usually shipped with U-Boot that uses software ECC:
	 *	.PQR.stu ==> PsQRtu
	 *
	 * If you need MV/TI compatible NAND I/O in U-Boot, it should
	 * be possible to (a) change the mangling above, (b) reverse
	 * that mangling in nand_davinci_correct_data() below.
	 */

	return 0;
}

static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
		u_char *read_ecc, u_char *calc_ecc)
{
	struct nand_chip *this = mtd->priv;
	u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
					  (read_ecc[2] << 16);
	u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
					  (calc_ecc[2] << 16);
	u_int32_t diff = ecc_calc ^ ecc_nand;

	if (diff) {
		if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
			/* Correctable error */
			if ((diff >> (12 + 3)) < this->ecc.size) {
				uint8_t find_bit = 1 << ((diff >> 12) & 7);
				uint32_t find_byte = diff >> (12 + 3);

				dat[find_byte] ^= find_bit;
				MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
					 "bit ECC error at offset: %d, bit: "
					 "%d\n", find_byte, find_bit);
				return 1;
			} else {
				return -1;
			}
		} else if (!(diff & (diff - 1))) {
			/* Single bit ECC error in the ECC itself,
			   nothing to fix */
			MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
				 "ECC.\n");
			return 1;
		} else {
			/* Uncorrectable error */
			MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
			return -1;
		}
	}
	return 0;
}
#endif /* CONFIG_SYS_NAND_HW_ECC */

#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
#if defined(CONFIG_SYS_NAND_PAGE_2K)
	.eccbytes = 40,
	.eccpos = {
		24, 25, 26, 27, 28,
		29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
		39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
		49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
		59, 60, 61, 62, 63,
		},
	.oobfree = {
		{.offset = 2, .length = 22, },
	},
#elif defined(CONFIG_SYS_NAND_PAGE_4K)
	.eccbytes = 80,
	.eccpos = {
		48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
		58, 59, 60, 61, 62, 63,	64, 65, 66, 67,
		68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
		78, 79,	80, 81, 82, 83,	84, 85, 86, 87,
		88, 89, 90, 91, 92, 93,	94, 95, 96, 97,
		98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
		108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
		118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
		},
	.oobfree = {
		{.offset = 2, .length = 46, },
	},
#endif
};

static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
{
	u32 val;

	switch (mode) {
	case NAND_ECC_WRITE:
	case NAND_ECC_READ:
		/*
		 * Start a new ECC calculation for reading or writing 512 bytes
		 * of data.
		 */
		val = __raw_readl(&davinci_emif_regs->nandfcr);
		val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
		val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
		val |= DAVINCI_NANDFCR_4BIT_ECC_START;
		__raw_writel(val, &davinci_emif_regs->nandfcr);
		break;
	case NAND_ECC_READSYN:
		val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
		break;
	default:
		break;
	}
}

static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
{
	int i;

	for (i = 0; i < 4; i++) {
		ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
			NAND_4BITECC_MASK;
	}

	return 0;
}

static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
					   const uint8_t *dat,
					   uint8_t *ecc_code)
{
	unsigned int hw_4ecc[4];
	unsigned int i;

	nand_davinci_4bit_readecc(mtd, hw_4ecc);

	/*Convert 10 bit ecc value to 8 bit */
	for (i = 0; i < 2; i++) {
		unsigned int hw_ecc_low = hw_4ecc[i * 2];
		unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];

		/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
		*ecc_code++ = hw_ecc_low & 0xFF;

		/*
		 * Take 2 bits as LSB bits from val1 (count1=0) or val5
		 * (count1=1) and 6 bits from val2 (count1=0) or
		 * val5 (count1=1)
		 */
		*ecc_code++ =
		    ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);

		/*
		 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
		 * 4 bits from val3 (count1=0) or val6 (count1=1)
		 */
		*ecc_code++ =
		    ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);

		/*
		 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
		 * 2 bits from val4 (count1=0) or  val7 (count1=1)
		 */
		*ecc_code++ =
		    ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);

		/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
		*ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
	}

	return 0;
}

static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
					  uint8_t *read_ecc, uint8_t *calc_ecc)
{
	int i;
	unsigned int hw_4ecc[4];
	unsigned int iserror;
	unsigned short *ecc16;
	unsigned int numerrors, erroraddress, errorvalue;
	u32 val;

	/*
	 * Check for an ECC where all bytes are 0xFF.  If this is the case, we
	 * will assume we are looking at an erased page and we should ignore
	 * the ECC.
	 */
	for (i = 0; i < 10; i++) {
		if (read_ecc[i] != 0xFF)
			break;
	}
	if (i == 10)
		return 0;

	/* Convert 8 bit in to 10 bit */
	ecc16 = (unsigned short *)&read_ecc[0];

	/*
	 * Write the parity values in the NAND Flash 4-bit ECC Load register.
	 * Write each parity value one at a time starting from 4bit_ecc_val8
	 * to 4bit_ecc_val1.
	 */

	/*Take 2 bits from 8th byte and 8 bits from 9th byte */
	__raw_writel(((ecc16[4]) >> 6) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
	__raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
			&davinci_emif_regs->nand4biteccload);

	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
	__raw_writel((ecc16[3] >> 2) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
	__raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
			&davinci_emif_regs->nand4biteccload);

	/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
	__raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
			&davinci_emif_regs->nand4biteccload);

	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
	__raw_writel(((ecc16[1]) >> 4) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
	__raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
			&davinci_emif_regs->nand4biteccload);

	/* Take 10 bits from 0th and 1st bytes */
	__raw_writel((ecc16[0]) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/*
	 * Perform a dummy read to the EMIF Revision Code and Status register.
	 * This is required to ensure time for syndrome calculation after
	 * writing the ECC values in previous step.
	 */

	val = __raw_readl(&davinci_emif_regs->nandfsr);

	/*
	 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
	 * A syndrome value of 0 means no bit errors. If the syndrome is
	 * non-zero then go further otherwise return.
	 */
	nand_davinci_4bit_readecc(mtd, hw_4ecc);

	if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
		return 0;

	/*
	 * Clear any previous address calculation by doing a dummy read of an
	 * error address register.
	 */
	val = __raw_readl(&davinci_emif_regs->nanderradd1);

	/*
	 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
	 * register to 1.
	 */
	__raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
			&davinci_emif_regs->nandfcr);

	/*
	 * Wait for the corr_state field (bits 8 to 11) in the
	 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
	 * Otherwise ECC calculation has not even begun and the next loop might
	 * fail because of a false positive!
	 */
	i = NAND_TIMEOUT;
	do {
		val = __raw_readl(&davinci_emif_regs->nandfsr);
		val &= 0xc00;
		i--;
	} while ((i > 0) && !val);

	/*
	 * Wait for the corr_state field (bits 8 to 11) in the
	 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
	 */
	i = NAND_TIMEOUT;
	do {
		val = __raw_readl(&davinci_emif_regs->nandfsr);
		val &= 0xc00;
		i--;
	} while ((i > 0) && val);

	iserror = __raw_readl(&davinci_emif_regs->nandfsr);
	iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
	iserror = iserror >> 8;

	/*
	 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
	 * corrected (five or more errors).  The number of errors
	 * calculated (err_num field) differs from the number of errors
	 * searched.  ECC_STATE_ERR_CORR_COMP_P (0x2) means error
	 * correction complete (errors on bit 8 or 9).
	 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
	 * complete (error exists).
	 */

	if (iserror == ECC_STATE_NO_ERR) {
		val = __raw_readl(&davinci_emif_regs->nanderrval1);
		return 0;
	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
		val = __raw_readl(&davinci_emif_regs->nanderrval1);
		return -1;
	}

	numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
			& 0x3) + 1;

	/* Read the error address, error value and correct */
	for (i = 0; i < numerrors; i++) {
		if (i > 1) {
			erroraddress =
			    ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
			      (16 * (i & 1))) & 0x3FF);
			erroraddress = ((512 + 7) - erroraddress);
			errorvalue =
			    ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
			      (16 * (i & 1))) & 0xFF);
		} else {
			erroraddress =
			    ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
			      (16 * (i & 1))) & 0x3FF);
			erroraddress = ((512 + 7) - erroraddress);
			errorvalue =
			    ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
			      (16 * (i & 1))) & 0xFF);
		}
		/* xor the corrupt data with error value */
		if (erroraddress < 512)
			dat[erroraddress] ^= errorvalue;
	}

	return numerrors;
}
#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */

static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
	return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
}

static void nand_flash_init(void)
{
	/* This is for DM6446 EVM and *very* similar.  DO NOT GROW THIS!
	 * Instead, have your board_init() set EMIF timings, based on its
	 * knowledge of the clocks and what devices are hooked up ... and
	 * don't even do that unless no UBL handled it.
	 */
#ifdef CONFIG_SOC_DM644X
	u_int32_t	acfg1 = 0x3ffffffc;

	/*------------------------------------------------------------------*
	 *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
	 *                                                                  *
	 *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
	 *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
	 *                                                                  *
	 *------------------------------------------------------------------*/
	 acfg1 = 0
		| (0 << 31)	/* selectStrobe */
		| (0 << 30)	/* extWait */
		| (1 << 26)	/* writeSetup	10 ns */
		| (3 << 20)	/* writeStrobe	40 ns */
		| (1 << 17)	/* writeHold	10 ns */
		| (1 << 13)	/* readSetup	10 ns */
		| (5 << 7)	/* readStrobe	60 ns */
		| (1 << 4)	/* readHold	10 ns */
		| (3 << 2)	/* turnAround	?? ns */
		| (0 << 0)	/* asyncSize	8-bit bus */
		;

	__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */

	/* NAND flash on CS2 */
	__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
#endif
}

void davinci_nand_init(struct nand_chip *nand)
{
	nand->chip_delay  = 0;
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
	nand->options	  |= NAND_USE_FLASH_BBT;
#endif
#ifdef CONFIG_SYS_NAND_HW_ECC
	nand->ecc.mode = NAND_ECC_HW;
	nand->ecc.size = 512;
	nand->ecc.bytes = 3;
	nand->ecc.calculate = nand_davinci_calculate_ecc;
	nand->ecc.correct  = nand_davinci_correct_data;
	nand->ecc.hwctl  = nand_davinci_enable_hwecc;
#else
	nand->ecc.mode = NAND_ECC_SOFT;
#endif /* CONFIG_SYS_NAND_HW_ECC */
#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
	nand->ecc.size = 512;
	nand->ecc.bytes = 10;
	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
	nand->ecc.correct = nand_davinci_4bit_correct_data;
	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
#endif
	/* Set address of hardware control function */
	nand->cmd_ctrl = nand_davinci_hwcontrol;

	nand->read_buf = nand_davinci_read_buf;
	nand->write_buf = nand_davinci_write_buf;

	nand->dev_ready = nand_davinci_dev_ready;

	nand_flash_init();
}

int board_nand_init(struct nand_chip *chip) __attribute__((weak));

int board_nand_init(struct nand_chip *chip)
{
	davinci_nand_init(chip);
	return 0;
}
Commit	Line	Data
c74b2108 SK	1	/*
	2	* NAND driver for TI DaVinci based boards.
	3	*
	4	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	5	*
	6	* Based on Linux DaVinci NAND driver by TI. Original copyright follows:
	7	*/
	8
	9	/*
	10	*
	11	* linux/drivers/mtd/nand/nand_davinci.c
	12	*
	13	* NAND Flash Driver
	14	*
	15	* Copyright (C) 2006 Texas Instruments.
	16	*
	17	* ----------------------------------------------------------------------------
	18	*
	19	* This program is free software; you can redistribute it and/or modify
	20	* it under the terms of the GNU General Public License as published by
	21	* the Free Software Foundation; either version 2 of the License, or
	22	* (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	32	* ----------------------------------------------------------------------------
	33	*
	34	* Overview:
	35	* This is a device driver for the NAND flash device found on the
	36	* DaVinci board which utilizes the Samsung k9k2g08 part.
	37	*
	38	Modifications:
	39	ver. 1.0: Feb 2005, Vinod/Sudhakar
	40	-
	41	*
	42	*/
	43
	44	#include <common.h>
cfa460ad	45	#include <asm/io.h>
c74b2108 SK	46	#include <nand.h>
	47	#include <asm/arch/nand_defs.h>
	48	#include <asm/arch/emif_defs.h>
	49
77b351cd SP	50	/* Definitions for 4-bit hardware ECC */
	51	#define NAND_TIMEOUT 10240
	52	#define NAND_ECC_BUSY 0xC
	53	#define NAND_4BITECC_MASK 0x03FF03FF
	54	#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
	55	#define ECC_STATE_NO_ERR 0x0
	56	#define ECC_STATE_TOO_MANY_ERRS 0x1
	57	#define ECC_STATE_ERR_CORR_COMP_P 0x2
	58	#define ECC_STATE_ERR_CORR_COMP_N 0x3
	59
20da6f4d NT	60	/*
	61	* Exploit the little endianness of the ARM to do multi-byte transfers
	62	* per device read. This can perform over twice as quickly as individual
	63	* byte transfers when buffer alignment is conducive.
	64	*
	65	* NOTE: This only works if the NAND is not connected to the 2 LSBs of
	66	* the address bus. On Davinci EVM platforms this has always been true.
	67	*/
	68	static void nand_davinci_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	69	{
	70	struct nand_chip *chip = mtd->priv;
	71	const u32 *nand = chip->IO_ADDR_R;
	72
	73	/* Make sure that buf is 32 bit aligned */
	74	if (((int)buf & 0x3) != 0) {
	75	if (((int)buf & 0x1) != 0) {
	76	if (len) {
	77	*buf = readb(nand);
	78	buf += 1;
	79	len--;
	80	}
	81	}
	82
	83	if (((int)buf & 0x3) != 0) {
	84	if (len >= 2) {
	85	(u16 )buf = readw(nand);
	86	buf += 2;
	87	len -= 2;
	88	}
	89	}
	90	}
	91
	92	/* copy aligned data */
	93	while (len >= 4) {
cc41a59a	94	(u32 )buf = __raw_readl(nand);
20da6f4d NT	95	buf += 4;
	96	len -= 4;
	97	}
	98
	99	/* mop up any remaining bytes */
	100	if (len) {
	101	if (len >= 2) {
	102	(u16 )buf = readw(nand);
	103	buf += 2;
	104	len -= 2;
	105	}
	106
	107	if (len)
	108	*buf = readb(nand);
	109	}
	110	}
	111
	112	static void nand_davinci_write_buf(struct mtd_info mtd, const uint8_t buf,
	113	int len)
	114	{
	115	struct nand_chip *chip = mtd->priv;
	116	const u32 *nand = chip->IO_ADDR_W;
	117
	118	/* Make sure that buf is 32 bit aligned */
	119	if (((int)buf & 0x3) != 0) {
	120	if (((int)buf & 0x1) != 0) {
	121	if (len) {
	122	writeb(*buf, nand);
	123	buf += 1;
	124	len--;
	125	}
	126	}
	127
	128	if (((int)buf & 0x3) != 0) {
	129	if (len >= 2) {
	130	writew((u16 )buf, nand);
	131	buf += 2;
	132	len -= 2;
	133	}
	134	}
	135	}
	136
	137	/* copy aligned data */
	138	while (len >= 4) {
cc41a59a	139	__raw_writel((u32 )buf, nand);
20da6f4d NT	140	buf += 4;
	141	len -= 4;
	142	}
	143
	144	/* mop up any remaining bytes */
	145	if (len) {
	146	if (len >= 2) {
	147	writew((u16 )buf, nand);
	148	buf += 2;
	149	len -= 2;
	150	}
	151
	152	if (len)
	153	writeb(*buf, nand);
	154	}
	155	}
	156
cc41a59a CC	157	static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
cc41a59a CC	158	unsigned int ctrl)
c74b2108 SK	159	{
	160	struct nand_chip *this = mtd->priv;
	161	u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
	162
cfa460ad	163	if (ctrl & NAND_CTRL_CHANGE) {
20da6f4d NT	164	IO_ADDR_W &= ~(MASK_ALE\|MASK_CLE);
20da6f4d NT	165
cc41a59a	166	if (ctrl & NAND_CLE)
c74b2108	167	IO_ADDR_W \|= MASK_CLE;
cc41a59a	168	if (ctrl & NAND_ALE)
c74b2108	169	IO_ADDR_W \|= MASK_ALE;
cfa460ad	170	this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
c74b2108 SK	171	}
c74b2108 SK	172
5e1dae5c	173	if (cmd != NAND_CMD_NONE)
20da6f4d	174	writeb(cmd, IO_ADDR_W);
c74b2108 SK	175	}
c74b2108 SK	176
6d0f6bcf	177	#ifdef CONFIG_SYS_NAND_HW_ECC
c74b2108 SK	178
	179	static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
	180	{
97f4eb8c	181	u_int32_t val;
c74b2108	182
cc41a59a CC	183	(void)__raw_readl(&(davinci_emif_regs->nandfecc[
cc41a59a CC	184	CONFIG_SYS_NAND_CS - 2]));
c74b2108	185
cc41a59a	186	val = __raw_readl(&davinci_emif_regs->nandfcr);
26be2c53	187	val \|= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
97f4eb8c	188	val \|= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
cc41a59a	189	__raw_writel(val, &davinci_emif_regs->nandfcr);
c74b2108 SK	190	}
	191
	192	static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
	193	{
	194	u_int32_t ecc = 0;
c74b2108	195
cc41a59a	196	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
c74b2108	197
cc41a59a	198	return ecc;
c74b2108 SK	199	}
c74b2108 SK	200
cc41a59a CC	201	static int nand_davinci_calculate_ecc(struct mtd_info mtd, const u_char dat,
cc41a59a CC	202	u_char *ecc_code)
c74b2108 SK	203	{
c74b2108 SK	204	u_int32_t tmp;
9b05aa78 HV	205	const int region = 1;
	206
	207	tmp = nand_davinci_readecc(mtd, region);
	208
	209	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
	210	* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
	211	tmp = (tmp & 0x00000fff) \| ((tmp & 0x0fff0000) >> 4);
	212
	213	/* Invert so that erased block ECC is correct */
	214	tmp = ~tmp;
	215
	216	*ecc_code++ = tmp;
	217	*ecc_code++ = tmp >> 8;
	218	*ecc_code++ = tmp >> 16;
c74b2108	219
6e29ed8e DB	220	/* NOTE: the above code matches mainline Linux:
	221	* .PQR.stu ==> ~PQRstu
	222	*
	223	* MontaVista/TI kernels encode those bytes differently, use
	224	* complicated (and allegedly sometimes-wrong) correction code,
	225	* and usually shipped with U-Boot that uses software ECC:
	226	* .PQR.stu ==> PsQRtu
	227	*
	228	* If you need MV/TI compatible NAND I/O in U-Boot, it should
	229	* be possible to (a) change the mangling above, (b) reverse
	230	* that mangling in nand_davinci_correct_data() below.
	231	*/
c74b2108	232
6e29ed8e	233	return 0;
c74b2108 SK	234	}
c74b2108 SK	235
cc41a59a CC	236	static int nand_davinci_correct_data(struct mtd_info mtd, u_char dat,
cc41a59a CC	237	u_char read_ecc, u_char calc_ecc)
c74b2108	238	{
9b05aa78	239	struct nand_chip *this = mtd->priv;
9b05aa78 HV	240	u_int32_t ecc_nand = read_ecc[0] \| (read_ecc[1] << 8) \|
	241	(read_ecc[2] << 16);
	242	u_int32_t ecc_calc = calc_ecc[0] \| (calc_ecc[1] << 8) \|
	243	(calc_ecc[2] << 16);
	244	u_int32_t diff = ecc_calc ^ ecc_nand;
	245
	246	if (diff) {
	247	if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
	248	/* Correctable error */
	249	if ((diff >> (12 + 3)) < this->ecc.size) {
	250	uint8_t find_bit = 1 << ((diff >> 12) & 7);
	251	uint32_t find_byte = diff >> (12 + 3);
	252
	253	dat[find_byte] ^= find_bit;
	254	MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
	255	"bit ECC error at offset: %d, bit: "
	256	"%d\n", find_byte, find_bit);
	257	return 1;
	258	} else {
	259	return -1;
	260	}
	261	} else if (!(diff & (diff - 1))) {
	262	/* Single bit ECC error in the ECC itself,
	263	nothing to fix */
	264	MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
	265	"ECC.\n");
	266	return 1;
	267	} else {
	268	/* Uncorrectable error */
	269	MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
	270	return -1;
	271	}
	272	}
cc41a59a	273	return 0;
c74b2108	274	}
6d0f6bcf	275	#endif /* CONFIG_SYS_NAND_HW_ECC */
c74b2108	276
77b351cd SP	277	#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
77b351cd SP	278	static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
10a5a799	279	#if defined(CONFIG_SYS_NAND_PAGE_2K)
77b351cd SP	280	.eccbytes = 40,
	281	.eccpos = {
	282	24, 25, 26, 27, 28,
	283	29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
	284	39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
	285	49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
	286	59, 60, 61, 62, 63,
	287	},
	288	.oobfree = {
	289	{.offset = 2, .length = 22, },
	290	},
10a5a799 SP	291	#elif defined(CONFIG_SYS_NAND_PAGE_4K)
	292	.eccbytes = 80,
	293	.eccpos = {
	294	48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
	295	58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
	296	68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
	297	78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
	298	88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
	299	98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
	300	108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
	301	118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
	302	},
	303	.oobfree = {
	304	{.offset = 2, .length = 46, },
	305	},
77b351cd SP	306	#endif
77b351cd SP	307	};
77b351cd SP	308
	309	static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
	310	{
	311	u32 val;
	312
	313	switch (mode) {
	314	case NAND_ECC_WRITE:
	315	case NAND_ECC_READ:
	316	/*
	317	* Start a new ECC calculation for reading or writing 512 bytes
	318	* of data.
	319	*/
cc41a59a	320	val = __raw_readl(&davinci_emif_regs->nandfcr);
97f4eb8c	321	val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
26be2c53	322	val \|= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
97f4eb8c NT	323	val \|= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
97f4eb8c NT	324	val \|= DAVINCI_NANDFCR_4BIT_ECC_START;
cc41a59a	325	__raw_writel(val, &davinci_emif_regs->nandfcr);
77b351cd SP	326	break;
77b351cd SP	327	case NAND_ECC_READSYN:
cc41a59a	328	val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
77b351cd SP	329	break;
	330	default:
	331	break;
	332	}
	333	}
	334
	335	static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
	336	{
cc41a59a CC	337	int i;
	338
	339	for (i = 0; i < 4; i++) {
	340	ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
	341	NAND_4BITECC_MASK;
	342	}
77b351cd SP	343
	344	return 0;
	345	}
	346
	347	static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
	348	const uint8_t *dat,
	349	uint8_t *ecc_code)
	350	{
20da6f4d NT	351	unsigned int hw_4ecc[4];
20da6f4d NT	352	unsigned int i;
77b351cd SP	353
	354	nand_davinci_4bit_readecc(mtd, hw_4ecc);
	355
	356	/Convert 10 bit ecc value to 8 bit /
20da6f4d NT	357	for (i = 0; i < 2; i++) {
	358	unsigned int hw_ecc_low = hw_4ecc[i * 2];
	359	unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
77b351cd SP	360
77b351cd SP	361	/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
20da6f4d	362	*ecc_code++ = hw_ecc_low & 0xFF;
77b351cd SP	363
	364	/*
	365	* Take 2 bits as LSB bits from val1 (count1=0) or val5
	366	* (count1=1) and 6 bits from val2 (count1=0) or
	367	* val5 (count1=1)
	368	*/
20da6f4d NT	369	*ecc_code++ =
20da6f4d NT	370	((hw_ecc_low >> 8) & 0x3) \| ((hw_ecc_low >> 14) & 0xFC);
77b351cd SP	371
	372	/*
	373	* Take 4 bits from val2 (count1=0) or val5 (count1=1) and
	374	* 4 bits from val3 (count1=0) or val6 (count1=1)
	375	*/
20da6f4d NT	376	*ecc_code++ =
20da6f4d NT	377	((hw_ecc_low >> 22) & 0xF) \| ((hw_ecc_hi << 4) & 0xF0);
77b351cd SP	378
	379	/*
	380	* Take 6 bits from val3(count1=0) or val6 (count1=1) and
	381	* 2 bits from val4 (count1=0) or val7 (count1=1)
	382	*/
20da6f4d NT	383	*ecc_code++ =
20da6f4d NT	384	((hw_ecc_hi >> 4) & 0x3F) \| ((hw_ecc_hi >> 10) & 0xC0);
77b351cd SP	385
77b351cd SP	386	/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
20da6f4d	387	*ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
77b351cd	388	}
20da6f4d	389
77b351cd SP	390	return 0;
	391	}
	392
77b351cd SP	393	static int nand_davinci_4bit_correct_data(struct mtd_info mtd, uint8_t dat,
	394	uint8_t read_ecc, uint8_t calc_ecc)
	395	{
77b351cd	396	int i;
20da6f4d NT	397	unsigned int hw_4ecc[4];
	398	unsigned int iserror;
	399	unsigned short *ecc16;
77b351cd SP	400	unsigned int numerrors, erroraddress, errorvalue;
	401	u32 val;
	402
	403	/*
	404	* Check for an ECC where all bytes are 0xFF. If this is the case, we
	405	* will assume we are looking at an erased page and we should ignore
	406	* the ECC.
	407	*/
	408	for (i = 0; i < 10; i++) {
	409	if (read_ecc[i] != 0xFF)
	410	break;
	411	}
	412	if (i == 10)
	413	return 0;
	414
	415	/* Convert 8 bit in to 10 bit */
20da6f4d	416	ecc16 = (unsigned short *)&read_ecc[0];
77b351cd	417
20da6f4d NT	418	/*
	419	* Write the parity values in the NAND Flash 4-bit ECC Load register.
	420	* Write each parity value one at a time starting from 4bit_ecc_val8
	421	* to 4bit_ecc_val1.
	422	*/
77b351cd	423
20da6f4d	424	/Take 2 bits from 8th byte and 8 bits from 9th byte /
cc41a59a CC	425	__raw_writel(((ecc16[4]) >> 6) & 0x3FF,
cc41a59a CC	426	&davinci_emif_regs->nand4biteccload);
77b351cd	427
20da6f4d	428	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
cc41a59a CC	429	__raw_writel((((ecc16[3]) >> 12) & 0xF) \| ((((ecc16[4])) << 4) & 0x3F0),
cc41a59a CC	430	&davinci_emif_regs->nand4biteccload);
77b351cd	431
20da6f4d	432	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
cc41a59a CC	433	__raw_writel((ecc16[3] >> 2) & 0x3FF,
cc41a59a CC	434	&davinci_emif_regs->nand4biteccload);
77b351cd SP	435
77b351cd SP	436	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
cc41a59a CC	437	__raw_writel(((ecc16[2]) >> 8) \| ((((ecc16[3])) << 8) & 0x300),
cc41a59a CC	438	&davinci_emif_regs->nand4biteccload);
77b351cd	439
20da6f4d	440	/Take 2 bits from 3rd byte and 8 bits from 4th byte /
cc41a59a CC	441	__raw_writel((((ecc16[1]) >> 14) & 0x3) \| ((((ecc16[2])) << 2) & 0x3FC),
cc41a59a CC	442	&davinci_emif_regs->nand4biteccload);
77b351cd	443
20da6f4d	444	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
cc41a59a CC	445	__raw_writel(((ecc16[1]) >> 4) & 0x3FF,
cc41a59a CC	446	&davinci_emif_regs->nand4biteccload);
77b351cd	447
20da6f4d	448	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
cc41a59a CC	449	__raw_writel((((ecc16[0]) >> 10) & 0x3F) \| (((ecc16[1]) << 6) & 0x3C0),
cc41a59a CC	450	&davinci_emif_regs->nand4biteccload);
77b351cd	451
20da6f4d	452	/* Take 10 bits from 0th and 1st bytes */
cc41a59a CC	453	__raw_writel((ecc16[0]) & 0x3FF,
cc41a59a CC	454	&davinci_emif_regs->nand4biteccload);
77b351cd SP	455
	456	/*
	457	* Perform a dummy read to the EMIF Revision Code and Status register.
	458	* This is required to ensure time for syndrome calculation after
	459	* writing the ECC values in previous step.
	460	*/
	461
cc41a59a	462	val = __raw_readl(&davinci_emif_regs->nandfsr);
77b351cd SP	463
	464	/*
	465	* Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
	466	* A syndrome value of 0 means no bit errors. If the syndrome is
	467	* non-zero then go further otherwise return.
	468	*/
	469	nand_davinci_4bit_readecc(mtd, hw_4ecc);
	470
20da6f4d	471	if (!(hw_4ecc[0] \| hw_4ecc[1] \| hw_4ecc[2] \| hw_4ecc[3]))
77b351cd SP	472	return 0;
	473
	474	/*
	475	* Clear any previous address calculation by doing a dummy read of an
	476	* error address register.
	477	*/
cc41a59a	478	val = __raw_readl(&davinci_emif_regs->nanderradd1);
77b351cd SP	479
	480	/*
	481	* Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
	482	* register to 1.
	483	*/
10d6ac94 BG	484	__raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
10d6ac94 BG	485	&davinci_emif_regs->nandfcr);
77b351cd SP	486
77b351cd SP	487	/*
1075b07e WS	488	* Wait for the corr_state field (bits 8 to 11) in the
	489	* NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
	490	* Otherwise ECC calculation has not even begun and the next loop might
	491	* fail because of a false positive!
	492	*/
	493	i = NAND_TIMEOUT;
	494	do {
	495	val = __raw_readl(&davinci_emif_regs->nandfsr);
	496	val &= 0xc00;
	497	i--;
	498	} while ((i > 0) && !val);
	499
	500	/*
	501	* Wait for the corr_state field (bits 8 to 11) in the
77b351cd SP	502	* NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
	503	*/
	504	i = NAND_TIMEOUT;
	505	do {
cc41a59a	506	val = __raw_readl(&davinci_emif_regs->nandfsr);
77b351cd SP	507	val &= 0xc00;
	508	i--;
	509	} while ((i > 0) && val);
	510
cc41a59a	511	iserror = __raw_readl(&davinci_emif_regs->nandfsr);
77b351cd SP	512	iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
	513	iserror = iserror >> 8;
	514
	515	/*
	516	* ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
	517	* corrected (five or more errors). The number of errors
	518	* calculated (err_num field) differs from the number of errors
	519	* searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
	520	* correction complete (errors on bit 8 or 9).
	521	* ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
	522	* complete (error exists).
	523	*/
	524
	525	if (iserror == ECC_STATE_NO_ERR) {
cc41a59a	526	val = __raw_readl(&davinci_emif_regs->nanderrval1);
77b351cd SP	527	return 0;
77b351cd SP	528	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
cc41a59a	529	val = __raw_readl(&davinci_emif_regs->nanderrval1);
77b351cd SP	530	return -1;
	531	}
	532
cc41a59a CC	533	numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
cc41a59a CC	534	& 0x3) + 1;
77b351cd SP	535
	536	/* Read the error address, error value and correct */
	537	for (i = 0; i < numerrors; i++) {
	538	if (i > 1) {
	539	erroraddress =
cc41a59a	540	((__raw_readl(&davinci_emif_regs->nanderradd2) >>
77b351cd SP	541	(16 * (i & 1))) & 0x3FF);
	542	erroraddress = ((512 + 7) - erroraddress);
	543	errorvalue =
cc41a59a	544	((__raw_readl(&davinci_emif_regs->nanderrval2) >>
77b351cd SP	545	(16 * (i & 1))) & 0xFF);
	546	} else {
	547	erroraddress =
cc41a59a	548	((__raw_readl(&davinci_emif_regs->nanderradd1) >>
77b351cd SP	549	(16 * (i & 1))) & 0x3FF);
	550	erroraddress = ((512 + 7) - erroraddress);
	551	errorvalue =
cc41a59a	552	((__raw_readl(&davinci_emif_regs->nanderrval1) >>
77b351cd SP	553	(16 * (i & 1))) & 0xFF);
	554	}
	555	/* xor the corrupt data with error value */
	556	if (erroraddress < 512)
	557	dat[erroraddress] ^= errorvalue;
	558	}
	559
	560	return numerrors;
	561	}
d44e9c17	562	#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
77b351cd	563
c74b2108 SK	564	static int nand_davinci_dev_ready(struct mtd_info *mtd)
c74b2108 SK	565	{
cc41a59a	566	return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
c74b2108 SK	567	}
	568
	569	static void nand_flash_init(void)
	570	{
fcb77477 DB	571	/* This is for DM6446 EVM and very similar. DO NOT GROW THIS!
	572	* Instead, have your board_init() set EMIF timings, based on its
	573	* knowledge of the clocks and what devices are hooked up ... and
	574	* don't even do that unless no UBL handled it.
	575	*/
ed727d39	576	#ifdef CONFIG_SOC_DM644X
950a3924	577	u_int32_t acfg1 = 0x3ffffffc;
950a3924 WD	578
	579	/------------------------------------------------------------------
	580	* NAND FLASH CHIP TIMEOUT @ 459 MHz *
	581	* *
	582	* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
	583	* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
	584	* *
	585	------------------------------------------------------------------/
	586	acfg1 = 0
cc41a59a CC	587	\| (0 << 31) /* selectStrobe */
	588	\| (0 << 30) /* extWait */
	589	\| (1 << 26) /* writeSetup 10 ns */
	590	\| (3 << 20) /* writeStrobe 40 ns */
	591	\| (1 << 17) /* writeHold 10 ns */
	592	\| (1 << 13) /* readSetup 10 ns */
	593	\| (5 << 7) /* readStrobe 60 ns */
	594	\| (1 << 4) /* readHold 10 ns */
	595	\| (3 << 2) /* turnAround ?? ns */
	596	\| (0 << 0) /* asyncSize 8-bit bus */
53677ef1	597	;
950a3924	598
cc41a59a	599	__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
d583ef51	600
cc41a59a CC	601	/* NAND flash on CS2 */
cc41a59a CC	602	__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
fcb77477	603	#endif
c74b2108 SK	604	}
c74b2108 SK	605
154b5484	606	void davinci_nand_init(struct nand_chip *nand)
c74b2108	607	{
c74b2108	608	nand->chip_delay = 0;
6d0f6bcf	609	#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
77b351cd	610	nand->options \|= NAND_USE_FLASH_BBT;
c74b2108	611	#endif
6d0f6bcf	612	#ifdef CONFIG_SYS_NAND_HW_ECC
5e1dae5c	613	nand->ecc.mode = NAND_ECC_HW;
9b05aa78 HV	614	nand->ecc.size = 512;
9b05aa78 HV	615	nand->ecc.bytes = 3;
cfa460ad WJ	616	nand->ecc.calculate = nand_davinci_calculate_ecc;
cfa460ad WJ	617	nand->ecc.correct = nand_davinci_correct_data;
4cbb651b	618	nand->ecc.hwctl = nand_davinci_enable_hwecc;
c74b2108	619	#else
5e1dae5c	620	nand->ecc.mode = NAND_ECC_SOFT;
6d0f6bcf	621	#endif /* CONFIG_SYS_NAND_HW_ECC */
77b351cd SP	622	#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	623	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
	624	nand->ecc.size = 512;
	625	nand->ecc.bytes = 10;
	626	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
	627	nand->ecc.correct = nand_davinci_4bit_correct_data;
	628	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
	629	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
	630	#endif
c74b2108	631	/* Set address of hardware control function */
cfa460ad	632	nand->cmd_ctrl = nand_davinci_hwcontrol;
c74b2108	633
20da6f4d NT	634	nand->read_buf = nand_davinci_read_buf;
	635	nand->write_buf = nand_davinci_write_buf;
	636
c74b2108	637	nand->dev_ready = nand_davinci_dev_ready;
c74b2108 SK	638
c74b2108 SK	639	nand_flash_init();
154b5484	640	}
c74b2108	641
154b5484 DB	642	int board_nand_init(struct nand_chip *chip) __attribute__((weak));
	643
	644	int board_nand_init(struct nand_chip *chip)
	645	{
	646	davinci_nand_init(chip);
	647	return 0;
c74b2108	648	}