[people/ms/u-boot.git] / drivers / net / fec_mxc.c

/*
 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
 * (C) Copyright 2008 Armadeus Systems nc
 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include "fec_mxc.h"

#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <asm/errno.h>

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_MII
#error "CONFIG_MII has to be defined!"
#endif

#undef DEBUG

struct nbuf {
	uint8_t data[1500];	/**< actual data */
	int length;		/**< actual length */
	int used;		/**< buffer in use or not */
	uint8_t head[16];	/**< MAC header(6 + 6 + 2) + 2(aligned) */
};

struct fec_priv gfec = {
	.eth       = (struct ethernet_regs *)IMX_FEC_BASE,
	.xcv_type  = MII100,
	.rbd_base  = NULL,
	.rbd_index = 0,
	.tbd_base  = NULL,
	.tbd_index = 0,
	.bd        = NULL,
	.rdb_ptr   = NULL,
	.base_ptr  = NULL,
};

/*
 * MII-interface related functions
 */
static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
		uint16_t *retVal)
{
	struct eth_device *edev = eth_get_dev_by_name(dev);
	struct fec_priv *fec = (struct fec_priv *)edev->priv;

	uint32_t reg;		/* convenient holder for the PHY register */
	uint32_t phy;		/* convenient holder for the PHY */
	uint32_t start;

	/*
	 * reading from any PHY's register is done by properly
	 * programming the FEC's MII data register.
	 */
	writel(FEC_IEVENT_MII, &fec->eth->ievent);
	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;

	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
			phy | reg, &fec->eth->mii_data);

	/*
	 * wait for the related interrupt
	 */
	start = get_timer_masked();
	while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
			printf("Read MDIO failed...\n");
			return -1;
		}
	}

	/*
	 * clear mii interrupt bit
	 */
	writel(FEC_IEVENT_MII, &fec->eth->ievent);

	/*
	 * it's now safe to read the PHY's register
	 */
	*retVal = readl(&fec->eth->mii_data);
	debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
			regAddr, *retVal);
	return 0;
}

static void fec_mii_setspeed(struct fec_priv *fec)
{
	/*
	 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
	 * and do not drop the Preamble.
	 */
	writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
			&fec->eth->mii_speed);
	debug("fec_init: mii_speed %#lx\n",
			fec->eth->mii_speed);
}
static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
		uint16_t data)
{
	struct eth_device *edev = eth_get_dev_by_name(dev);
	struct fec_priv *fec = (struct fec_priv *)edev->priv;

	uint32_t reg;		/* convenient holder for the PHY register */
	uint32_t phy;		/* convenient holder for the PHY */
	uint32_t start;

	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;

	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
		FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);

	/*
	 * wait for the MII interrupt
	 */
	start = get_timer_masked();
	while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
			printf("Write MDIO failed...\n");
			return -1;
		}
	}

	/*
	 * clear MII interrupt bit
	 */
	writel(FEC_IEVENT_MII, &fec->eth->ievent);
	debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
			regAddr, data);

	return 0;
}

static int miiphy_restart_aneg(struct eth_device *dev)
{
	/*
	 * Wake up from sleep if necessary
	 * Reset PHY, then delay 300ns
	 */
	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
			PHY_BMCR_RESET);
	udelay(1000);

	/*
	 * Set the auto-negotiation advertisement register bits
	 */
	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR,
			PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
			PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3);
	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);

	return 0;
}

static int miiphy_wait_aneg(struct eth_device *dev)
{
	uint32_t start;
	uint16_t status;

	/*
	 * Wait for AN completion
	 */
	start = get_timer_masked();
	do {
		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
			printf("%s: Autonegotiation timeout\n", dev->name);
			return -1;
		}

		if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
					PHY_BMSR, &status)) {
			printf("%s: Autonegotiation failed. status: 0x%04x\n",
					dev->name, status);
			return -1;
		}
	} while (!(status & PHY_BMSR_LS));

	return 0;
}
static int fec_rx_task_enable(struct fec_priv *fec)
{
	writel(1 << 24, &fec->eth->r_des_active);
	return 0;
}

static int fec_rx_task_disable(struct fec_priv *fec)
{
	return 0;
}

static int fec_tx_task_enable(struct fec_priv *fec)
{
	writel(1 << 24, &fec->eth->x_des_active);
	return 0;
}

static int fec_tx_task_disable(struct fec_priv *fec)
{
	return 0;
}

/**
 * Initialize receive task's buffer descriptors
 * @param[in] fec all we know about the device yet
 * @param[in] count receive buffer count to be allocated
 * @param[in] size size of each receive buffer
 * @return 0 on success
 *
 * For this task we need additional memory for the data buffers. And each
 * data buffer requires some alignment. Thy must be aligned to a specific
 * boundary each (DB_DATA_ALIGNMENT).
 */
static int fec_rbd_init(struct fec_priv *fec, int count, int size)
{
	int ix;
	uint32_t p = 0;

	/* reserve data memory and consider alignment */
	if (fec->rdb_ptr == NULL)
		fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
	p = (uint32_t)fec->rdb_ptr;
	if (!p) {
		puts("fec_mxc: not enough malloc memory\n");
		return -ENOMEM;
	}
	memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
	p += DB_DATA_ALIGNMENT-1;
	p &= ~(DB_DATA_ALIGNMENT-1);

	for (ix = 0; ix < count; ix++) {
		writel(p, &fec->rbd_base[ix].data_pointer);
		p += size;
		writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
		writew(0, &fec->rbd_base[ix].data_length);
	}
	/*
	 * mark the last RBD to close the ring
	 */
	writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
	fec->rbd_index = 0;

	return 0;
}

/**
 * Initialize transmit task's buffer descriptors
 * @param[in] fec all we know about the device yet
 *
 * Transmit buffers are created externally. We only have to init the BDs here.\n
 * Note: There is a race condition in the hardware. When only one BD is in
 * use it must be marked with the WRAP bit to use it for every transmitt.
 * This bit in combination with the READY bit results into double transmit
 * of each data buffer. It seems the state machine checks READY earlier then
 * resetting it after the first transfer.
 * Using two BDs solves this issue.
 */
static void fec_tbd_init(struct fec_priv *fec)
{
	writew(0x0000, &fec->tbd_base[0].status);
	writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
	fec->tbd_index = 0;
}

/**
 * Mark the given read buffer descriptor as free
 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
 * @param[in] pRbd buffer descriptor to mark free again
 */
static void fec_rbd_clean(int last, struct fec_bd *pRbd)
{
	/*
	 * Reset buffer descriptor as empty
	 */
	if (last)
		writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
	else
		writew(FEC_RBD_EMPTY, &pRbd->status);
	/*
	 * no data in it
	 */
	writew(0, &pRbd->data_length);
}

static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
{
/*
 * The MX27 can store the mac address in internal eeprom
 * This mechanism is not supported now by MX51
 */
#ifdef CONFIG_MX51
	return -1;
#else
	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
	int i;

	for (i = 0; i < 6; i++)
		mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);

	return is_valid_ether_addr(mac);
#endif
}

static int fec_set_hwaddr(struct eth_device *dev)
{
	uchar *mac = dev->enetaddr;
	struct fec_priv *fec = (struct fec_priv *)dev->priv;

	writel(0, &fec->eth->iaddr1);
	writel(0, &fec->eth->iaddr2);
	writel(0, &fec->eth->gaddr1);
	writel(0, &fec->eth->gaddr2);

	/*
	 * Set physical address
	 */
	writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
			&fec->eth->paddr1);
	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);

	return 0;
}

/**
 * Start the FEC engine
 * @param[in] dev Our device to handle
 */
static int fec_open(struct eth_device *edev)
{
	struct fec_priv *fec = (struct fec_priv *)edev->priv;

	debug("fec_open: fec_open(dev)\n");
	/* full-duplex, heartbeat disabled */
	writel(1 << 2, &fec->eth->x_cntrl);
	fec->rbd_index = 0;

	/*
	 * Enable FEC-Lite controller
	 */
	writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);

	miiphy_wait_aneg(edev);
	miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
	miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR);

	/*
	 * Enable SmartDMA receive task
	 */
	fec_rx_task_enable(fec);

	udelay(100000);
	return 0;
}

static int fec_init(struct eth_device *dev, bd_t* bd)
{
	uint32_t base;
	struct fec_priv *fec = (struct fec_priv *)dev->priv;

	/*
	 * reserve memory for both buffer descriptor chains at once
	 * Datasheet forces the startaddress of each chain is 16 byte
	 * aligned
	 */
	if (fec->base_ptr == NULL)
		fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
				sizeof(struct fec_bd) + DB_ALIGNMENT);
	base = (uint32_t)fec->base_ptr;
	if (!base) {
		puts("fec_mxc: not enough malloc memory\n");
		return -ENOMEM;
	}
	memset((void *)base, 0, (2 + FEC_RBD_NUM) *
			sizeof(struct fec_bd) + DB_ALIGNMENT);
	base += (DB_ALIGNMENT-1);
	base &= ~(DB_ALIGNMENT-1);

	fec->rbd_base = (struct fec_bd *)base;

	base += FEC_RBD_NUM * sizeof(struct fec_bd);

	fec->tbd_base = (struct fec_bd *)base;

	/*
	 * Set interrupt mask register
	 */
	writel(0x00000000, &fec->eth->imask);

	/*
	 * Clear FEC-Lite interrupt event register(IEVENT)
	 */
	writel(0xffffffff, &fec->eth->ievent);


	/*
	 * Set FEC-Lite receive control register(R_CNTRL):
	 */
	if (fec->xcv_type == SEVENWIRE) {
		/*
		 * Frame length=1518; 7-wire mode
		 */
		writel(0x05ee0020, &fec->eth->r_cntrl);	/* FIXME 0x05ee0000 */
	} else {
		/*
		 * Frame length=1518; MII mode;
		 */
		writel(0x05ee0024, &fec->eth->r_cntrl);	/* FIXME 0x05ee0004 */

		fec_mii_setspeed(fec);
	}
	/*
	 * Set Opcode/Pause Duration Register
	 */
	writel(0x00010020, &fec->eth->op_pause);	/* FIXME 0xffff0020; */
	writel(0x2, &fec->eth->x_wmrk);
	/*
	 * Set multicast address filter
	 */
	writel(0x00000000, &fec->eth->gaddr1);
	writel(0x00000000, &fec->eth->gaddr2);


	/* clear MIB RAM */
	long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
	while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
		*mib_ptr++ = 0;

	/* FIFO receive start register */
	writel(0x520, &fec->eth->r_fstart);

	/* size and address of each buffer */
	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
	writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
	writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);

	/*
	 * Initialize RxBD/TxBD rings
	 */
	if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
		free(fec->base_ptr);
		fec->base_ptr = NULL;
		return -ENOMEM;
	}
	fec_tbd_init(fec);


	if (fec->xcv_type != SEVENWIRE)
		miiphy_restart_aneg(dev);

	fec_open(dev);
	fec_set_hwaddr(dev);
	return 0;
}

/**
 * Halt the FEC engine
 * @param[in] dev Our device to handle
 */
static void fec_halt(struct eth_device *dev)
{
	struct fec_priv *fec = &gfec;
	int counter = 0xffff;

	/*
	 * issue graceful stop command to the FEC transmitter if necessary
	 */
	writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
			&fec->eth->x_cntrl);

	debug("eth_halt: wait for stop regs\n");
	/*
	 * wait for graceful stop to register
	 */
	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
		;	/* FIXME ensure time */

	/*
	 * Disable SmartDMA tasks
	 */
	fec_tx_task_disable(fec);
	fec_rx_task_disable(fec);

	/*
	 * Disable the Ethernet Controller
	 * Note: this will also reset the BD index counter!
	 */
	writel(0, &fec->eth->ecntrl);
	fec->rbd_index = 0;
	fec->tbd_index = 0;
	debug("eth_halt: done\n");
}

/**
 * Transmit one frame
 * @param[in] dev Our ethernet device to handle
 * @param[in] packet Pointer to the data to be transmitted
 * @param[in] length Data count in bytes
 * @return 0 on success
 */
static int fec_send(struct eth_device *dev, volatile void* packet, int length)
{
	unsigned int status;

	/*
	 * This routine transmits one frame.  This routine only accepts
	 * 6-byte Ethernet addresses.
	 */
	struct fec_priv *fec = (struct fec_priv *)dev->priv;

	/*
	 * Check for valid length of data.
	 */
	if ((length > 1500) || (length <= 0)) {
		printf("Payload (%d) too large\n", length);
		return -1;
	}

	/*
	 * Setup the transmit buffer
	 * Note: We are always using the first buffer for transmission,
	 * the second will be empty and only used to stop the DMA engine
	 */
	writew(length, &fec->tbd_base[fec->tbd_index].data_length);
	writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
	/*
	 * update BD's status now
	 * This block:
	 * - is always the last in a chain (means no chain)
	 * - should transmitt the CRC
	 * - might be the last BD in the list, so the address counter should
	 *   wrap (-> keep the WRAP flag)
	 */
	status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
	status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
	writew(status, &fec->tbd_base[fec->tbd_index].status);

	/*
	 * Enable SmartDMA transmit task
	 */
	fec_tx_task_enable(fec);

	/*
	 * wait until frame is sent .
	 */
	while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
		/* FIXME: Timeout */
	}
	debug("fec_send: status 0x%x index %d\n",
			readw(&fec->tbd_base[fec->tbd_index].status),
			fec->tbd_index);
	/* for next transmission use the other buffer */
	if (fec->tbd_index)
		fec->tbd_index = 0;
	else
		fec->tbd_index = 1;

	return 0;
}

/**
 * Pull one frame from the card
 * @param[in] dev Our ethernet device to handle
 * @return Length of packet read
 */
static int fec_recv(struct eth_device *dev)
{
	struct fec_priv *fec = (struct fec_priv *)dev->priv;
	struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
	unsigned long ievent;
	int frame_length, len = 0;
	struct nbuf *frame;
	uint16_t bd_status;
	uchar buff[FEC_MAX_PKT_SIZE];

	/*
	 * Check if any critical events have happened
	 */
	ievent = readl(&fec->eth->ievent);
	writel(ievent, &fec->eth->ievent);
	debug("fec_recv: ievent 0x%x\n", ievent);
	if (ievent & FEC_IEVENT_BABR) {
		fec_halt(dev);
		fec_init(dev, fec->bd);
		printf("some error: 0x%08lx\n", ievent);
		return 0;
	}
	if (ievent & FEC_IEVENT_HBERR) {
		/* Heartbeat error */
		writel(0x00000001 | readl(&fec->eth->x_cntrl),
				&fec->eth->x_cntrl);
	}
	if (ievent & FEC_IEVENT_GRA) {
		/* Graceful stop complete */
		if (readl(&fec->eth->x_cntrl) & 0x00000001) {
			fec_halt(dev);
			writel(~0x00000001 & readl(&fec->eth->x_cntrl),
					&fec->eth->x_cntrl);
			fec_init(dev, fec->bd);
		}
	}

	/*
	 * ensure reading the right buffer status
	 */
	bd_status = readw(&rbd->status);
	debug("fec_recv: status 0x%x\n", bd_status);

	if (!(bd_status & FEC_RBD_EMPTY)) {
		if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
			((readw(&rbd->data_length) - 4) > 14)) {
			/*
			 * Get buffer address and size
			 */
			frame = (struct nbuf *)readl(&rbd->data_pointer);
			frame_length = readw(&rbd->data_length) - 4;
			/*
			 *  Fill the buffer and pass it to upper layers
			 */
			memcpy(buff, frame->data, frame_length);
			NetReceive(buff, frame_length);
			len = frame_length;
		} else {
			if (bd_status & FEC_RBD_ERR)
				printf("error frame: 0x%08lx 0x%08x\n",
						(ulong)rbd->data_pointer,
						bd_status);
		}
		/*
		 * free the current buffer, restart the engine
		 * and move forward to the next buffer
		 */
		fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
		fec_rx_task_enable(fec);
		fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
	}
	debug("fec_recv: stop\n");

	return len;
}

static int fec_probe(bd_t *bd)
{
	struct eth_device *edev;
	struct fec_priv *fec = &gfec;
	unsigned char ethaddr[6];

	/* create and fill edev struct */
	edev = (struct eth_device *)malloc(sizeof(struct eth_device));
	if (!edev) {
		puts("fec_mxc: not enough malloc memory\n");
		return -ENOMEM;
	}
	edev->priv = fec;
	edev->init = fec_init;
	edev->send = fec_send;
	edev->recv = fec_recv;
	edev->halt = fec_halt;

	fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
	fec->bd = bd;

	fec->xcv_type = MII100;

	/* Reset chip. */
	writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
	while (readl(&fec->eth->ecntrl) & 1)
		udelay(10);

	/*
	 * Set interrupt mask register
	 */
	writel(0x00000000, &fec->eth->imask);

	/*
	 * Clear FEC-Lite interrupt event register(IEVENT)
	 */
	writel(0xffffffff, &fec->eth->ievent);

	/*
	 * Set FEC-Lite receive control register(R_CNTRL):
	 */
	/*
	 * Frame length=1518; MII mode;
	 */
	writel(0x05ee0024, &fec->eth->r_cntrl);	/* FIXME 0x05ee0004 */
	fec_mii_setspeed(fec);

	sprintf(edev->name, "FEC_MXC");

	miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);

	eth_register(edev);

	if (fec_get_hwaddr(edev, ethaddr) == 0) {
		printf("got MAC address from EEPROM: %pM\n", ethaddr);
		memcpy(edev->enetaddr, ethaddr, 6);
		fec_set_hwaddr(edev);
	}

	return 0;
}

int fecmxc_initialize(bd_t *bd)
{
	int lout = 1;

	debug("eth_init: fec_probe(bd)\n");
	lout = fec_probe(bd);

	return lout;
}
Commit	Line	Data
0b23fb36 IY	1	/*
	2	* (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
	3	* (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
	4	* (C) Copyright 2008 Armadeus Systems nc
	5	* (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
	6	* (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <malloc.h>
	26	#include <net.h>
	27	#include <miiphy.h>
	28	#include "fec_mxc.h"
	29
	30	#include <asm/arch/clock.h>
	31	#include <asm/arch/imx-regs.h>
	32	#include <asm/io.h>
	33	#include <asm/errno.h>
	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
	37	#ifndef CONFIG_MII
	38	#error "CONFIG_MII has to be defined!"
	39	#endif
	40
	41	#undef DEBUG
	42
	43	struct nbuf {
	44	uint8_t data[1500]; /*< actual data /
	45	int length; /*< actual length /
	46	int used; /*< buffer in use or not /
	47	uint8_t head[16]; /*< MAC header(6 + 6 + 2) + 2(aligned) /
	48	};
	49
	50	struct fec_priv gfec = {
	51	.eth = (struct ethernet_regs *)IMX_FEC_BASE,
	52	.xcv_type = MII100,
	53	.rbd_base = NULL,
	54	.rbd_index = 0,
	55	.tbd_base = NULL,
	56	.tbd_index = 0,
	57	.bd = NULL,
651ef90f M	58	.rdb_ptr = NULL,
651ef90f M	59	.base_ptr = NULL,
0b23fb36 IY	60	};
	61
	62	/*
	63	* MII-interface related functions
	64	*/
	65	static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
	66	uint16_t *retVal)
	67	{
	68	struct eth_device *edev = eth_get_dev_by_name(dev);
	69	struct fec_priv fec = (struct fec_priv )edev->priv;
	70
	71	uint32_t reg; /* convenient holder for the PHY register */
	72	uint32_t phy; /* convenient holder for the PHY */
	73	uint32_t start;
	74
	75	/*
	76	* reading from any PHY's register is done by properly
	77	* programming the FEC's MII data register.
	78	*/
	79	writel(FEC_IEVENT_MII, &fec->eth->ievent);
	80	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
	81	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
	82
	83	writel(FEC_MII_DATA_ST \| FEC_MII_DATA_OP_RD \| FEC_MII_DATA_TA \|
	84	phy \| reg, &fec->eth->mii_data);
	85
	86	/*
	87	* wait for the related interrupt
	88	*/
	89	start = get_timer_masked();
	90	while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
	91	if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
	92	printf("Read MDIO failed...\n");
	93	return -1;
	94	}
	95	}
	96
	97	/*
	98	* clear mii interrupt bit
	99	*/
	100	writel(FEC_IEVENT_MII, &fec->eth->ievent);
	101
	102	/*
	103	* it's now safe to read the PHY's register
	104	*/
	105	*retVal = readl(&fec->eth->mii_data);
	106	debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
	107	regAddr, *retVal);
	108	return 0;
	109	}
	110
4294b248 SB	111	static void fec_mii_setspeed(struct fec_priv *fec)
	112	{
	113	/*
	114	* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
	115	* and do not drop the Preamble.
	116	*/
	117	writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
	118	&fec->eth->mii_speed);
	119	debug("fec_init: mii_speed %#lx\n",
	120	fec->eth->mii_speed);
	121	}
0b23fb36 IY	122	static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
	123	uint16_t data)
	124	{
	125	struct eth_device *edev = eth_get_dev_by_name(dev);
	126	struct fec_priv fec = (struct fec_priv )edev->priv;
	127
	128	uint32_t reg; /* convenient holder for the PHY register */
	129	uint32_t phy; /* convenient holder for the PHY */
	130	uint32_t start;
	131
	132	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
	133	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
	134
	135	writel(FEC_MII_DATA_ST \| FEC_MII_DATA_OP_WR \|
	136	FEC_MII_DATA_TA \| phy \| reg \| data, &fec->eth->mii_data);
	137
	138	/*
	139	* wait for the MII interrupt
	140	*/
	141	start = get_timer_masked();
	142	while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
	143	if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
	144	printf("Write MDIO failed...\n");
	145	return -1;
	146	}
	147	}
	148
	149	/*
	150	* clear MII interrupt bit
	151	*/
	152	writel(FEC_IEVENT_MII, &fec->eth->ievent);
	153	debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
	154	regAddr, data);
	155
	156	return 0;
	157	}
	158
	159	static int miiphy_restart_aneg(struct eth_device *dev)
	160	{
	161	/*
	162	* Wake up from sleep if necessary
	163	* Reset PHY, then delay 300ns
	164	*/
	165	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
	166	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
	167	PHY_BMCR_RESET);
	168	udelay(1000);
	169
	170	/*
	171	* Set the auto-negotiation advertisement register bits
	172	*/
e8f1546a M	173	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR,
	174	PHY_ANLPAR_TXFD \| PHY_ANLPAR_TX \| PHY_ANLPAR_10FD \|
	175	PHY_ANLPAR_10 \| PHY_ANLPAR_PSB_802_3);
0b23fb36 IY	176	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
	177	PHY_BMCR_AUTON \| PHY_BMCR_RST_NEG);
	178
	179	return 0;
	180	}
	181
	182	static int miiphy_wait_aneg(struct eth_device *dev)
	183	{
	184	uint32_t start;
	185	uint16_t status;
	186
	187	/*
	188	* Wait for AN completion
	189	*/
	190	start = get_timer_masked();
	191	do {
	192	if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
	193	printf("%s: Autonegotiation timeout\n", dev->name);
	194	return -1;
	195	}
	196
	197	if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
	198	PHY_BMSR, &status)) {
	199	printf("%s: Autonegotiation failed. status: 0x%04x\n",
	200	dev->name, status);
	201	return -1;
	202	}
	203	} while (!(status & PHY_BMSR_LS));
	204
	205	return 0;
	206	}
	207	static int fec_rx_task_enable(struct fec_priv *fec)
	208	{
	209	writel(1 << 24, &fec->eth->r_des_active);
	210	return 0;
	211	}
	212
	213	static int fec_rx_task_disable(struct fec_priv *fec)
	214	{
	215	return 0;
	216	}
	217
	218	static int fec_tx_task_enable(struct fec_priv *fec)
	219	{
	220	writel(1 << 24, &fec->eth->x_des_active);
	221	return 0;
	222	}
	223
	224	static int fec_tx_task_disable(struct fec_priv *fec)
	225	{
	226	return 0;
	227	}
	228
	229	/**
	230	* Initialize receive task's buffer descriptors
	231	* @param[in] fec all we know about the device yet
	232	* @param[in] count receive buffer count to be allocated
	233	* @param[in] size size of each receive buffer
	234	* @return 0 on success
	235	*
	236	* For this task we need additional memory for the data buffers. And each
	237	* data buffer requires some alignment. Thy must be aligned to a specific
	238	* boundary each (DB_DATA_ALIGNMENT).
	239	*/
240	static int fec_rbd_init(struct fec_priv *fec, int count, int size)
241	{
242	int ix;
243	uint32_t p = 0;
244
245	/* reserve data memory and consider alignment */
651ef90f M	246	if (fec->rdb_ptr == NULL)
651ef90f M	247	fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
0b23fb36 IY	248	p = (uint32_t)fec->rdb_ptr;
0b23fb36 IY	249	if (!p) {
4294b248	250	puts("fec_mxc: not enough malloc memory\n");
0b23fb36 IY	251	return -ENOMEM;
	252	}
	253	memset((void )p, 0, size count + DB_DATA_ALIGNMENT);
	254	p += DB_DATA_ALIGNMENT-1;
	255	p &= ~(DB_DATA_ALIGNMENT-1);
	256
	257	for (ix = 0; ix < count; ix++) {
	258	writel(p, &fec->rbd_base[ix].data_pointer);
	259	p += size;
	260	writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
	261	writew(0, &fec->rbd_base[ix].data_length);
	262	}
	263	/*
	264	* mark the last RBD to close the ring
	265	*/
	266	writew(FEC_RBD_WRAP \| FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
	267	fec->rbd_index = 0;
	268
	269	return 0;
	270	}
	271
	272	/**
	273	* Initialize transmit task's buffer descriptors
	274	* @param[in] fec all we know about the device yet
	275	*
	276	* Transmit buffers are created externally. We only have to init the BDs here.\n
	277	* Note: There is a race condition in the hardware. When only one BD is in
	278	* use it must be marked with the WRAP bit to use it for every transmitt.
	279	* This bit in combination with the READY bit results into double transmit
	280	* of each data buffer. It seems the state machine checks READY earlier then
	281	* resetting it after the first transfer.
	282	* Using two BDs solves this issue.
	283	*/
	284	static void fec_tbd_init(struct fec_priv *fec)
	285	{
	286	writew(0x0000, &fec->tbd_base[0].status);
	287	writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
	288	fec->tbd_index = 0;
	289	}
	290
	291	/**
	292	* Mark the given read buffer descriptor as free
	293	* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
	294	* @param[in] pRbd buffer descriptor to mark free again
	295	*/
	296	static void fec_rbd_clean(int last, struct fec_bd *pRbd)
	297	{
	298	/*
	299	* Reset buffer descriptor as empty
	300	*/
	301	if (last)
	302	writew(FEC_RBD_WRAP \| FEC_RBD_EMPTY, &pRbd->status);
	303	else
	304	writew(FEC_RBD_EMPTY, &pRbd->status);
	305	/*
	306	* no data in it
	307	*/
	308	writew(0, &pRbd->data_length);
	309	}
	310
	311	static int fec_get_hwaddr(struct eth_device dev, unsigned char mac)
	312	{
4294b248 SB	313	/*
	314	* The MX27 can store the mac address in internal eeprom
	315	* This mechanism is not supported now by MX51
	316	*/
	317	#ifdef CONFIG_MX51
	318	return -1;
	319	#else
0b23fb36 IY	320	struct iim_regs iim = (struct iim_regs )IMX_IIM_BASE;
	321	int i;
	322
	323	for (i = 0; i < 6; i++)
	324	mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);
	325
	326	return is_valid_ether_addr(mac);
4294b248	327	#endif
0b23fb36 IY	328	}
0b23fb36 IY	329
4294b248	330	static int fec_set_hwaddr(struct eth_device *dev)
0b23fb36	331	{
4294b248	332	uchar *mac = dev->enetaddr;
0b23fb36 IY	333	struct fec_priv fec = (struct fec_priv )dev->priv;
	334
	335	writel(0, &fec->eth->iaddr1);
	336	writel(0, &fec->eth->iaddr2);
	337	writel(0, &fec->eth->gaddr1);
	338	writel(0, &fec->eth->gaddr2);
	339
	340	/*
	341	* Set physical address
	342	*/
	343	writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
	344	&fec->eth->paddr1);
	345	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
	346
	347	return 0;
	348	}
	349
	350	/**
	351	* Start the FEC engine
	352	* @param[in] dev Our device to handle
	353	*/
	354	static int fec_open(struct eth_device *edev)
	355	{
	356	struct fec_priv fec = (struct fec_priv )edev->priv;
	357
	358	debug("fec_open: fec_open(dev)\n");
	359	/* full-duplex, heartbeat disabled */
	360	writel(1 << 2, &fec->eth->x_cntrl);
	361	fec->rbd_index = 0;
	362
	363	/*
	364	* Enable FEC-Lite controller
	365	*/
	366	writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
	367
	368	miiphy_wait_aneg(edev);
e8f1546a M	369	miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
e8f1546a M	370	miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR);
0b23fb36 IY	371
	372	/*
	373	* Enable SmartDMA receive task
	374	*/
	375	fec_rx_task_enable(fec);
	376
	377	udelay(100000);
	378	return 0;
	379	}
	380
	381	static int fec_init(struct eth_device dev, bd_t bd)
	382	{
	383	uint32_t base;
	384	struct fec_priv fec = (struct fec_priv )dev->priv;
	385
	386	/*
	387	* reserve memory for both buffer descriptor chains at once
	388	* Datasheet forces the startaddress of each chain is 16 byte
	389	* aligned
	390	*/
651ef90f M	391	if (fec->base_ptr == NULL)
	392	fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
	393	sizeof(struct fec_bd) + DB_ALIGNMENT);
0b23fb36 IY	394	base = (uint32_t)fec->base_ptr;
0b23fb36 IY	395	if (!base) {
4294b248	396	puts("fec_mxc: not enough malloc memory\n");
0b23fb36 IY	397	return -ENOMEM;
	398	}
	399	memset((void )base, 0, (2 + FEC_RBD_NUM)
	400	sizeof(struct fec_bd) + DB_ALIGNMENT);
	401	base += (DB_ALIGNMENT-1);
	402	base &= ~(DB_ALIGNMENT-1);
	403
	404	fec->rbd_base = (struct fec_bd *)base;
	405
	406	base += FEC_RBD_NUM * sizeof(struct fec_bd);
	407
	408	fec->tbd_base = (struct fec_bd *)base;
	409
	410	/*
	411	* Set interrupt mask register
	412	*/
	413	writel(0x00000000, &fec->eth->imask);
	414
	415	/*
	416	* Clear FEC-Lite interrupt event register(IEVENT)
	417	*/
	418	writel(0xffffffff, &fec->eth->ievent);
	419
	420
	421	/*
	422	* Set FEC-Lite receive control register(R_CNTRL):
	423	*/
	424	if (fec->xcv_type == SEVENWIRE) {
	425	/*
	426	* Frame length=1518; 7-wire mode
	427	*/
	428	writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */
	429	} else {
	430	/*
	431	* Frame length=1518; MII mode;
	432	*/
	433	writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
4294b248 SB	434
4294b248 SB	435	fec_mii_setspeed(fec);
0b23fb36 IY	436	}
	437	/*
	438	* Set Opcode/Pause Duration Register
	439	*/
	440	writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
	441	writel(0x2, &fec->eth->x_wmrk);
	442	/*
	443	* Set multicast address filter
	444	*/
	445	writel(0x00000000, &fec->eth->gaddr1);
	446	writel(0x00000000, &fec->eth->gaddr2);
	447
	448
	449	/* clear MIB RAM */
	450	long mib_ptr = (long )(IMX_FEC_BASE + 0x200);
	451	while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
	452	*mib_ptr++ = 0;
	453
	454	/* FIFO receive start register */
	455	writel(0x520, &fec->eth->r_fstart);
	456
	457	/* size and address of each buffer */
	458	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
	459	writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
	460	writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
	461
	462	/*
	463	* Initialize RxBD/TxBD rings
	464	*/
	465	if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
	466	free(fec->base_ptr);
c179a289	467	fec->base_ptr = NULL;
0b23fb36 IY	468	return -ENOMEM;
	469	}
	470	fec_tbd_init(fec);
	471
	472
	473	if (fec->xcv_type != SEVENWIRE)
	474	miiphy_restart_aneg(dev);
	475
	476	fec_open(dev);
4294b248	477	fec_set_hwaddr(dev);
0b23fb36 IY	478	return 0;
	479	}
	480
	481	/**
	482	* Halt the FEC engine
	483	* @param[in] dev Our device to handle
	484	*/
	485	static void fec_halt(struct eth_device *dev)
	486	{
	487	struct fec_priv *fec = &gfec;
	488	int counter = 0xffff;
	489
	490	/*
	491	* issue graceful stop command to the FEC transmitter if necessary
	492	*/
	493	writel(FEC_ECNTRL_RESET \| readl(&fec->eth->x_cntrl),
	494	&fec->eth->x_cntrl);
	495
	496	debug("eth_halt: wait for stop regs\n");
	497	/*
	498	* wait for graceful stop to register
	499	*/
	500	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
	501	; /* FIXME ensure time */
	502
	503	/*
	504	* Disable SmartDMA tasks
	505	*/
	506	fec_tx_task_disable(fec);
	507	fec_rx_task_disable(fec);
	508
	509	/*
	510	* Disable the Ethernet Controller
	511	* Note: this will also reset the BD index counter!
	512	*/
	513	writel(0, &fec->eth->ecntrl);
	514	fec->rbd_index = 0;
	515	fec->tbd_index = 0;
0b23fb36 IY	516	debug("eth_halt: done\n");
	517	}
	518
	519	/**
	520	* Transmit one frame
	521	* @param[in] dev Our ethernet device to handle
	522	* @param[in] packet Pointer to the data to be transmitted
	523	* @param[in] length Data count in bytes
	524	* @return 0 on success
	525	*/
	526	static int fec_send(struct eth_device dev, volatile void packet, int length)
	527	{
	528	unsigned int status;
	529
	530	/*
	531	* This routine transmits one frame. This routine only accepts
	532	* 6-byte Ethernet addresses.
	533	*/
	534	struct fec_priv fec = (struct fec_priv )dev->priv;
	535
	536	/*
	537	* Check for valid length of data.
	538	*/
	539	if ((length > 1500) \|\| (length <= 0)) {
4294b248	540	printf("Payload (%d) too large\n", length);
0b23fb36 IY	541	return -1;
	542	}
	543
	544	/*
	545	* Setup the transmit buffer
	546	* Note: We are always using the first buffer for transmission,
	547	* the second will be empty and only used to stop the DMA engine
	548	*/
	549	writew(length, &fec->tbd_base[fec->tbd_index].data_length);
	550	writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
	551	/*
	552	* update BD's status now
	553	* This block:
	554	* - is always the last in a chain (means no chain)
	555	* - should transmitt the CRC
	556	* - might be the last BD in the list, so the address counter should
	557	* wrap (-> keep the WRAP flag)
	558	*/
	559	status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
	560	status \|= FEC_TBD_LAST \| FEC_TBD_TC \| FEC_TBD_READY;
	561	writew(status, &fec->tbd_base[fec->tbd_index].status);
	562
	563	/*
	564	* Enable SmartDMA transmit task
	565	*/
	566	fec_tx_task_enable(fec);
	567
	568	/*
	569	* wait until frame is sent .
	570	*/
	571	while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
	572	/* FIXME: Timeout */
	573	}
	574	debug("fec_send: status 0x%x index %d\n",
	575	readw(&fec->tbd_base[fec->tbd_index].status),
	576	fec->tbd_index);
	577	/* for next transmission use the other buffer */
	578	if (fec->tbd_index)
	579	fec->tbd_index = 0;
	580	else
	581	fec->tbd_index = 1;
	582
	583	return 0;
	584	}
	585
	586	/**
	587	* Pull one frame from the card
	588	* @param[in] dev Our ethernet device to handle
	589	* @return Length of packet read
	590	*/
	591	static int fec_recv(struct eth_device *dev)
	592	{
	593	struct fec_priv fec = (struct fec_priv )dev->priv;
	594	struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
	595	unsigned long ievent;
	596	int frame_length, len = 0;
	597	struct nbuf *frame;
	598	uint16_t bd_status;
	599	uchar buff[FEC_MAX_PKT_SIZE];
	600
	601	/*
	602	* Check if any critical events have happened
	603	*/
	604	ievent = readl(&fec->eth->ievent);
605	writel(ievent, &fec->eth->ievent);
606	debug("fec_recv: ievent 0x%x\n", ievent);
607	if (ievent & FEC_IEVENT_BABR) {
608	fec_halt(dev);
609	fec_init(dev, fec->bd);
610	printf("some error: 0x%08lx\n", ievent);
611	return 0;
612	}
613	if (ievent & FEC_IEVENT_HBERR) {
614	/* Heartbeat error */
615	writel(0x00000001 \| readl(&fec->eth->x_cntrl),
616	&fec->eth->x_cntrl);
617	}
618	if (ievent & FEC_IEVENT_GRA) {
619	/* Graceful stop complete */
620	if (readl(&fec->eth->x_cntrl) & 0x00000001) {
621	fec_halt(dev);
622	writel(~0x00000001 & readl(&fec->eth->x_cntrl),
623	&fec->eth->x_cntrl);
624	fec_init(dev, fec->bd);
625	}
626	}
627
628	/*
629	* ensure reading the right buffer status
630	*/
631	bd_status = readw(&rbd->status);
632	debug("fec_recv: status 0x%x\n", bd_status);
633
634	if (!(bd_status & FEC_RBD_EMPTY)) {
635	if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
636	((readw(&rbd->data_length) - 4) > 14)) {
637	/*
638	* Get buffer address and size
639	*/
640	frame = (struct nbuf *)readl(&rbd->data_pointer);
641	frame_length = readw(&rbd->data_length) - 4;
642	/*
643	* Fill the buffer and pass it to upper layers
644	*/
645	memcpy(buff, frame->data, frame_length);
646	NetReceive(buff, frame_length);
647	len = frame_length;
648	} else {
649	if (bd_status & FEC_RBD_ERR)
650	printf("error frame: 0x%08lx 0x%08x\n",
651	(ulong)rbd->data_pointer,
652	bd_status);
653	}
654	/*
655	* free the current buffer, restart the engine
656	* and move forward to the next buffer
657	*/
658	fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
659	fec_rx_task_enable(fec);
660	fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
661	}
662	debug("fec_recv: stop\n");
663
664	return len;
665	}
666
667	static int fec_probe(bd_t *bd)
668	{
0b23fb36 IY	669	struct eth_device *edev;
0b23fb36 IY	670	struct fec_priv *fec = &gfec;
0b23fb36	671	unsigned char ethaddr[6];
0b23fb36 IY	672
	673	/* create and fill edev struct */
	674	edev = (struct eth_device *)malloc(sizeof(struct eth_device));
	675	if (!edev) {
4294b248	676	puts("fec_mxc: not enough malloc memory\n");
0b23fb36 IY	677	return -ENOMEM;
	678	}
	679	edev->priv = fec;
	680	edev->init = fec_init;
	681	edev->send = fec_send;
	682	edev->recv = fec_recv;
	683	edev->halt = fec_halt;
	684
	685	fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
	686	fec->bd = bd;
	687
	688	fec->xcv_type = MII100;
	689
	690	/* Reset chip. */
	691	writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
	692	while (readl(&fec->eth->ecntrl) & 1)
	693	udelay(10);
	694
	695	/*
	696	* Set interrupt mask register
	697	*/
	698	writel(0x00000000, &fec->eth->imask);
	699
	700	/*
	701	* Clear FEC-Lite interrupt event register(IEVENT)
	702	*/
	703	writel(0xffffffff, &fec->eth->ievent);
	704
	705	/*
	706	* Set FEC-Lite receive control register(R_CNTRL):
	707	*/
	708	/*
	709	* Frame length=1518; MII mode;
	710	*/
	711	writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
4294b248	712	fec_mii_setspeed(fec);
0b23fb36 IY	713
	714	sprintf(edev->name, "FEC_MXC");
	715
	716	miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
	717
	718	eth_register(edev);
	719
4294b248	720	if (fec_get_hwaddr(edev, ethaddr) == 0) {
0b23fb36	721	printf("got MAC address from EEPROM: %pM\n", ethaddr);
4294b248 SB	722	memcpy(edev->enetaddr, ethaddr, 6);
4294b248 SB	723	fec_set_hwaddr(edev);
0b23fb36	724	}
0b23fb36 IY	725
	726	return 0;
	727	}
	728
	729	int fecmxc_initialize(bd_t *bd)
	730	{
	731	int lout = 1;
	732
	733	debug("eth_init: fec_probe(bd)\n");
	734	lout = fec_probe(bd);
	735
	736	return lout;
	737	}