[people/ms/u-boot.git] / drivers / net / sh_eth.c

/*
 * sh_eth.c - Driver for Renesas ethernet controler.
 *
 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/errno.h>
#include <asm/io.h>

#include "sh_eth.h"

#ifndef CONFIG_SH_ETHER_USE_PORT
# error "Please define CONFIG_SH_ETHER_USE_PORT"
#endif
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
#define flush_cache_wback(addr, len)	\
			dcache_wback_range((u32)addr, (u32)(addr + len - 1))
#else
#define flush_cache_wback(...)
#endif

#define TIMEOUT_CNT 1000

int sh_eth_send(struct eth_device *dev, void *packet, int len)
{
	struct sh_eth_dev *eth = dev->priv;
	int port = eth->port, ret = 0, timeout;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (!packet || len > 0xffff) {
		printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
		ret = -EINVAL;
		goto err;
	}

	/* packet must be a 4 byte boundary */
	if ((int)packet & 3) {
		printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
		ret = -EFAULT;
		goto err;
	}

	/* Update tx descriptor */
	flush_cache_wback(packet, len);
	port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
	port_info->tx_desc_cur->td1 = len << 16;
	/* Must preserve the end of descriptor list indication */
	if (port_info->tx_desc_cur->td0 & TD_TDLE)
		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
	else
		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;

	/* Restart the transmitter if disabled */
	if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
		sh_eth_write(eth, EDTRR_TRNS, EDTRR);

	/* Wait until packet is transmitted */
	timeout = TIMEOUT_CNT;
	while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
		udelay(100);

	if (timeout < 0) {
		printf(SHETHER_NAME ": transmit timeout\n");
		ret = -ETIMEDOUT;
		goto err;
	}

	port_info->tx_desc_cur++;
	if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
		port_info->tx_desc_cur = port_info->tx_desc_base;

err:
	return ret;
}

int sh_eth_recv(struct eth_device *dev)
{
	struct sh_eth_dev *eth = dev->priv;
	int port = eth->port, len = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	uchar *packet;

	/* Check if the rx descriptor is ready */
	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
		/* Check for errors */
		if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
			len = port_info->rx_desc_cur->rd1 & 0xffff;
			packet = (uchar *)
				ADDR_TO_P2(port_info->rx_desc_cur->rd2);
			NetReceive(packet, len);
		}

		/* Make current descriptor available again */
		if (port_info->rx_desc_cur->rd0 & RD_RDLE)
			port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
		else
			port_info->rx_desc_cur->rd0 = RD_RACT;

		/* Point to the next descriptor */
		port_info->rx_desc_cur++;
		if (port_info->rx_desc_cur >=
		    port_info->rx_desc_base + NUM_RX_DESC)
			port_info->rx_desc_cur = port_info->rx_desc_base;
	}

	/* Restart the receiver if disabled */
	if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
		sh_eth_write(eth, EDRRR_R, EDRRR);

	return len;
}

static int sh_eth_reset(struct sh_eth_dev *eth)
{
#if defined(SH_ETH_TYPE_GETHER)
	int ret = 0, i;

	/* Start e-dmac transmitter and receiver */
	sh_eth_write(eth, EDSR_ENALL, EDSR);

	/* Perform a software reset and wait for it to complete */
	sh_eth_write(eth, EDMR_SRST, EDMR);
	for (i = 0; i < TIMEOUT_CNT ; i++) {
		if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
			break;
		udelay(1000);
	}

	if (i == TIMEOUT_CNT) {
		printf(SHETHER_NAME  ": Software reset timeout\n");
		ret = -EIO;
	}

	return ret;
#else
	sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
	udelay(3000);
	sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);

	return 0;
#endif
}

static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
{
	int port = eth->port, i, ret = 0;
	u32 tmp_addr;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct tx_desc_s *cur_tx_desc;

	/*
	 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
	 */
	port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
						 sizeof(struct tx_desc_s) +
						 TX_DESC_SIZE - 1);
	if (!port_info->tx_desc_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err;
	}

	tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
			  ~(TX_DESC_SIZE - 1));
	flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
	/* Make sure we use a P2 address (non-cacheable) */
	port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
	port_info->tx_desc_cur = port_info->tx_desc_base;

	/* Initialize all descriptors */
	for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
	     cur_tx_desc++, i++) {
		cur_tx_desc->td0 = 0x00;
		cur_tx_desc->td1 = 0x00;
		cur_tx_desc->td2 = 0x00;
	}

	/* Mark the end of the descriptors */
	cur_tx_desc--;
	cur_tx_desc->td0 |= TD_TDLE;

	/* Point the controller to the tx descriptor list. Must use physical
	   addresses */
	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
	sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
	sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
#endif

err:
	return ret;
}

static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
{
	int port = eth->port, i , ret = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct rx_desc_s *cur_rx_desc;
	u32 tmp_addr;
	u8 *rx_buf;

	/*
	 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
	 */
	port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
						 sizeof(struct rx_desc_s) +
						 RX_DESC_SIZE - 1);
	if (!port_info->rx_desc_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err;
	}

	tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
			  ~(RX_DESC_SIZE - 1));
	flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
	/* Make sure we use a P2 address (non-cacheable) */
	port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);

	port_info->rx_desc_cur = port_info->rx_desc_base;

	/*
	 * Allocate rx data buffers. They must be 32 bytes aligned  and in
	 * P2 area
	 */
	port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
	if (!port_info->rx_buf_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err_buf_malloc;
	}

	tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
			  ~(32 - 1));
	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);

	/* Initialize all descriptors */
	for (cur_rx_desc = port_info->rx_desc_base,
	     rx_buf = port_info->rx_buf_base, i = 0;
	     i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
		cur_rx_desc->rd0 = RD_RACT;
		cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
		cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
	}

	/* Mark the end of the descriptors */
	cur_rx_desc--;
	cur_rx_desc->rd0 |= RD_RDLE;

	/* Point the controller to the rx descriptor list */
	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
	sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
	sh_eth_write(eth, RDFFR_RDLF, RDFFR);
#endif

	return ret;

err_buf_malloc:
	free(port_info->rx_desc_malloc);
	port_info->rx_desc_malloc = NULL;

err:
	return ret;
}

static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
{
	int port = eth->port;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (port_info->tx_desc_malloc) {
		free(port_info->tx_desc_malloc);
		port_info->tx_desc_malloc = NULL;
	}
}

static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
{
	int port = eth->port;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (port_info->rx_desc_malloc) {
		free(port_info->rx_desc_malloc);
		port_info->rx_desc_malloc = NULL;
	}

	if (port_info->rx_buf_malloc) {
		free(port_info->rx_buf_malloc);
		port_info->rx_buf_malloc = NULL;
	}
}

static int sh_eth_desc_init(struct sh_eth_dev *eth)
{
	int ret = 0;

	ret = sh_eth_tx_desc_init(eth);
	if (ret)
		goto err_tx_init;

	ret = sh_eth_rx_desc_init(eth);
	if (ret)
		goto err_rx_init;

	return ret;
err_rx_init:
	sh_eth_tx_desc_free(eth);

err_tx_init:
	return ret;
}

static int sh_eth_phy_config(struct sh_eth_dev *eth)
{
	int port = eth->port, ret = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct eth_device *dev = port_info->dev;
	struct phy_device *phydev;

	phydev = phy_connect(
			miiphy_get_dev_by_name(dev->name),
			port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
	port_info->phydev = phydev;
	phy_config(phydev);

	return ret;
}

static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
{
	int port = eth->port, ret = 0;
	u32 val;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct eth_device *dev = port_info->dev;
	struct phy_device *phy;

	/* Configure e-dmac registers */
	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL,
		     EDMR);
	sh_eth_write(eth, 0, EESIPR);
	sh_eth_write(eth, 0, TRSCER);
	sh_eth_write(eth, 0, TFTR);
	sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
	sh_eth_write(eth, RMCR_RST, RMCR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, 0, RPADIR);
#endif
	sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);

	/* Configure e-mac registers */
	sh_eth_write(eth, 0, ECSIPR);

	/* Set Mac address */
	val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
	    dev->enetaddr[2] << 8 | dev->enetaddr[3];
	sh_eth_write(eth, val, MAHR);

	val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
	sh_eth_write(eth, val, MALR);

	sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, 0, PIPR);
	sh_eth_write(eth, APR_AP, APR);
	sh_eth_write(eth, MPR_MP, MPR);
	sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
#endif

#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#endif
	/* Configure phy */
	ret = sh_eth_phy_config(eth);
	if (ret) {
		printf(SHETHER_NAME ": phy config timeout\n");
		goto err_phy_cfg;
	}
	phy = port_info->phydev;
	ret = phy_startup(phy);
	if (ret) {
		printf(SHETHER_NAME ": phy startup failure\n");
		return ret;
	}

	val = 0;

	/* Set the transfer speed */
	if (phy->speed == 100) {
		printf(SHETHER_NAME ": 100Base/");
#if defined(SH_ETH_TYPE_GETHER)
		sh_eth_write(eth, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
		sh_eth_write(eth, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724)
		val = ECMR_RTM;
#endif
	} else if (phy->speed == 10) {
		printf(SHETHER_NAME ": 10Base/");
#if defined(SH_ETH_TYPE_GETHER)
		sh_eth_write(eth, GECMR_10B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
		sh_eth_write(eth, 0, RTRATE);
#endif
	}
#if defined(SH_ETH_TYPE_GETHER)
	else if (phy->speed == 1000) {
		printf(SHETHER_NAME ": 1000Base/");
		sh_eth_write(eth, GECMR_1000B, GECMR);
	}
#endif

	/* Check if full duplex mode is supported by the phy */
	if (phy->duplex) {
		printf("Full\n");
		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
			     ECMR);
	} else {
		printf("Half\n");
		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
	}

	return ret;

err_phy_cfg:
	return ret;
}

static void sh_eth_start(struct sh_eth_dev *eth)
{
	/*
	 * Enable the e-dmac receiver only. The transmitter will be enabled when
	 * we have something to transmit
	 */
	sh_eth_write(eth, EDRRR_R, EDRRR);
}

static void sh_eth_stop(struct sh_eth_dev *eth)
{
	sh_eth_write(eth, ~EDRRR_R, EDRRR);
}

int sh_eth_init(struct eth_device *dev, bd_t *bd)
{
	int ret = 0;
	struct sh_eth_dev *eth = dev->priv;

	ret = sh_eth_reset(eth);
	if (ret)
		goto err;

	ret = sh_eth_desc_init(eth);
	if (ret)
		goto err;

	ret = sh_eth_config(eth, bd);
	if (ret)
		goto err_config;

	sh_eth_start(eth);

	return ret;

err_config:
	sh_eth_tx_desc_free(eth);
	sh_eth_rx_desc_free(eth);

err:
	return ret;
}

void sh_eth_halt(struct eth_device *dev)
{
	struct sh_eth_dev *eth = dev->priv;
	sh_eth_stop(eth);
}

int sh_eth_initialize(bd_t *bd)
{
    int ret = 0;
	struct sh_eth_dev *eth = NULL;
    struct eth_device *dev = NULL;

    eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
	if (!eth) {
		printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
		ret = -ENOMEM;
		goto err;
	}

    dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	if (!dev) {
		printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
		ret = -ENOMEM;
		goto err;
	}
    memset(dev, 0, sizeof(struct eth_device));
    memset(eth, 0, sizeof(struct sh_eth_dev));

	eth->port = CONFIG_SH_ETHER_USE_PORT;
	eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;

    dev->priv = (void *)eth;
    dev->iobase = 0;
    dev->init = sh_eth_init;
    dev->halt = sh_eth_halt;
    dev->send = sh_eth_send;
    dev->recv = sh_eth_recv;
    eth->port_info[eth->port].dev = dev;

	sprintf(dev->name, SHETHER_NAME);

    /* Register Device to EtherNet subsystem  */
    eth_register(dev);

	bb_miiphy_buses[0].priv = eth;
	miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);

	if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
		puts("Please set MAC address\n");

	return ret;

err:
	if (dev)
		free(dev);

	if (eth)
		free(eth);

	printf(SHETHER_NAME ": Failed\n");
	return ret;
}

/******* for bb_miiphy *******/
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct sh_eth_dev *eth = bus->priv;

	sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);

	return 0;
}

static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct sh_eth_dev *eth = bus->priv;

	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);

	return 0;
}

static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct sh_eth_dev *eth = bus->priv;

	if (v)
		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
	else
		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);

	return 0;
}

static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct sh_eth_dev *eth = bus->priv;

	*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;

	return 0;
}

static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct sh_eth_dev *eth = bus->priv;

	if (v)
		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
	else
		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);

	return 0;
}

static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(10);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name		= "sh_eth",
		.init		= sh_eth_bb_init,
		.mdio_active	= sh_eth_bb_mdio_active,
		.mdio_tristate	= sh_eth_bb_mdio_tristate,
		.set_mdio	= sh_eth_bb_set_mdio,
		.get_mdio	= sh_eth_bb_get_mdio,
		.set_mdc	= sh_eth_bb_set_mdc,
		.delay		= sh_eth_bb_delay,
	}
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
Commit	Line	Data
9751ee09	1	/*
26235093	2	* sh_eth.c - Driver for Renesas ethernet controler.
9751ee09	3	*
3bb4cc31 NI	4	* Copyright (C) 2008, 2011 Renesas Solutions Corp.
3bb4cc31 NI	5	* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
9751ee09 NI	6	* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
9751ee09 NI	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
9751ee09 NI	9	*/
	10
	11	#include <config.h>
	12	#include <common.h>
	13	#include <malloc.h>
	14	#include <net.h>
bd3980cc	15	#include <netdev.h>
bd1024b0	16	#include <miiphy.h>
9751ee09 NI	17	#include <asm/errno.h>
	18	#include <asm/io.h>
	19
	20	#include "sh_eth.h"
	21
	22	#ifndef CONFIG_SH_ETHER_USE_PORT
	23	# error "Please define CONFIG_SH_ETHER_USE_PORT"
	24	#endif
	25	#ifndef CONFIG_SH_ETHER_PHY_ADDR
	26	# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
	27	#endif
68260aab YS	28	#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
	29	#define flush_cache_wback(addr, len) \
	30	dcache_wback_range((u32)addr, (u32)(addr + len - 1))
	31	#else
	32	#define flush_cache_wback(...)
	33	#endif
9751ee09	34
4ba62c72 NI	35	#define TIMEOUT_CNT 1000
4ba62c72 NI	36
10cbe3b6	37	int sh_eth_send(struct eth_device dev, void packet, int len)
9751ee09	38	{
bd3980cc NI	39	struct sh_eth_dev *eth = dev->priv;
	40	int port = eth->port, ret = 0, timeout;
	41	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	42
9751ee09 NI	43	if (!packet \|\| len > 0xffff) {
bd3980cc NI	44	printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
	45	ret = -EINVAL;
	46	goto err;
9751ee09 NI	47	}
	48
	49	/* packet must be a 4 byte boundary */
ee6ec5d4	50	if ((int)packet & 3) {
bd3980cc NI	51	printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
	52	ret = -EFAULT;
	53	goto err;
9751ee09 NI	54	}
	55
	56	/* Update tx descriptor */
68260aab	57	flush_cache_wback(packet, len);
9751ee09 NI	58	port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
	59	port_info->tx_desc_cur->td1 = len << 16;
	60	/* Must preserve the end of descriptor list indication */
	61	if (port_info->tx_desc_cur->td0 & TD_TDLE)
	62	port_info->tx_desc_cur->td0 = TD_TACT \| TD_TFP \| TD_TDLE;
	63	else
	64	port_info->tx_desc_cur->td0 = TD_TACT \| TD_TFP;
	65
	66	/* Restart the transmitter if disabled */
49afb8ca YS	67	if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
49afb8ca YS	68	sh_eth_write(eth, EDTRR_TRNS, EDTRR);
9751ee09 NI	69
9751ee09 NI	70	/* Wait until packet is transmitted */
4ba62c72	71	timeout = TIMEOUT_CNT;
9751ee09 NI	72	while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
	73	udelay(100);
	74
	75	if (timeout < 0) {
bd3980cc NI	76	printf(SHETHER_NAME ": transmit timeout\n");
bd3980cc NI	77	ret = -ETIMEDOUT;
9751ee09 NI	78	goto err;
	79	}
	80
9751ee09 NI	81	port_info->tx_desc_cur++;
	82	if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
	83	port_info->tx_desc_cur = port_info->tx_desc_base;
	84
bd3980cc NI	85	err:
bd3980cc NI	86	return ret;
9751ee09 NI	87	}
9751ee09 NI	88
bd3980cc	89	int sh_eth_recv(struct eth_device *dev)
9751ee09	90	{
bd3980cc NI	91	struct sh_eth_dev *eth = dev->priv;
	92	int port = eth->port, len = 0;
	93	struct sh_eth_info *port_info = &eth->port_info[port];
10cbe3b6	94	uchar *packet;
9751ee09 NI	95
	96	/* Check if the rx descriptor is ready */
	97	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
	98	/* Check for errors */
	99	if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
	100	len = port_info->rx_desc_cur->rd1 & 0xffff;
10cbe3b6 JH	101	packet = (uchar *)
10cbe3b6 JH	102	ADDR_TO_P2(port_info->rx_desc_cur->rd2);
9751ee09 NI	103	NetReceive(packet, len);
	104	}
	105
	106	/* Make current descriptor available again */
	107	if (port_info->rx_desc_cur->rd0 & RD_RDLE)
	108	port_info->rx_desc_cur->rd0 = RD_RACT \| RD_RDLE;
	109	else
	110	port_info->rx_desc_cur->rd0 = RD_RACT;
	111
	112	/* Point to the next descriptor */
	113	port_info->rx_desc_cur++;
	114	if (port_info->rx_desc_cur >=
	115	port_info->rx_desc_base + NUM_RX_DESC)
	116	port_info->rx_desc_cur = port_info->rx_desc_base;
	117	}
	118
	119	/* Restart the receiver if disabled */
49afb8ca YS	120	if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
49afb8ca YS	121	sh_eth_write(eth, EDRRR_R, EDRRR);
9751ee09 NI	122
	123	return len;
	124	}
	125
bd3980cc	126	static int sh_eth_reset(struct sh_eth_dev *eth)
9751ee09	127	{
26235093	128	#if defined(SH_ETH_TYPE_GETHER)
bd3980cc	129	int ret = 0, i;
9751ee09 NI	130
9751ee09 NI	131	/* Start e-dmac transmitter and receiver */
49afb8ca	132	sh_eth_write(eth, EDSR_ENALL, EDSR);
9751ee09 NI	133
9751ee09 NI	134	/* Perform a software reset and wait for it to complete */
49afb8ca	135	sh_eth_write(eth, EDMR_SRST, EDMR);
4ba62c72	136	for (i = 0; i < TIMEOUT_CNT ; i++) {
49afb8ca	137	if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
9751ee09 NI	138	break;
	139	udelay(1000);
	140	}
	141
4ba62c72	142	if (i == TIMEOUT_CNT) {
bd3980cc NI	143	printf(SHETHER_NAME ": Software reset timeout\n");
bd3980cc NI	144	ret = -EIO;
9751ee09	145	}
bd3980cc NI	146
bd3980cc NI	147	return ret;
903de461	148	#else
49afb8ca	149	sh_eth_write(eth, sh_eth_read(eth, EDMR) \| EDMR_SRST, EDMR);
903de461	150	udelay(3000);
49afb8ca	151	sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
903de461 YS	152
	153	return 0;
	154	#endif
9751ee09 NI	155	}
9751ee09 NI	156
bd3980cc	157	static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
9751ee09	158	{
bd3980cc	159	int port = eth->port, i, ret = 0;
9751ee09	160	u32 tmp_addr;
bd3980cc	161	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09	162	struct tx_desc_s *cur_tx_desc;
9751ee09	163
bd3980cc NI	164	/*
	165	* Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
	166	*/
	167	port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
9751ee09	168	sizeof(struct tx_desc_s) +
bd3980cc NI	169	TX_DESC_SIZE - 1);
	170	if (!port_info->tx_desc_malloc) {
	171	printf(SHETHER_NAME ": malloc failed\n");
	172	ret = -ENOMEM;
	173	goto err;
9751ee09	174	}
bd3980cc	175
9751ee09 NI	176	tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
9751ee09 NI	177	~(TX_DESC_SIZE - 1));
68260aab	178	flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
9751ee09 NI	179	/* Make sure we use a P2 address (non-cacheable) */
9751ee09 NI	180	port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
9751ee09 NI	181	port_info->tx_desc_cur = port_info->tx_desc_base;
	182
	183	/* Initialize all descriptors */
	184	for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
	185	cur_tx_desc++, i++) {
	186	cur_tx_desc->td0 = 0x00;
	187	cur_tx_desc->td1 = 0x00;
	188	cur_tx_desc->td2 = 0x00;
	189	}
	190
	191	/* Mark the end of the descriptors */
	192	cur_tx_desc--;
	193	cur_tx_desc->td0 \|= TD_TDLE;
	194
	195	/* Point the controller to the tx descriptor list. Must use physical
	196	addresses */
49afb8ca	197	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
26235093	198	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca YS	199	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
	200	sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
	201	sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
903de461	202	#endif
9751ee09	203
bd3980cc NI	204	err:
bd3980cc NI	205	return ret;
9751ee09 NI	206	}
9751ee09 NI	207
bd3980cc	208	static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
9751ee09	209	{
bd3980cc NI	210	int port = eth->port, i , ret = 0;
bd3980cc NI	211	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09	212	struct rx_desc_s *cur_rx_desc;
bd3980cc	213	u32 tmp_addr;
9751ee09	214	u8 *rx_buf;
9751ee09	215
bd3980cc NI	216	/*
	217	* Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
	218	*/
	219	port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
9751ee09	220	sizeof(struct rx_desc_s) +
bd3980cc NI	221	RX_DESC_SIZE - 1);
	222	if (!port_info->rx_desc_malloc) {
	223	printf(SHETHER_NAME ": malloc failed\n");
	224	ret = -ENOMEM;
	225	goto err;
9751ee09	226	}
bd3980cc	227
9751ee09 NI	228	tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
9751ee09 NI	229	~(RX_DESC_SIZE - 1));
68260aab	230	flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
9751ee09 NI	231	/* Make sure we use a P2 address (non-cacheable) */
	232	port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
	233
	234	port_info->rx_desc_cur = port_info->rx_desc_base;
	235
bd3980cc NI	236	/*
	237	* Allocate rx data buffers. They must be 32 bytes aligned and in
	238	* P2 area
	239	*/
	240	port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
	241	if (!port_info->rx_buf_malloc) {
	242	printf(SHETHER_NAME ": malloc failed\n");
	243	ret = -ENOMEM;
	244	goto err_buf_malloc;
9751ee09	245	}
bd3980cc	246
9751ee09 NI	247	tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
	248	~(32 - 1));
	249	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
	250
	251	/* Initialize all descriptors */
	252	for (cur_rx_desc = port_info->rx_desc_base,
	253	rx_buf = port_info->rx_buf_base, i = 0;
	254	i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
	255	cur_rx_desc->rd0 = RD_RACT;
	256	cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
	257	cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
	258	}
	259
	260	/* Mark the end of the descriptors */
	261	cur_rx_desc--;
	262	cur_rx_desc->rd0 \|= RD_RDLE;
	263
	264	/* Point the controller to the rx descriptor list */
49afb8ca	265	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
26235093	266	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca YS	267	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
	268	sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
	269	sh_eth_write(eth, RDFFR_RDLF, RDFFR);
903de461	270	#endif
9751ee09	271
bd3980cc NI	272	return ret;
	273
	274	err_buf_malloc:
	275	free(port_info->rx_desc_malloc);
	276	port_info->rx_desc_malloc = NULL;
	277
	278	err:
	279	return ret;
9751ee09 NI	280	}
9751ee09 NI	281
bd3980cc	282	static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
9751ee09	283	{
bd3980cc NI	284	int port = eth->port;
bd3980cc NI	285	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	286
	287	if (port_info->tx_desc_malloc) {
	288	free(port_info->tx_desc_malloc);
	289	port_info->tx_desc_malloc = NULL;
	290	}
bd3980cc NI	291	}
	292
	293	static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
	294	{
	295	int port = eth->port;
	296	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	297
	298	if (port_info->rx_desc_malloc) {
	299	free(port_info->rx_desc_malloc);
	300	port_info->rx_desc_malloc = NULL;
	301	}
	302
	303	if (port_info->rx_buf_malloc) {
	304	free(port_info->rx_buf_malloc);
	305	port_info->rx_buf_malloc = NULL;
	306	}
	307	}
	308
bd3980cc	309	static int sh_eth_desc_init(struct sh_eth_dev *eth)
9751ee09	310	{
bd3980cc	311	int ret = 0;
9751ee09	312
bd3980cc NI	313	ret = sh_eth_tx_desc_init(eth);
	314	if (ret)
	315	goto err_tx_init;
9751ee09	316
bd3980cc NI	317	ret = sh_eth_rx_desc_init(eth);
	318	if (ret)
	319	goto err_rx_init;
	320
	321	return ret;
	322	err_rx_init:
	323	sh_eth_tx_desc_free(eth);
	324
	325	err_tx_init:
	326	return ret;
9751ee09 NI	327	}
9751ee09 NI	328
bd3980cc	329	static int sh_eth_phy_config(struct sh_eth_dev *eth)
9751ee09	330	{
bd1024b0	331	int port = eth->port, ret = 0;
bd3980cc	332	struct sh_eth_info *port_info = &eth->port_info[port];
bd1024b0 YS	333	struct eth_device *dev = port_info->dev;
bd1024b0 YS	334	struct phy_device *phydev;
9751ee09	335
ee6ec5d4 NI	336	phydev = phy_connect(
ee6ec5d4 NI	337	miiphy_get_dev_by_name(dev->name),
4398d559	338	port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
bd1024b0 YS	339	port_info->phydev = phydev;
bd1024b0 YS	340	phy_config(phydev);
bd3980cc	341
bd3980cc	342	return ret;
9751ee09 NI	343	}
9751ee09 NI	344
bd3980cc	345	static int sh_eth_config(struct sh_eth_dev eth, bd_t bd)
9751ee09	346	{
bd3980cc	347	int port = eth->port, ret = 0;
bd1024b0	348	u32 val;
bd3980cc	349	struct sh_eth_info *port_info = &eth->port_info[port];
c527ce92	350	struct eth_device *dev = port_info->dev;
bd1024b0	351	struct phy_device *phy;
9751ee09 NI	352
9751ee09 NI	353	/* Configure e-dmac registers */
49afb8ca YS	354	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) \| EDMR_EL,
	355	EDMR);
	356	sh_eth_write(eth, 0, EESIPR);
	357	sh_eth_write(eth, 0, TRSCER);
	358	sh_eth_write(eth, 0, TFTR);
	359	sh_eth_write(eth, (FIFO_SIZE_T \| FIFO_SIZE_R), FDR);
	360	sh_eth_write(eth, RMCR_RST, RMCR);
26235093	361	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca	362	sh_eth_write(eth, 0, RPADIR);
903de461	363	#endif
49afb8ca	364	sh_eth_write(eth, (FIFO_F_D_RFF \| FIFO_F_D_RFD), FCFTR);
9751ee09 NI	365
9751ee09 NI	366	/* Configure e-mac registers */
49afb8ca	367	sh_eth_write(eth, 0, ECSIPR);
9751ee09 NI	368
9751ee09 NI	369	/* Set Mac address */
c527ce92 MF	370	val = dev->enetaddr[0] << 24 \| dev->enetaddr[1] << 16 \|
c527ce92 MF	371	dev->enetaddr[2] << 8 \| dev->enetaddr[3];
49afb8ca	372	sh_eth_write(eth, val, MAHR);
9751ee09	373
c527ce92	374	val = dev->enetaddr[4] << 8 \| dev->enetaddr[5];
49afb8ca	375	sh_eth_write(eth, val, MALR);
9751ee09	376
49afb8ca	377	sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
26235093	378	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca YS	379	sh_eth_write(eth, 0, PIPR);
	380	sh_eth_write(eth, APR_AP, APR);
	381	sh_eth_write(eth, MPR_MP, MPR);
	382	sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
903de461	383	#endif
3bb4cc31	384
dcd5a593	385	#if defined(CONFIG_CPU_SH7734) \|\| defined(CONFIG_R8A7740)
49afb8ca	386	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
4398d559	387	#endif
9751ee09	388	/* Configure phy */
bd3980cc NI	389	ret = sh_eth_phy_config(eth);
bd3980cc NI	390	if (ret) {
88a4c2e7	391	printf(SHETHER_NAME ": phy config timeout\n");
bd3980cc NI	392	goto err_phy_cfg;
bd3980cc NI	393	}
bd1024b0	394	phy = port_info->phydev;
11af8d65 TT	395	ret = phy_startup(phy);
	396	if (ret) {
	397	printf(SHETHER_NAME ": phy startup failure\n");
	398	return ret;
	399	}
9751ee09	400
3bb4cc31 NI	401	val = 0;
3bb4cc31 NI	402
9751ee09	403	/* Set the transfer speed */
bd1024b0	404	if (phy->speed == 100) {
bd3980cc	405	printf(SHETHER_NAME ": 100Base/");
26235093	406	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca	407	sh_eth_write(eth, GECMR_100B, GECMR);
e3bb3254	408	#elif defined(CONFIG_CPU_SH7757) \|\| defined(CONFIG_CPU_SH7752)
49afb8ca	409	sh_eth_write(eth, 1, RTRATE);
3bb4cc31 NI	410	#elif defined(CONFIG_CPU_SH7724)
	411	val = ECMR_RTM;
	412	#endif
bd1024b0	413	} else if (phy->speed == 10) {
bd3980cc	414	printf(SHETHER_NAME ": 10Base/");
26235093	415	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca	416	sh_eth_write(eth, GECMR_10B, GECMR);
e3bb3254	417	#elif defined(CONFIG_CPU_SH7757) \|\| defined(CONFIG_CPU_SH7752)
49afb8ca	418	sh_eth_write(eth, 0, RTRATE);
903de461	419	#endif
3bb4cc31	420	}
26235093	421	#if defined(SH_ETH_TYPE_GETHER)
4398d559 NI	422	else if (phy->speed == 1000) {
4398d559 NI	423	printf(SHETHER_NAME ": 1000Base/");
49afb8ca	424	sh_eth_write(eth, GECMR_1000B, GECMR);
4398d559 NI	425	}
4398d559 NI	426	#endif
9751ee09 NI	427
9751ee09 NI	428	/* Check if full duplex mode is supported by the phy */
bd1024b0	429	if (phy->duplex) {
9751ee09	430	printf("Full\n");
49afb8ca YS	431	sh_eth_write(eth, val \| (ECMR_CHG_DM\|ECMR_RE\|ECMR_TE\|ECMR_DM),
49afb8ca YS	432	ECMR);
9751ee09 NI	433	} else {
9751ee09 NI	434	printf("Half\n");
49afb8ca	435	sh_eth_write(eth, val \| (ECMR_CHG_DM\|ECMR_RE\|ECMR_TE), ECMR);
9751ee09	436	}
bd3980cc NI	437
	438	return ret;
	439
	440	err_phy_cfg:
	441	return ret;
9751ee09 NI	442	}
9751ee09 NI	443
bd3980cc	444	static void sh_eth_start(struct sh_eth_dev *eth)
9751ee09 NI	445	{
	446	/*
	447	* Enable the e-dmac receiver only. The transmitter will be enabled when
	448	* we have something to transmit
	449	*/
49afb8ca	450	sh_eth_write(eth, EDRRR_R, EDRRR);
bd3980cc	451	}
9751ee09	452
bd3980cc NI	453	static void sh_eth_stop(struct sh_eth_dev *eth)
bd3980cc NI	454	{
49afb8ca	455	sh_eth_write(eth, ~EDRRR_R, EDRRR);
9751ee09 NI	456	}
9751ee09 NI	457
bd3980cc	458	int sh_eth_init(struct eth_device dev, bd_t bd)
9751ee09	459	{
bd3980cc NI	460	int ret = 0;
bd3980cc NI	461	struct sh_eth_dev *eth = dev->priv;
9751ee09	462
bd3980cc NI	463	ret = sh_eth_reset(eth);
	464	if (ret)
	465	goto err;
9751ee09	466
bd3980cc NI	467	ret = sh_eth_desc_init(eth);
	468	if (ret)
	469	goto err;
9751ee09	470
bd3980cc NI	471	ret = sh_eth_config(eth, bd);
	472	if (ret)
	473	goto err_config;
	474
	475	sh_eth_start(eth);
	476
	477	return ret;
9751ee09	478
bd3980cc NI	479	err_config:
	480	sh_eth_tx_desc_free(eth);
	481	sh_eth_rx_desc_free(eth);
	482
	483	err:
	484	return ret;
	485	}
	486
	487	void sh_eth_halt(struct eth_device *dev)
	488	{
	489	struct sh_eth_dev *eth = dev->priv;
bd3980cc NI	490	sh_eth_stop(eth);
	491	}
	492
	493	int sh_eth_initialize(bd_t *bd)
	494	{
	495	int ret = 0;
	496	struct sh_eth_dev *eth = NULL;
	497	struct eth_device *dev = NULL;
	498
	499	eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
	500	if (!eth) {
	501	printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
	502	ret = -ENOMEM;
9751ee09	503	goto err;
bd3980cc	504	}
9751ee09	505
bd3980cc NI	506	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	507	if (!dev) {
	508	printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
	509	ret = -ENOMEM;
	510	goto err;
	511	}
	512	memset(dev, 0, sizeof(struct eth_device));
	513	memset(eth, 0, sizeof(struct sh_eth_dev));
9751ee09	514
bd3980cc NI	515	eth->port = CONFIG_SH_ETHER_USE_PORT;
	516	eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
	517
	518	dev->priv = (void *)eth;
	519	dev->iobase = 0;
	520	dev->init = sh_eth_init;
	521	dev->halt = sh_eth_halt;
	522	dev->send = sh_eth_send;
	523	dev->recv = sh_eth_recv;
	524	eth->port_info[eth->port].dev = dev;
	525
	526	sprintf(dev->name, SHETHER_NAME);
	527
	528	/* Register Device to EtherNet subsystem */
	529	eth_register(dev);
	530
bd1024b0 YS	531	bb_miiphy_buses[0].priv = eth;
	532	miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
	533
c527ce92 MF	534	if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
c527ce92 MF	535	puts("Please set MAC address\n");
bd3980cc NI	536
bd3980cc NI	537	return ret;
9751ee09	538
9751ee09	539	err:
bd3980cc NI	540	if (dev)
	541	free(dev);
	542
	543	if (eth)
	544	free(eth);
	545
	546	printf(SHETHER_NAME ": Failed\n");
	547	return ret;
9751ee09	548	}
bd1024b0 YS	549
	550	/***** for bb_miiphy *****/
	551	static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
	552	{
	553	return 0;
	554	}
	555
	556	static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
	557	{
	558	struct sh_eth_dev *eth = bus->priv;
bd1024b0	559
49afb8ca	560	sh_eth_write(eth, sh_eth_read(eth, PIR) \| PIR_MMD, PIR);
bd1024b0 YS	561
	562	return 0;
	563	}
	564
	565	static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
	566	{
	567	struct sh_eth_dev *eth = bus->priv;
bd1024b0	568
49afb8ca	569	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
bd1024b0 YS	570
	571	return 0;
	572	}
	573
	574	static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
	575	{
	576	struct sh_eth_dev *eth = bus->priv;
bd1024b0 YS	577
bd1024b0 YS	578	if (v)
49afb8ca	579	sh_eth_write(eth, sh_eth_read(eth, PIR) \| PIR_MDO, PIR);
bd1024b0	580	else
49afb8ca	581	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
bd1024b0 YS	582
	583	return 0;
	584	}
	585
	586	static int sh_eth_bb_get_mdio(struct bb_miiphy_bus bus, int v)
	587	{
	588	struct sh_eth_dev *eth = bus->priv;
bd1024b0	589
49afb8ca	590	*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
bd1024b0 YS	591
	592	return 0;
	593	}
	594
	595	static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
	596	{
	597	struct sh_eth_dev *eth = bus->priv;
bd1024b0 YS	598
bd1024b0 YS	599	if (v)
49afb8ca	600	sh_eth_write(eth, sh_eth_read(eth, PIR) \| PIR_MDC, PIR);
bd1024b0	601	else
49afb8ca	602	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
bd1024b0 YS	603
	604	return 0;
	605	}
	606
	607	static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
	608	{
	609	udelay(10);
	610
	611	return 0;
	612	}
	613
	614	struct bb_miiphy_bus bb_miiphy_buses[] = {
	615	{
	616	.name = "sh_eth",
	617	.init = sh_eth_bb_init,
	618	.mdio_active = sh_eth_bb_mdio_active,
	619	.mdio_tristate = sh_eth_bb_mdio_tristate,
	620	.set_mdio = sh_eth_bb_set_mdio,
	621	.get_mdio = sh_eth_bb_get_mdio,
	622	.set_mdc = sh_eth_bb_set_mdc,
	623	.delay = sh_eth_bb_delay,
	624	}
	625	};
	626	int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);