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9751ee09 NI |
1 | /* |
2 | * sh_eth.c - Driver for Renesas SH7763's ethernet controler. | |
3 | * | |
4 | * Copyright (C) 2008 Renesas Solutions Corp. | |
5 | * Copyright (c) 2008 Nobuhiro Iwamatsu | |
6 | * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
24 | #include <common.h> | |
25 | #include <malloc.h> | |
26 | #include <net.h> | |
27 | #include <asm/errno.h> | |
28 | #include <asm/io.h> | |
29 | ||
30 | #include "sh_eth.h" | |
31 | ||
32 | #ifndef CONFIG_SH_ETHER_USE_PORT | |
33 | # error "Please define CONFIG_SH_ETHER_USE_PORT" | |
34 | #endif | |
35 | #ifndef CONFIG_SH_ETHER_PHY_ADDR | |
36 | # error "Please define CONFIG_SH_ETHER_PHY_ADDR" | |
37 | #endif | |
38 | ||
39 | extern int eth_init(bd_t *bd); | |
40 | extern void eth_halt(void); | |
41 | extern int eth_rx(void); | |
42 | extern int eth_send(volatile void *packet, int length); | |
43 | ||
44 | static struct dev_info_s *dev; | |
45 | ||
46 | /* | |
47 | * Bits are written to the PHY serially using the | |
48 | * PIR register, just like a bit banger. | |
49 | */ | |
50 | static void sh_eth_mii_write_phy_bits(int port, u32 val, int len) | |
51 | { | |
52 | int i; | |
53 | u32 pir; | |
54 | ||
55 | /* Bit positions is 1 less than the number of bits */ | |
56 | for (i = len - 1; i >= 0; i--) { | |
57 | /* Write direction, bit to write, clock is low */ | |
58 | pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); | |
59 | outl(pir, PIR(port)); | |
60 | udelay(1); | |
61 | /* Write direction, bit to write, clock is high */ | |
62 | pir = 3 | ((val & 1 << i) ? 1 << 2 : 0); | |
63 | outl(pir, PIR(port)); | |
64 | udelay(1); | |
65 | /* Write direction, bit to write, clock is low */ | |
66 | pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); | |
67 | outl(pir, PIR(port)); | |
68 | udelay(1); | |
69 | } | |
70 | } | |
71 | ||
72 | static void sh_eth_mii_bus_release(int port) | |
73 | { | |
74 | /* Read direction, clock is low */ | |
75 | outl(0, PIR(port)); | |
76 | udelay(1); | |
77 | /* Read direction, clock is high */ | |
78 | outl(1, PIR(port)); | |
79 | udelay(1); | |
80 | /* Read direction, clock is low */ | |
81 | outl(0, PIR(port)); | |
82 | udelay(1); | |
83 | } | |
84 | ||
85 | static void sh_eth_mii_ind_bus_release(int port) | |
86 | { | |
87 | /* Read direction, clock is low */ | |
88 | outl(0, PIR(port)); | |
89 | udelay(1); | |
90 | } | |
91 | ||
92 | static int sh_eth_mii_read_phy_bits(int port, u32 * val, int len) | |
93 | { | |
94 | int i; | |
95 | u32 pir; | |
96 | ||
97 | *val = 0; | |
98 | for (i = len - 1; i >= 0; i--) { | |
99 | /* Read direction, clock is high */ | |
100 | outl(1, PIR(port)); | |
101 | udelay(1); | |
102 | /* Read bit */ | |
103 | pir = inl(PIR(port)); | |
104 | *val |= (pir & 8) ? 1 << i : 0; | |
105 | /* Read direction, clock is low */ | |
106 | outl(0, PIR(port)); | |
107 | udelay(1); | |
108 | } | |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
113 | #define PHY_INIT 0xFFFFFFFF | |
114 | #define PHY_READ 0x02 | |
115 | #define PHY_WRITE 0x01 | |
116 | /* | |
117 | * To read a phy register, mii managements frames are sent to the phy. | |
118 | * The frames look like this: | |
119 | * pre (32 bits): 0xffff ffff | |
120 | * st (2 bits): 01 | |
121 | * op (2bits): 10: read 01: write | |
122 | * phyad (5 bits): xxxxx | |
123 | * regad (5 bits): xxxxx | |
124 | * ta (Bus release): | |
125 | * data (16 bits): read data | |
126 | */ | |
127 | static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg) | |
128 | { | |
129 | u32 val; | |
130 | ||
131 | /* Sent mii management frame */ | |
132 | /* pre */ | |
133 | sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); | |
134 | /* st (start of frame) */ | |
135 | sh_eth_mii_write_phy_bits(port, 0x1, 2); | |
136 | /* op (code) */ | |
137 | sh_eth_mii_write_phy_bits(port, PHY_READ, 2); | |
138 | /* phy address */ | |
139 | sh_eth_mii_write_phy_bits(port, phy_addr, 5); | |
140 | /* Register to read */ | |
141 | sh_eth_mii_write_phy_bits(port, reg, 5); | |
142 | ||
143 | /* Bus release */ | |
144 | sh_eth_mii_bus_release(port); | |
145 | ||
146 | /* Read register */ | |
147 | sh_eth_mii_read_phy_bits(port, &val, 16); | |
148 | ||
149 | return val; | |
150 | } | |
151 | ||
152 | /* | |
153 | * To write a phy register, mii managements frames are sent to the phy. | |
154 | * The frames look like this: | |
155 | * pre (32 bits): 0xffff ffff | |
156 | * st (2 bits): 01 | |
157 | * op (2bits): 10: read 01: write | |
158 | * phyad (5 bits): xxxxx | |
159 | * regad (5 bits): xxxxx | |
160 | * ta (2 bits): 10 | |
161 | * data (16 bits): write data | |
162 | * idle (Independent bus release) | |
163 | */ | |
164 | static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val) | |
165 | { | |
166 | /* Sent mii management frame */ | |
167 | /* pre */ | |
168 | sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); | |
169 | /* st (start of frame) */ | |
170 | sh_eth_mii_write_phy_bits(port, 0x1, 2); | |
171 | /* op (code) */ | |
172 | sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2); | |
173 | /* phy address */ | |
174 | sh_eth_mii_write_phy_bits(port, phy_addr, 5); | |
175 | /* Register to read */ | |
176 | sh_eth_mii_write_phy_bits(port, reg, 5); | |
177 | /* ta */ | |
178 | sh_eth_mii_write_phy_bits(port, PHY_READ, 2); | |
179 | /* Write register data */ | |
180 | sh_eth_mii_write_phy_bits(port, val, 16); | |
181 | ||
182 | /* Independent bus release */ | |
183 | sh_eth_mii_ind_bus_release(port); | |
184 | } | |
185 | ||
186 | void eth_halt(void) | |
187 | { | |
188 | } | |
189 | ||
190 | int eth_send(volatile void *packet, int len) | |
191 | { | |
192 | int port = dev->port; | |
193 | struct port_info_s *port_info = &dev->port_info[port]; | |
194 | int timeout; | |
195 | int rc = 0; | |
196 | ||
197 | if (!packet || len > 0xffff) { | |
198 | printf("eth_send: Invalid argument\n"); | |
199 | return -EINVAL; | |
200 | } | |
201 | ||
202 | /* packet must be a 4 byte boundary */ | |
203 | if ((int)packet & (4 - 1)) { | |
204 | printf("eth_send: packet not 4 byte alligned\n"); | |
205 | return -EFAULT; | |
206 | } | |
207 | ||
208 | /* Update tx descriptor */ | |
209 | port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); | |
210 | port_info->tx_desc_cur->td1 = len << 16; | |
211 | /* Must preserve the end of descriptor list indication */ | |
212 | if (port_info->tx_desc_cur->td0 & TD_TDLE) | |
213 | port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; | |
214 | else | |
215 | port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; | |
216 | ||
217 | /* Restart the transmitter if disabled */ | |
218 | if (!(inl(EDTRR(port)) & EDTRR_TRNS)) | |
219 | outl(EDTRR_TRNS, EDTRR(port)); | |
220 | ||
221 | /* Wait until packet is transmitted */ | |
222 | timeout = 1000; | |
223 | while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) | |
224 | udelay(100); | |
225 | ||
226 | if (timeout < 0) { | |
227 | printf("eth_send: transmit timeout\n"); | |
228 | rc = -1; | |
229 | goto err; | |
230 | } | |
231 | ||
232 | err: | |
233 | port_info->tx_desc_cur++; | |
234 | if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) | |
235 | port_info->tx_desc_cur = port_info->tx_desc_base; | |
236 | ||
237 | return rc; | |
238 | } | |
239 | ||
240 | int eth_rx(void) | |
241 | { | |
242 | int port = dev->port; | |
243 | struct port_info_s *port_info = &dev->port_info[port]; | |
244 | int len = 0; | |
245 | volatile u8 *packet; | |
246 | ||
247 | /* Check if the rx descriptor is ready */ | |
248 | if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { | |
249 | /* Check for errors */ | |
250 | if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { | |
251 | len = port_info->rx_desc_cur->rd1 & 0xffff; | |
252 | packet = (volatile u8 *) | |
253 | ADDR_TO_P2(port_info->rx_desc_cur->rd2); | |
254 | NetReceive(packet, len); | |
255 | } | |
256 | ||
257 | /* Make current descriptor available again */ | |
258 | if (port_info->rx_desc_cur->rd0 & RD_RDLE) | |
259 | port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; | |
260 | else | |
261 | port_info->rx_desc_cur->rd0 = RD_RACT; | |
262 | ||
263 | /* Point to the next descriptor */ | |
264 | port_info->rx_desc_cur++; | |
265 | if (port_info->rx_desc_cur >= | |
266 | port_info->rx_desc_base + NUM_RX_DESC) | |
267 | port_info->rx_desc_cur = port_info->rx_desc_base; | |
268 | } | |
269 | ||
270 | /* Restart the receiver if disabled */ | |
271 | if (!(inl(EDRRR(port)) & EDRRR_R)) | |
272 | outl(EDRRR_R, EDRRR(port)); | |
273 | ||
274 | return len; | |
275 | } | |
276 | ||
277 | #define EDMR_INIT_CNT 1000 | |
278 | static int sh_eth_reset(struct dev_info_s *dev) | |
279 | { | |
280 | int port = dev->port; | |
281 | int i; | |
282 | ||
283 | /* Start e-dmac transmitter and receiver */ | |
284 | outl(EDSR_ENALL, EDSR(port)); | |
285 | ||
286 | /* Perform a software reset and wait for it to complete */ | |
287 | outl(EDMR_SRST, EDMR(port)); | |
288 | for (i = 0; i < EDMR_INIT_CNT; i++) { | |
289 | if (!(inl(EDMR(port)) & EDMR_SRST)) | |
290 | break; | |
291 | udelay(1000); | |
292 | } | |
293 | ||
294 | if (i == EDMR_INIT_CNT) { | |
295 | printf("Error: Software reset timeout\n"); | |
296 | return -1; | |
297 | } | |
298 | return 0; | |
299 | } | |
300 | ||
301 | static int sh_eth_tx_desc_init(struct dev_info_s *dev) | |
302 | { | |
303 | int port = dev->port; | |
304 | struct port_info_s *port_info = &dev->port_info[port]; | |
305 | u32 tmp_addr; | |
306 | struct tx_desc_s *cur_tx_desc; | |
307 | int i; | |
308 | ||
309 | /* Allocate tx descriptors. They must be TX_DESC_SIZE bytes | |
310 | aligned */ | |
311 | if (!(port_info->tx_desc_malloc = malloc(NUM_TX_DESC * | |
312 | sizeof(struct tx_desc_s) + | |
313 | TX_DESC_SIZE - 1))) { | |
314 | printf("Error: malloc failed\n"); | |
315 | return -ENOMEM; | |
316 | } | |
317 | tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & | |
318 | ~(TX_DESC_SIZE - 1)); | |
319 | /* Make sure we use a P2 address (non-cacheable) */ | |
320 | port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); | |
321 | ||
322 | port_info->tx_desc_cur = port_info->tx_desc_base; | |
323 | ||
324 | /* Initialize all descriptors */ | |
325 | for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; | |
326 | cur_tx_desc++, i++) { | |
327 | cur_tx_desc->td0 = 0x00; | |
328 | cur_tx_desc->td1 = 0x00; | |
329 | cur_tx_desc->td2 = 0x00; | |
330 | } | |
331 | ||
332 | /* Mark the end of the descriptors */ | |
333 | cur_tx_desc--; | |
334 | cur_tx_desc->td0 |= TD_TDLE; | |
335 | ||
336 | /* Point the controller to the tx descriptor list. Must use physical | |
337 | addresses */ | |
338 | outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); | |
339 | outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); | |
340 | outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); | |
341 | outl(0x01, TDFFR(port));/* Last discriptor bit */ | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static int sh_eth_rx_desc_init(struct dev_info_s *dev) | |
347 | { | |
348 | int port = dev->port; | |
349 | struct port_info_s *port_info = &dev->port_info[port]; | |
350 | u32 tmp_addr; | |
351 | struct rx_desc_s *cur_rx_desc; | |
352 | u8 *rx_buf; | |
353 | int i; | |
354 | ||
355 | /* Allocate rx descriptors. They must be RX_DESC_SIZE bytes | |
356 | aligned */ | |
357 | if (!(port_info->rx_desc_malloc = malloc(NUM_RX_DESC * | |
358 | sizeof(struct rx_desc_s) + | |
359 | RX_DESC_SIZE - 1))) { | |
360 | printf("Error: malloc failed\n"); | |
361 | return -ENOMEM; | |
362 | } | |
363 | tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & | |
364 | ~(RX_DESC_SIZE - 1)); | |
365 | /* Make sure we use a P2 address (non-cacheable) */ | |
366 | port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); | |
367 | ||
368 | port_info->rx_desc_cur = port_info->rx_desc_base; | |
369 | ||
370 | /* Allocate rx data buffers. They must be 32 bytes aligned and in | |
371 | P2 area */ | |
372 | if (!(port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + | |
373 | 31))) { | |
374 | printf("Error: malloc failed\n"); | |
375 | free(port_info->rx_desc_malloc); | |
376 | port_info->rx_desc_malloc = NULL; | |
377 | return -ENOMEM; | |
378 | } | |
379 | tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & | |
380 | ~(32 - 1)); | |
381 | port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); | |
382 | ||
383 | /* Initialize all descriptors */ | |
384 | for (cur_rx_desc = port_info->rx_desc_base, | |
385 | rx_buf = port_info->rx_buf_base, i = 0; | |
386 | i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { | |
387 | cur_rx_desc->rd0 = RD_RACT; | |
388 | cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; | |
389 | cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); | |
390 | } | |
391 | ||
392 | /* Mark the end of the descriptors */ | |
393 | cur_rx_desc--; | |
394 | cur_rx_desc->rd0 |= RD_RDLE; | |
395 | ||
396 | /* Point the controller to the rx descriptor list */ | |
397 | outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); | |
398 | outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); | |
399 | outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); | |
400 | outl(RDFFR_RDLF, RDFFR(port)); | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
405 | static void sh_eth_desc_free(struct dev_info_s *dev) | |
406 | { | |
407 | int port = dev->port; | |
408 | struct port_info_s *port_info = &dev->port_info[port]; | |
409 | ||
410 | if (port_info->tx_desc_malloc) { | |
411 | free(port_info->tx_desc_malloc); | |
412 | port_info->tx_desc_malloc = NULL; | |
413 | } | |
414 | ||
415 | if (port_info->rx_desc_malloc) { | |
416 | free(port_info->rx_desc_malloc); | |
417 | port_info->rx_desc_malloc = NULL; | |
418 | } | |
419 | ||
420 | if (port_info->rx_buf_malloc) { | |
421 | free(port_info->rx_buf_malloc); | |
422 | port_info->rx_buf_malloc = NULL; | |
423 | } | |
424 | } | |
425 | ||
426 | static int sh_eth_desc_init(struct dev_info_s *dev) | |
427 | { | |
428 | int rc; | |
429 | ||
430 | if ((rc = sh_eth_tx_desc_init(dev)) || (rc = sh_eth_rx_desc_init(dev))) { | |
431 | sh_eth_desc_free(dev); | |
432 | return rc; | |
433 | } | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
438 | static int sh_eth_phy_config(struct dev_info_s *dev) | |
439 | { | |
440 | int port = dev->port; | |
441 | struct port_info_s *port_info = &dev->port_info[port]; | |
442 | int timeout; | |
443 | u32 val; | |
444 | /* Reset phy */ | |
445 | sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET); | |
446 | timeout = 10; | |
447 | while (timeout--) { | |
448 | val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, PHY_CTRL); | |
449 | if (!(val & PHY_C_RESET)) | |
450 | break; | |
451 | udelay(50000); | |
452 | } | |
453 | if (timeout < 0) { | |
454 | printf("%s phy reset timeout\n", __func__); | |
455 | return -1; | |
456 | } | |
457 | ||
458 | /* Advertise 100/10 baseT full/half duplex */ | |
459 | sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA, | |
460 | (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT)); | |
461 | /* Autonegotiation, normal operation, full duplex, enable tx */ | |
462 | sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, | |
463 | (PHY_C_ANEGEN|PHY_C_RANEG)); | |
464 | /* Wait for autonegotiation to complete */ | |
465 | timeout = 100; | |
466 | while (timeout--) { | |
467 | val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); | |
468 | if (val & PHY_S_ANEGC) | |
469 | break; | |
470 | udelay(50000); | |
471 | } | |
472 | if (timeout < 0) { | |
473 | printf("sh_eth_phy_config() phy auto-negotiation failed\n"); | |
474 | return -1; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int sh_eth_config(struct dev_info_s *dev, bd_t * bd) | |
481 | { | |
482 | int port = dev->port; | |
483 | struct port_info_s *port_info = &dev->port_info[port]; | |
484 | u32 val; | |
485 | u32 phy_status; | |
486 | int rc; | |
487 | ||
488 | /* Configure e-dmac registers */ | |
489 | outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); | |
490 | outl(0, EESIPR(port)); | |
491 | outl(0, TRSCER(port)); | |
492 | outl(0, TFTR(port)); | |
493 | outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); | |
494 | outl(RMCR_RST, RMCR(port)); | |
495 | outl(0, RPADIR(port)); | |
496 | outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); | |
497 | ||
498 | /* Configure e-mac registers */ | |
499 | outl(0, ECSIPR(port)); | |
500 | ||
501 | /* Set Mac address */ | |
502 | val = bd->bi_enetaddr[0] << 24 | bd->bi_enetaddr[1] << 16 | | |
503 | bd->bi_enetaddr[2] << 8 | bd->bi_enetaddr[3]; | |
504 | outl(val, MAHR(port)); | |
505 | ||
506 | val = bd->bi_enetaddr[4] << 8 | bd->bi_enetaddr[5]; | |
507 | outl(val, MALR(port)); | |
508 | ||
509 | outl(RFLR_RFL_MIN, RFLR(port)); | |
510 | outl(0, PIPR(port)); | |
511 | outl(APR_AP, APR(port)); | |
512 | outl(MPR_MP, MPR(port)); | |
513 | outl(TPAUSER_TPAUSE, TPAUSER(port)); | |
514 | ||
515 | /* Configure phy */ | |
516 | if ((rc = sh_eth_phy_config(dev))) | |
517 | return rc; | |
518 | ||
519 | /* Read phy status to finish configuring the e-mac */ | |
520 | phy_status = sh_eth_mii_read_phy_reg(dev->port, | |
521 | dev->port_info[dev->port].phy_addr, | |
522 | 1); | |
523 | ||
524 | /* Set the transfer speed */ | |
525 | if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { | |
526 | printf("100Base/"); | |
527 | outl(GECMR_100B, GECMR(port)); | |
528 | } else { | |
529 | printf("10Base/"); | |
530 | outl(GECMR_10B, GECMR(port)); | |
531 | } | |
532 | ||
533 | /* Check if full duplex mode is supported by the phy */ | |
534 | if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { | |
535 | printf("Full\n"); | |
536 | outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); | |
537 | } else { | |
538 | printf("Half\n"); | |
539 | outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); | |
540 | } | |
541 | return 0; | |
542 | } | |
543 | ||
544 | static int sh_eth_start(struct dev_info_s *dev) | |
545 | { | |
546 | /* | |
547 | * Enable the e-dmac receiver only. The transmitter will be enabled when | |
548 | * we have something to transmit | |
549 | */ | |
550 | outl(EDRRR_R, EDRRR(dev->port)); | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
555 | static int sh_eth_get_mac(bd_t *bd) | |
556 | { | |
557 | char *s, *e; | |
558 | int i; | |
559 | ||
560 | s = getenv("ethaddr"); | |
561 | if (s != NULL) { | |
562 | for (i = 0; i < 6; ++i) { | |
563 | bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; | |
564 | if (s) | |
565 | s = (*e) ? e + 1 : e; | |
566 | } | |
567 | } else { | |
568 | puts("Please set MAC address\n"); | |
569 | } | |
570 | return 0; | |
571 | } | |
572 | ||
573 | int eth_init(bd_t *bd) | |
574 | { | |
575 | int rc; | |
576 | /* Allocate main device information structure */ | |
577 | if (!(dev = malloc(sizeof(*dev)))) { | |
578 | printf("eth_init: malloc failed\n"); | |
579 | return -ENOMEM; | |
580 | } | |
581 | ||
582 | memset(dev, 0, sizeof(*dev)); | |
583 | ||
584 | dev->port = CONFIG_SH_ETHER_USE_PORT; | |
585 | dev->port_info[dev->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; | |
586 | ||
587 | sh_eth_get_mac(bd); | |
588 | ||
589 | if ((rc = sh_eth_reset(dev)) || (rc = sh_eth_desc_init(dev))) | |
590 | goto err; | |
591 | ||
592 | if ((rc = sh_eth_config(dev, bd)) || (rc = sh_eth_start(dev))) | |
593 | goto err_desc; | |
594 | ||
595 | return 0; | |
596 | ||
597 | err_desc: | |
598 | sh_eth_desc_free(dev); | |
599 | err: | |
600 | free(dev); | |
601 | printf("eth_init: Failed\n"); | |
602 | return rc; | |
603 | } |