]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/pinctrl/rockchip/pinctrl_rk322x.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rockchip: pinctrl: Add rk322x gmac pinctrl support
[people/ms/u-boot.git] / drivers / pinctrl / rockchip / pinctrl_rk322x.c
CommitLineData
5cc9d31a
KY		 1/*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
10#include <syscon.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/grf_rk322x.h>
14#include <asm/arch/hardware.h>
15#include <asm/arch/periph.h>
16#include <dm/pinctrl.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
424324d3
DW		 20/* GRF_GPIO0A_IOMUX */
21enum {
22 GPIO0A7_SHIFT = 14,
23 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
24 GPIO0A7_GPIO = 0,
25 GPIO0A7_I2C3_SDA,
26 GPIO0A7_HDMI_DDCSDA,
27
28 GPIO0A6_SHIFT = 12,
29 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
30 GPIO0A6_GPIO = 0,
31 GPIO0A6_I2C3_SCL,
32 GPIO0A6_HDMI_DDCSCL,
33
34 GPIO0A3_SHIFT = 6,
35 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
36 GPIO0A3_GPIO = 0,
37 GPIO0A3_I2C1_SDA,
38 GPIO0A3_SDIO_CMD,
39
40 GPIO0A2_SHIFT = 4,
41 GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
42 GPIO0A2_GPIO = 0,
43 GPIO0A2_I2C1_SCL,
44
45 GPIO0A1_SHIFT = 2,
46 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
47 GPIO0A1_GPIO = 0,
48 GPIO0A1_I2C0_SDA,
49
50 GPIO0A0_SHIFT = 0,
51 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
52 GPIO0A0_GPIO = 0,
53 GPIO0A0_I2C0_SCL,
54};
55
56/* GRF_GPIO0B_IOMUX */
57enum {
58 GPIO0B7_SHIFT = 14,
59 GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
60 GPIO0B7_GPIO = 0,
61 GPIO0B7_HDMI_HDP,
62
63 GPIO0B6_SHIFT = 12,
64 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
65 GPIO0B6_GPIO = 0,
66 GPIO0B6_I2S_SDI,
67 GPIO0B6_SPI_CSN0,
68
69 GPIO0B5_SHIFT = 10,
70 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
71 GPIO0B5_GPIO = 0,
72 GPIO0B5_I2S_SDO,
73 GPIO0B5_SPI_RXD,
74
75 GPIO0B3_SHIFT = 6,
76 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
77 GPIO0B3_GPIO = 0,
78 GPIO0B3_I2S1_LRCKRX,
79 GPIO0B3_SPI_TXD,
80
81 GPIO0B1_SHIFT = 2,
82 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
83 GPIO0B1_GPIO = 0,
84 GPIO0B1_I2S_SCLK,
85 GPIO0B1_SPI_CLK,
86
87 GPIO0B0_SHIFT = 0,
88 GPIO0B0_MASK = 3,
89 GPIO0B0_GPIO = 0,
90 GPIO0B0_I2S_MCLK,
91};
92
93/* GRF_GPIO0C_IOMUX */
94enum {
95 GPIO0C4_SHIFT = 8,
96 GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
97 GPIO0C4_GPIO = 0,
98 GPIO0C4_HDMI_CECSDA,
99
100 GPIO0C1_SHIFT = 2,
101 GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
102 GPIO0C1_GPIO = 0,
103 GPIO0C1_UART0_RSTN,
104 GPIO0C1_CLK_OUT1,
105};
106
107/* GRF_GPIO0D_IOMUX */
108enum {
109 GPIO0D6_SHIFT = 12,
110 GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
111 GPIO0D6_GPIO = 0,
112 GPIO0D6_SDIO_PWREN,
113 GPIO0D6_PWM11,
114
115 GPIO0D4_SHIFT = 8,
116 GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
117 GPIO0D4_GPIO = 0,
118 GPIO0D4_PWM2,
119
120 GPIO0D3_SHIFT = 6,
121 GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
122 GPIO0D3_GPIO = 0,
123 GPIO0D3_PWM1,
124
125 GPIO0D2_SHIFT = 4,
126 GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
127 GPIO0D2_GPIO = 0,
128 GPIO0D2_PWM0,
129};
130
131/* GRF_GPIO1A_IOMUX */
132enum {
133 GPIO1A7_SHIFT = 14,
134 GPIO1A7_MASK = 1,
135 GPIO1A7_GPIO = 0,
136 GPIO1A7_SDMMC_WRPRT,
137};
138
139/* GRF_GPIO1B_IOMUX */
140enum {
141 GPIO1B7_SHIFT = 14,
142 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
143 GPIO1B7_GPIO = 0,
144 GPIO1B7_SDMMC_CMD,
145
146 GPIO1B6_SHIFT = 12,
147 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
148 GPIO1B6_GPIO = 0,
149 GPIO1B6_SDMMC_PWREN,
150
151 GPIO1B4_SHIFT = 8,
152 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
153 GPIO1B4_GPIO = 0,
154 GPIO1B4_SPI_CSN1,
155 GPIO1B4_PWM12,
156
157 GPIO1B3_SHIFT = 6,
158 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
159 GPIO1B3_GPIO = 0,
160 GPIO1B3_UART1_RSTN,
161 GPIO1B3_PWM13,
162
163 GPIO1B2_SHIFT = 4,
164 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
165 GPIO1B2_GPIO = 0,
166 GPIO1B2_UART1_SIN,
167 GPIO1B2_UART21_SIN,
168
169 GPIO1B1_SHIFT = 2,
170 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
171 GPIO1B1_GPIO = 0,
172 GPIO1B1_UART1_SOUT,
173 GPIO1B1_UART21_SOUT,
174};
175
176/* GRF_GPIO1C_IOMUX */
177enum {
178 GPIO1C7_SHIFT = 14,
179 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
180 GPIO1C7_GPIO = 0,
181 GPIO1C7_NAND_CS3,
182 GPIO1C7_EMMC_RSTNOUT,
183
184 GPIO1C6_SHIFT = 12,
185 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
186 GPIO1C6_GPIO = 0,
187 GPIO1C6_NAND_CS2,
188 GPIO1C6_EMMC_CMD,
189
190 GPIO1C5_SHIFT = 10,
191 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
192 GPIO1C5_GPIO = 0,
193 GPIO1C5_SDMMC_D3,
194 GPIO1C5_JTAG_TMS,
195
196 GPIO1C4_SHIFT = 8,
197 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
198 GPIO1C4_GPIO = 0,
199 GPIO1C4_SDMMC_D2,
200 GPIO1C4_JTAG_TCK,
201
202 GPIO1C3_SHIFT = 6,
203 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
204 GPIO1C3_GPIO = 0,
205 GPIO1C3_SDMMC_D1,
206 GPIO1C3_UART2_SIN,
207
208 GPIO1C2_SHIFT = 4,
209 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
210 GPIO1C2_GPIO = 0,
211 GPIO1C2_SDMMC_D0,
212 GPIO1C2_UART2_SOUT,
213
214 GPIO1C1_SHIFT = 2,
215 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
216 GPIO1C1_GPIO = 0,
217 GPIO1C1_SDMMC_DETN,
218
219 GPIO1C0_SHIFT = 0,
220 GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
221 GPIO1C0_GPIO = 0,
222 GPIO1C0_SDMMC_CLKOUT,
223};
224
225/* GRF_GPIO1D_IOMUX */
226enum {
227 GPIO1D7_SHIFT = 14,
228 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
229 GPIO1D7_GPIO = 0,
230 GPIO1D7_NAND_D7,
231 GPIO1D7_EMMC_D7,
232
233 GPIO1D6_SHIFT = 12,
234 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
235 GPIO1D6_GPIO = 0,
236 GPIO1D6_NAND_D6,
237 GPIO1D6_EMMC_D6,
238
239 GPIO1D5_SHIFT = 10,
240 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
241 GPIO1D5_GPIO = 0,
242 GPIO1D5_NAND_D5,
243 GPIO1D5_EMMC_D5,
244
245 GPIO1D4_SHIFT = 8,
246 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
247 GPIO1D4_GPIO = 0,
248 GPIO1D4_NAND_D4,
249 GPIO1D4_EMMC_D4,
250
251 GPIO1D3_SHIFT = 6,
252 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
253 GPIO1D3_GPIO = 0,
254 GPIO1D3_NAND_D3,
255 GPIO1D3_EMMC_D3,
256
257 GPIO1D2_SHIFT = 4,
258 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
259 GPIO1D2_GPIO = 0,
260 GPIO1D2_NAND_D2,
261 GPIO1D2_EMMC_D2,
262
263 GPIO1D1_SHIFT = 2,
264 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
265 GPIO1D1_GPIO = 0,
266 GPIO1D1_NAND_D1,
267 GPIO1D1_EMMC_D1,
268
269 GPIO1D0_SHIFT = 0,
270 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
271 GPIO1D0_GPIO = 0,
272 GPIO1D0_NAND_D0,
273 GPIO1D0_EMMC_D0,
274};
275
276/* GRF_GPIO2A_IOMUX */
277enum {
278 GPIO2A7_SHIFT = 14,
279 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
280 GPIO2A7_GPIO = 0,
281 GPIO2A7_NAND_DQS,
282 GPIO2A7_EMMC_CLKOUT,
283
284 GPIO2A5_SHIFT = 10,
285 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
286 GPIO2A5_GPIO = 0,
287 GPIO2A5_NAND_WP,
288 GPIO2A5_EMMC_PWREN,
289
290 GPIO2A4_SHIFT = 8,
291 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
292 GPIO2A4_GPIO = 0,
293 GPIO2A4_NAND_RDY,
294 GPIO2A4_EMMC_CMD,
295
296 GPIO2A3_SHIFT = 6,
297 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
298 GPIO2A3_GPIO = 0,
299 GPIO2A3_NAND_RDN,
300 GPIO2A4_SPI1_CSN1,
301
302 GPIO2A2_SHIFT = 4,
303 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
304 GPIO2A2_GPIO = 0,
305 GPIO2A2_NAND_WRN,
306 GPIO2A4_SPI1_CSN0,
307
308 GPIO2A1_SHIFT = 2,
309 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
310 GPIO2A1_GPIO = 0,
311 GPIO2A1_NAND_CLE,
312 GPIO2A1_SPI1_TXD,
313
314 GPIO2A0_SHIFT = 0,
315 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
316 GPIO2A0_GPIO = 0,
317 GPIO2A0_NAND_ALE,
318 GPIO2A0_SPI1_RXD,
319};
320
321/* GRF_GPIO2B_IOMUX */
322enum {
323 GPIO2B7_SHIFT = 14,
324 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
325 GPIO2B7_GPIO = 0,
326 GPIO2B7_GMAC_RXER,
327
328 GPIO2B6_SHIFT = 12,
329 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
330 GPIO2B6_GPIO = 0,
331 GPIO2B6_GMAC_CLK,
332 GPIO2B6_MAC_LINK,
333
334 GPIO2B5_SHIFT = 10,
335 GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
336 GPIO2B5_GPIO = 0,
337 GPIO2B5_GMAC_TXEN,
338
339 GPIO2B4_SHIFT = 8,
340 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
341 GPIO2B4_GPIO = 0,
342 GPIO2B4_GMAC_MDIO,
343
344 GPIO2B3_SHIFT = 6,
345 GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
346 GPIO2B3_GPIO = 0,
347 GPIO2B3_GMAC_RXCLK,
348
349 GPIO2B2_SHIFT = 4,
350 GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
351 GPIO2B2_GPIO = 0,
352 GPIO2B2_GMAC_CRS,
353
354 GPIO2B1_SHIFT = 2,
355 GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
356 GPIO2B1_GPIO = 0,
357 GPIO2B1_GMAC_TXCLK,
358
359 GPIO2B0_SHIFT = 0,
360 GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
361 GPIO2B0_GPIO = 0,
362 GPIO2B0_GMAC_RXDV,
363 GPIO2B0_MAC_SPEED_IOUT,
364};
365
366/* GRF_GPIO2C_IOMUX */
367enum {
368 GPIO2C7_SHIFT = 14,
369 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
370 GPIO2C7_GPIO = 0,
371 GPIO2C7_GMAC_TXD3,
372
373 GPIO2C6_SHIFT = 12,
374 GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
375 GPIO2C6_GPIO = 0,
376 GPIO2C6_GMAC_TXD2,
377
378 GPIO2C5_SHIFT = 10,
379 GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
380 GPIO2C5_GPIO = 0,
381 GPIO2C5_I2C2_SCL,
382 GPIO2C5_GMAC_RXD2,
383
384 GPIO2C4_SHIFT = 8,
385 GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
386 GPIO2C4_GPIO = 0,
387 GPIO2C4_I2C2_SDA,
388 GPIO2C4_GMAC_RXD3,
389
390 GPIO2C3_SHIFT = 6,
391 GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
392 GPIO2C3_GPIO = 0,
393 GPIO2C3_GMAC_TXD0,
394
395 GPIO2C2_SHIFT = 4,
396 GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
397 GPIO2C2_GPIO = 0,
398 GPIO2C2_GMAC_TXD1,
399
400 GPIO2C1_SHIFT = 2,
401 GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
402 GPIO2C1_GPIO = 0,
403 GPIO2C1_GMAC_RXD0,
404
405 GPIO2C0_SHIFT = 0,
406 GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
407 GPIO2C0_GPIO = 0,
408 GPIO2C0_GMAC_RXD1,
409};
410
411/* GRF_GPIO2D_IOMUX */
412enum {
413 GPIO2D1_SHIFT = 2,
414 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
415 GPIO2D1_GPIO = 0,
416 GPIO2D1_GMAC_MDC,
417
418 GPIO2D0_SHIFT = 0,
419 GPIO2D0_MASK = 3,
420 GPIO2D0_GPIO = 0,
421 GPIO2D0_GMAC_COL,
422};
423
424/* GRF_GPIO3C_IOMUX */
425enum {
426 GPIO3C6_SHIFT = 12,
427 GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
428 GPIO3C6_GPIO = 0,
429 GPIO3C6_DRV_VBUS1,
430
431 GPIO3C5_SHIFT = 10,
432 GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
433 GPIO3C5_GPIO = 0,
434 GPIO3C5_PWM10,
435
436 GPIO3C1_SHIFT = 2,
437 GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
438 GPIO3C1_GPIO = 0,
439 GPIO3C1_DRV_VBUS,
440};
441
442/* GRF_GPIO3D_IOMUX */
443enum {
444 GPIO3D2_SHIFT = 4,
445 GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
446 GPIO3D2_GPIO = 0,
447 GPIO3D2_PWM3,
448};
449
450/* GRF_CON_IOMUX */
451enum {
452 CON_IOMUX_GMACSEL_SHIFT = 15,
453 CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT,
454 CON_IOMUX_GMACSEL_1 = 1,
455 CON_IOMUX_UART1SEL_SHIFT = 11,
456 CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
457 CON_IOMUX_UART2SEL_SHIFT = 8,
458 CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
459 CON_IOMUX_UART2SEL_2 = 0,
460 CON_IOMUX_UART2SEL_21,
461 CON_IOMUX_EMMCSEL_SHIFT = 7,
462 CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
463 CON_IOMUX_PWM3SEL_SHIFT = 3,
464 CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
465 CON_IOMUX_PWM2SEL_SHIFT = 2,
466 CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
467 CON_IOMUX_PWM1SEL_SHIFT = 1,
468 CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
469 CON_IOMUX_PWM0SEL_SHIFT = 0,
470 CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
471};
472
20ee0fd8
DW		 473/* GRF_GPIO2B_E */
474enum {
475 GRF_GPIO2B0_E_SHIFT = 0,
476 GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT,
477 GRF_GPIO2B1_E_SHIFT = 2,
478 GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT,
479 GRF_GPIO2B3_E_SHIFT = 6,
480 GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT,
481 GRF_GPIO2B4_E_SHIFT = 8,
482 GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT,
483 GRF_GPIO2B5_E_SHIFT = 10,
484 GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT,
485 GRF_GPIO2B6_E_SHIFT = 12,
486 GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT,
487};
488
489/* GRF_GPIO2C_E */
490enum {
491 GRF_GPIO2C0_E_SHIFT = 0,
492 GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT,
493 GRF_GPIO2C1_E_SHIFT = 2,
494 GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT,
495 GRF_GPIO2C2_E_SHIFT = 4,
496 GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT,
497 GRF_GPIO2C3_E_SHIFT = 6,
498 GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT,
499 GRF_GPIO2C4_E_SHIFT = 8,
500 GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT,
501 GRF_GPIO2C5_E_SHIFT = 10,
502 GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT,
503 GRF_GPIO2C6_E_SHIFT = 12,
504 GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT,
505 GRF_GPIO2C7_E_SHIFT = 14,
506 GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT,
507};
508
509/* GRF_GPIO2D_E */
510enum {
511 GRF_GPIO2D1_E_SHIFT = 2,
512 GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT,
513};
514
515/* GPIO Bias drive strength settings */
516enum GPIO_BIAS {
517 GPIO_BIAS_2MA = 0,
518 GPIO_BIAS_4MA,
519 GPIO_BIAS_8MA,
520 GPIO_BIAS_12MA,
521};
522
5cc9d31a
KY		 523struct rk322x_pinctrl_priv {
524 struct rk322x_grf *grf;
525};
526
527static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
528{
529 u32 mux_con = readl(&grf->con_iomux);
530
531 switch (pwm_id) {
532 case PERIPH_ID_PWM0:
533 if (mux_con & CON_IOMUX_PWM0SEL_MASK)
534 rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
535 GPIO3C5_PWM10 << GPIO3C5_SHIFT);
536 else
537 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
538 GPIO0D2_PWM0 << GPIO0D2_SHIFT);
539 break;
540 case PERIPH_ID_PWM1:
541 if (mux_con & CON_IOMUX_PWM1SEL_MASK)
542 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
543 GPIO0D6_PWM11 << GPIO0D6_SHIFT);
544 else
545 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
546 GPIO0D3_PWM1 << GPIO0D3_SHIFT);
547 break;
548 case PERIPH_ID_PWM2:
549 if (mux_con & CON_IOMUX_PWM2SEL_MASK)
550 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
551 GPIO1B4_PWM12 << GPIO1B4_SHIFT);
552 else
553 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
554 GPIO0D4_PWM2 << GPIO0D4_SHIFT);
555 break;
556 case PERIPH_ID_PWM3:
557 if (mux_con & CON_IOMUX_PWM3SEL_MASK)
558 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
559 GPIO1B3_PWM13 << GPIO1B3_SHIFT);
560 else
561 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
562 GPIO3D2_PWM3 << GPIO3D2_SHIFT);
563 break;
564 default:
565 debug("pwm id = %d iomux error!\n", pwm_id);
566 break;
567 }
568}
569
570static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
571{
572 switch (i2c_id) {
573 case PERIPH_ID_I2C0:
574 rk_clrsetreg(&grf->gpio0a_iomux,
575 GPIO0A1_MASK | GPIO0A0_MASK,
576 GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
577 GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
578
579 break;
580 case PERIPH_ID_I2C1:
581 rk_clrsetreg(&grf->gpio0a_iomux,
582 GPIO0A3_MASK | GPIO0A2_MASK,
583 GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
584 GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
585 break;
586 case PERIPH_ID_I2C2:
587 rk_clrsetreg(&grf->gpio2c_iomux,
588 GPIO2C5_MASK | GPIO2C4_MASK,
589 GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
590 GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
591 break;
592 case PERIPH_ID_I2C3:
593 rk_clrsetreg(&grf->gpio0a_iomux,
594 GPIO0A7_MASK | GPIO0A6_MASK,
595 GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
596 GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
597
598 break;
599 }
600}
601
602static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
603{
604 switch (cs) {
605 case 0:
606 rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
607 GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
608 break;
609 case 1:
610 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
611 GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
612 break;
613 }
614 rk_clrsetreg(&grf->gpio0b_iomux,
615 GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
616 GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
617 GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
618 GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
619}
620
621static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
622{
623 u32 mux_con = readl(&grf->con_iomux);
624
625 switch (uart_id) {
626 case PERIPH_ID_UART1:
627 if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
628 rk_clrsetreg(&grf->gpio1b_iomux,
629 GPIO1B1_MASK | GPIO1B2_MASK,
630 GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
631 GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
632 break;
633 case PERIPH_ID_UART2:
634 if (mux_con & CON_IOMUX_UART2SEL_MASK)
635 rk_clrsetreg(&grf->gpio1b_iomux,
636 GPIO1B1_MASK | GPIO1B2_MASK,
637 GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
638 GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
639 else
640 rk_clrsetreg(&grf->gpio1c_iomux,
641 GPIO1C3_MASK | GPIO1C2_MASK,
642 GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
643 GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
644 break;
645 }
646}
647
648static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
649{
650 switch (mmc_id) {
651 case PERIPH_ID_EMMC:
652 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
653 GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
654 GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
655 GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
656 GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
657 GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
658 GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
659 GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
660 GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
661 rk_clrsetreg(&grf->gpio2a_iomux,
662 GPIO2A5_MASK | GPIO2A7_MASK,
663 GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
664 GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
665 rk_clrsetreg(&grf->gpio1c_iomux,
666 GPIO1C6_MASK | GPIO1C7_MASK,
667 GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
668 GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
669 break;
670 case PERIPH_ID_SDCARD:
671 rk_clrsetreg(&grf->gpio1b_iomux,
672 GPIO1B6_MASK | GPIO1B7_MASK,
673 GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
957b4ee3 674 GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT);
5cc9d31a
KY		 675 rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
676 GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
677 GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
678 GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
679 GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
680 GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
681 GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
682 break;
683 }
684}
685
20ee0fd8
DW		 686#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
687static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
688{
689 switch (gmac_id) {
690 case PERIPH_ID_GMAC:
691 /* set rgmii pins mux */
692 rk_clrsetreg(&grf->gpio2b_iomux,
693 GPIO2B0_MASK |
694 GPIO2B1_MASK |
695 GPIO2B3_MASK |
696 GPIO2B4_MASK |
697 GPIO2B5_MASK |
698 GPIO2B6_MASK,
699 GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
700 GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
701 GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
702 GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
703 GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
704 GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
705
706 rk_clrsetreg(&grf->gpio2c_iomux,
707 GPIO2C0_MASK |
708 GPIO2C1_MASK |
709 GPIO2C2_MASK |
710 GPIO2C3_MASK |
711 GPIO2C4_MASK |
712 GPIO2C5_MASK |
713 GPIO2C6_MASK |
714 GPIO2C7_MASK,
715 GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
716 GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
717 GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
718 GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
719 GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
720 GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
721 GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
722 GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
723
724 rk_clrsetreg(&grf->gpio2d_iomux,
725 GPIO2D1_MASK,
726 GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
727
728 /*
729 * set rgmii tx pins to 12ma drive-strength,
730 * clean others with 2ma.
731 */
732 rk_clrsetreg(&grf->gpio2_e[1],
733 GRF_GPIO2B0_E_MASK |
734 GRF_GPIO2B1_E_MASK |
735 GRF_GPIO2B3_E_MASK |
736 GRF_GPIO2B4_E_MASK |
737 GRF_GPIO2B5_E_MASK |
738 GRF_GPIO2B6_E_MASK,
739 GPIO_BIAS_2MA << GRF_GPIO2B0_E_SHIFT |
740 GPIO_BIAS_12MA << GRF_GPIO2B1_E_SHIFT |
741 GPIO_BIAS_2MA << GRF_GPIO2B3_E_SHIFT |
742 GPIO_BIAS_2MA << GRF_GPIO2B4_E_SHIFT |
743 GPIO_BIAS_12MA << GRF_GPIO2B5_E_SHIFT |
744 GPIO_BIAS_2MA << GRF_GPIO2B6_E_SHIFT);
745
746 rk_clrsetreg(&grf->gpio2_e[2],
747 GRF_GPIO2C0_E_MASK |
748 GRF_GPIO2C1_E_MASK |
749 GRF_GPIO2C2_E_MASK |
750 GRF_GPIO2C3_E_MASK |
751 GRF_GPIO2C4_E_MASK |
752 GRF_GPIO2C5_E_MASK |
753 GRF_GPIO2C6_E_MASK |
754 GRF_GPIO2C7_E_MASK,
755 GPIO_BIAS_2MA << GRF_GPIO2C0_E_SHIFT |
756 GPIO_BIAS_2MA << GRF_GPIO2C1_E_SHIFT |
757 GPIO_BIAS_12MA << GRF_GPIO2C2_E_SHIFT |
758 GPIO_BIAS_12MA << GRF_GPIO2C3_E_SHIFT |
759 GPIO_BIAS_2MA << GRF_GPIO2C4_E_SHIFT |
760 GPIO_BIAS_2MA << GRF_GPIO2C5_E_SHIFT |
761 GPIO_BIAS_12MA << GRF_GPIO2C6_E_SHIFT |
762 GPIO_BIAS_12MA << GRF_GPIO2C7_E_SHIFT);
763
764 rk_clrsetreg(&grf->gpio2_e[3],
765 GRF_GPIO2D1_E_MASK,
766 GPIO_BIAS_2MA << GRF_GPIO2D1_E_SHIFT);
767 break;
768 default:
769 debug("gmac id = %d iomux error!\n", gmac_id);
770 break;
771 }
772}
773#endif
774
5cc9d31a
KY		 775static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
776{
777 struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
778
779 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
780 switch (func) {
781 case PERIPH_ID_PWM0:
782 case PERIPH_ID_PWM1:
783 case PERIPH_ID_PWM2:
784 case PERIPH_ID_PWM3:
785 pinctrl_rk322x_pwm_config(priv->grf, func);
786 break;
787 case PERIPH_ID_I2C0:
788 case PERIPH_ID_I2C1:
789 case PERIPH_ID_I2C2:
790 pinctrl_rk322x_i2c_config(priv->grf, func);
791 break;
792 case PERIPH_ID_SPI0:
793 pinctrl_rk322x_spi_config(priv->grf, flags);
794 break;
795 case PERIPH_ID_UART0:
796 case PERIPH_ID_UART1:
797 case PERIPH_ID_UART2:
798 pinctrl_rk322x_uart_config(priv->grf, func);
799 break;
800 case PERIPH_ID_SDMMC0:
801 case PERIPH_ID_SDMMC1:
802 pinctrl_rk322x_sdmmc_config(priv->grf, func);
803 break;
20ee0fd8
DW		 804#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
805 case PERIPH_ID_GMAC:
806 pinctrl_rk322x_gmac_config(priv->grf, func);
807 break;
808#endif
5cc9d31a
KY		 809 default:
810 return -EINVAL;
811 }
812
813 return 0;
814}
815
816static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
817 struct udevice *periph)
818{
819 u32 cell[3];
820 int ret;
821
822 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
823 "interrupts", cell, ARRAY_SIZE(cell));
824 if (ret < 0)
825 return -EINVAL;
826
827 switch (cell[1]) {
828 case 12:
829 return PERIPH_ID_SDCARD;
830 case 14:
831 return PERIPH_ID_EMMC;
832 case 36:
833 return PERIPH_ID_I2C0;
834 case 37:
835 return PERIPH_ID_I2C1;
836 case 38:
837 return PERIPH_ID_I2C2;
838 case 49:
839 return PERIPH_ID_SPI0;
840 case 50:
841 return PERIPH_ID_PWM0;
842 case 55:
843 return PERIPH_ID_UART0;
844 case 56:
845 return PERIPH_ID_UART1;
846 case 57:
847 return PERIPH_ID_UART2;
20ee0fd8
DW		 848#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
849 case 24:
850 return PERIPH_ID_GMAC;
851#endif
5cc9d31a
KY		 852 }
853 return -ENOENT;
854}
855
856static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
857 struct udevice *periph)
858{
859 int func;
860
861 func = rk322x_pinctrl_get_periph_id(dev, periph);
862 if (func < 0)
863 return func;
864 return rk322x_pinctrl_request(dev, func, 0);
865}
866
867static struct pinctrl_ops rk322x_pinctrl_ops = {
868 .set_state_simple = rk322x_pinctrl_set_state_simple,
869 .request = rk322x_pinctrl_request,
870 .get_periph_id = rk322x_pinctrl_get_periph_id,
871};
872
873static int rk322x_pinctrl_probe(struct udevice *dev)
874{
875 struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
876
877 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
878 debug("%s: grf=%p\n", __func__, priv->grf);
879 return 0;
880}
881
882static const struct udevice_id rk322x_pinctrl_ids[] = {
a634236b 883 { .compatible = "rockchip,rk3228-pinctrl" },
5cc9d31a
KY		 884 { }
885};
886
a634236b
KY		 887U_BOOT_DRIVER(pinctrl_rk3228) = {
888 .name = "pinctrl_rk3228",
5cc9d31a
KY		 889 .id = UCLASS_PINCTRL,
890 .of_match = rk322x_pinctrl_ids,
891 .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
892 .ops = &rk322x_pinctrl_ops,
893 .bind = dm_scan_fdt_dev,
894 .probe = rk322x_pinctrl_probe,
895};
"Das U-Boot" Source Tree