2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/grf_rk322x.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/periph.h>
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 /* GRF_GPIO0A_IOMUX */
23 GPIO0A7_MASK
= 3 << GPIO0A7_SHIFT
,
29 GPIO0A6_MASK
= 3 << GPIO0A6_SHIFT
,
35 GPIO0A3_MASK
= 3 << GPIO0A3_SHIFT
,
41 GPIO0A2_MASK
= 3 << GPIO0A2_SHIFT
,
46 GPIO0A1_MASK
= 3 << GPIO0A1_SHIFT
,
51 GPIO0A0_MASK
= 3 << GPIO0A0_SHIFT
,
56 /* GRF_GPIO0B_IOMUX */
59 GPIO0B7_MASK
= 3 << GPIO0B7_SHIFT
,
64 GPIO0B6_MASK
= 3 << GPIO0B6_SHIFT
,
70 GPIO0B5_MASK
= 3 << GPIO0B5_SHIFT
,
76 GPIO0B3_MASK
= 3 << GPIO0B3_SHIFT
,
82 GPIO0B1_MASK
= 3 << GPIO0B1_SHIFT
,
93 /* GRF_GPIO0C_IOMUX */
96 GPIO0C4_MASK
= 3 << GPIO0C4_SHIFT
,
101 GPIO0C1_MASK
= 3 << GPIO0C1_SHIFT
,
107 /* GRF_GPIO0D_IOMUX */
110 GPIO0D6_MASK
= 3 << GPIO0D6_SHIFT
,
116 GPIO0D4_MASK
= 3 << GPIO0D4_SHIFT
,
121 GPIO0D3_MASK
= 3 << GPIO0D3_SHIFT
,
126 GPIO0D2_MASK
= 3 << GPIO0D2_SHIFT
,
131 /* GRF_GPIO1A_IOMUX */
139 /* GRF_GPIO1B_IOMUX */
142 GPIO1B7_MASK
= 3 << GPIO1B7_SHIFT
,
147 GPIO1B6_MASK
= 3 << GPIO1B6_SHIFT
,
152 GPIO1B4_MASK
= 3 << GPIO1B4_SHIFT
,
158 GPIO1B3_MASK
= 3 << GPIO1B3_SHIFT
,
164 GPIO1B2_MASK
= 3 << GPIO1B2_SHIFT
,
170 GPIO1B1_MASK
= 3 << GPIO1B1_SHIFT
,
176 /* GRF_GPIO1C_IOMUX */
179 GPIO1C7_MASK
= 3 << GPIO1C7_SHIFT
,
182 GPIO1C7_EMMC_RSTNOUT
,
185 GPIO1C6_MASK
= 3 << GPIO1C6_SHIFT
,
191 GPIO1C5_MASK
= 3 << GPIO1C5_SHIFT
,
197 GPIO1C4_MASK
= 3 << GPIO1C4_SHIFT
,
203 GPIO1C3_MASK
= 3 << GPIO1C3_SHIFT
,
209 GPIO1C2_MASK
= 3 << GPIO1C2_SHIFT
,
215 GPIO1C1_MASK
= 3 << GPIO1C1_SHIFT
,
220 GPIO1C0_MASK
= 3 << GPIO1C0_SHIFT
,
222 GPIO1C0_SDMMC_CLKOUT
,
225 /* GRF_GPIO1D_IOMUX */
228 GPIO1D7_MASK
= 3 << GPIO1D7_SHIFT
,
234 GPIO1D6_MASK
= 3 << GPIO1D6_SHIFT
,
240 GPIO1D5_MASK
= 3 << GPIO1D5_SHIFT
,
246 GPIO1D4_MASK
= 3 << GPIO1D4_SHIFT
,
252 GPIO1D3_MASK
= 3 << GPIO1D3_SHIFT
,
258 GPIO1D2_MASK
= 3 << GPIO1D2_SHIFT
,
264 GPIO1D1_MASK
= 3 << GPIO1D1_SHIFT
,
270 GPIO1D0_MASK
= 3 << GPIO1D0_SHIFT
,
276 /* GRF_GPIO2A_IOMUX */
279 GPIO2A7_MASK
= 3 << GPIO2A7_SHIFT
,
285 GPIO2A5_MASK
= 3 << GPIO2A5_SHIFT
,
291 GPIO2A4_MASK
= 3 << GPIO2A4_SHIFT
,
297 GPIO2A3_MASK
= 3 << GPIO2A3_SHIFT
,
303 GPIO2A2_MASK
= 3 << GPIO2A2_SHIFT
,
309 GPIO2A1_MASK
= 3 << GPIO2A1_SHIFT
,
315 GPIO2A0_MASK
= 3 << GPIO2A0_SHIFT
,
321 /* GRF_GPIO2B_IOMUX */
324 GPIO2B7_MASK
= 3 << GPIO2B7_SHIFT
,
329 GPIO2B6_MASK
= 3 << GPIO2B6_SHIFT
,
335 GPIO2B5_MASK
= 3 << GPIO2B5_SHIFT
,
340 GPIO2B4_MASK
= 3 << GPIO2B4_SHIFT
,
345 GPIO2B3_MASK
= 3 << GPIO2B3_SHIFT
,
350 GPIO2B2_MASK
= 3 << GPIO2B2_SHIFT
,
355 GPIO2B1_MASK
= 3 << GPIO2B1_SHIFT
,
360 GPIO2B0_MASK
= 3 << GPIO2B0_SHIFT
,
363 GPIO2B0_MAC_SPEED_IOUT
,
366 /* GRF_GPIO2C_IOMUX */
369 GPIO2C7_MASK
= 3 << GPIO2C7_SHIFT
,
374 GPIO2C6_MASK
= 3 << GPIO2C6_SHIFT
,
379 GPIO2C5_MASK
= 3 << GPIO2C5_SHIFT
,
385 GPIO2C4_MASK
= 3 << GPIO2C4_SHIFT
,
391 GPIO2C3_MASK
= 3 << GPIO2C3_SHIFT
,
396 GPIO2C2_MASK
= 3 << GPIO2C2_SHIFT
,
401 GPIO2C1_MASK
= 3 << GPIO2C1_SHIFT
,
406 GPIO2C0_MASK
= 3 << GPIO2C0_SHIFT
,
411 /* GRF_GPIO2D_IOMUX */
414 GPIO2D1_MASK
= 3 << GPIO2D1_SHIFT
,
424 /* GRF_GPIO3C_IOMUX */
427 GPIO3C6_MASK
= 3 << GPIO3C6_SHIFT
,
432 GPIO3C5_MASK
= 3 << GPIO3C5_SHIFT
,
437 GPIO3C1_MASK
= 3 << GPIO3C1_SHIFT
,
442 /* GRF_GPIO3D_IOMUX */
445 GPIO3D2_MASK
= 3 << GPIO3D2_SHIFT
,
452 CON_IOMUX_GMACSEL_SHIFT
= 15,
453 CON_IOMUX_GMACSEL_MASK
= 1 << CON_IOMUX_GMACSEL_SHIFT
,
454 CON_IOMUX_GMACSEL_1
= 1,
455 CON_IOMUX_UART1SEL_SHIFT
= 11,
456 CON_IOMUX_UART1SEL_MASK
= 1 << CON_IOMUX_UART1SEL_SHIFT
,
457 CON_IOMUX_UART2SEL_SHIFT
= 8,
458 CON_IOMUX_UART2SEL_MASK
= 1 << CON_IOMUX_UART2SEL_SHIFT
,
459 CON_IOMUX_UART2SEL_2
= 0,
460 CON_IOMUX_UART2SEL_21
,
461 CON_IOMUX_EMMCSEL_SHIFT
= 7,
462 CON_IOMUX_EMMCSEL_MASK
= 1 << CON_IOMUX_EMMCSEL_SHIFT
,
463 CON_IOMUX_PWM3SEL_SHIFT
= 3,
464 CON_IOMUX_PWM3SEL_MASK
= 1 << CON_IOMUX_PWM3SEL_SHIFT
,
465 CON_IOMUX_PWM2SEL_SHIFT
= 2,
466 CON_IOMUX_PWM2SEL_MASK
= 1 << CON_IOMUX_PWM2SEL_SHIFT
,
467 CON_IOMUX_PWM1SEL_SHIFT
= 1,
468 CON_IOMUX_PWM1SEL_MASK
= 1 << CON_IOMUX_PWM1SEL_SHIFT
,
469 CON_IOMUX_PWM0SEL_SHIFT
= 0,
470 CON_IOMUX_PWM0SEL_MASK
= 1 << CON_IOMUX_PWM0SEL_SHIFT
,
475 GRF_GPIO2B0_E_SHIFT
= 0,
476 GRF_GPIO2B0_E_MASK
= 3 << GRF_GPIO2B0_E_SHIFT
,
477 GRF_GPIO2B1_E_SHIFT
= 2,
478 GRF_GPIO2B1_E_MASK
= 3 << GRF_GPIO2B1_E_SHIFT
,
479 GRF_GPIO2B3_E_SHIFT
= 6,
480 GRF_GPIO2B3_E_MASK
= 3 << GRF_GPIO2B3_E_SHIFT
,
481 GRF_GPIO2B4_E_SHIFT
= 8,
482 GRF_GPIO2B4_E_MASK
= 3 << GRF_GPIO2B4_E_SHIFT
,
483 GRF_GPIO2B5_E_SHIFT
= 10,
484 GRF_GPIO2B5_E_MASK
= 3 << GRF_GPIO2B5_E_SHIFT
,
485 GRF_GPIO2B6_E_SHIFT
= 12,
486 GRF_GPIO2B6_E_MASK
= 3 << GRF_GPIO2B6_E_SHIFT
,
491 GRF_GPIO2C0_E_SHIFT
= 0,
492 GRF_GPIO2C0_E_MASK
= 3 << GRF_GPIO2C0_E_SHIFT
,
493 GRF_GPIO2C1_E_SHIFT
= 2,
494 GRF_GPIO2C1_E_MASK
= 3 << GRF_GPIO2C1_E_SHIFT
,
495 GRF_GPIO2C2_E_SHIFT
= 4,
496 GRF_GPIO2C2_E_MASK
= 3 << GRF_GPIO2C2_E_SHIFT
,
497 GRF_GPIO2C3_E_SHIFT
= 6,
498 GRF_GPIO2C3_E_MASK
= 3 << GRF_GPIO2C3_E_SHIFT
,
499 GRF_GPIO2C4_E_SHIFT
= 8,
500 GRF_GPIO2C4_E_MASK
= 3 << GRF_GPIO2C4_E_SHIFT
,
501 GRF_GPIO2C5_E_SHIFT
= 10,
502 GRF_GPIO2C5_E_MASK
= 3 << GRF_GPIO2C5_E_SHIFT
,
503 GRF_GPIO2C6_E_SHIFT
= 12,
504 GRF_GPIO2C6_E_MASK
= 3 << GRF_GPIO2C6_E_SHIFT
,
505 GRF_GPIO2C7_E_SHIFT
= 14,
506 GRF_GPIO2C7_E_MASK
= 3 << GRF_GPIO2C7_E_SHIFT
,
511 GRF_GPIO2D1_E_SHIFT
= 2,
512 GRF_GPIO2D1_E_MASK
= 3 << GRF_GPIO2D1_E_SHIFT
,
515 /* GPIO Bias drive strength settings */
523 struct rk322x_pinctrl_priv
{
524 struct rk322x_grf
*grf
;
527 static void pinctrl_rk322x_pwm_config(struct rk322x_grf
*grf
, int pwm_id
)
529 u32 mux_con
= readl(&grf
->con_iomux
);
533 if (mux_con
& CON_IOMUX_PWM0SEL_MASK
)
534 rk_clrsetreg(&grf
->gpio3c_iomux
, GPIO3C5_MASK
,
535 GPIO3C5_PWM10
<< GPIO3C5_SHIFT
);
537 rk_clrsetreg(&grf
->gpio0d_iomux
, GPIO0D2_MASK
,
538 GPIO0D2_PWM0
<< GPIO0D2_SHIFT
);
541 if (mux_con
& CON_IOMUX_PWM1SEL_MASK
)
542 rk_clrsetreg(&grf
->gpio0d_iomux
, GPIO0D6_MASK
,
543 GPIO0D6_PWM11
<< GPIO0D6_SHIFT
);
545 rk_clrsetreg(&grf
->gpio0d_iomux
, GPIO0D3_MASK
,
546 GPIO0D3_PWM1
<< GPIO0D3_SHIFT
);
549 if (mux_con
& CON_IOMUX_PWM2SEL_MASK
)
550 rk_clrsetreg(&grf
->gpio1b_iomux
, GPIO1B4_MASK
,
551 GPIO1B4_PWM12
<< GPIO1B4_SHIFT
);
553 rk_clrsetreg(&grf
->gpio0d_iomux
, GPIO0D4_MASK
,
554 GPIO0D4_PWM2
<< GPIO0D4_SHIFT
);
557 if (mux_con
& CON_IOMUX_PWM3SEL_MASK
)
558 rk_clrsetreg(&grf
->gpio1b_iomux
, GPIO1B3_MASK
,
559 GPIO1B3_PWM13
<< GPIO1B3_SHIFT
);
561 rk_clrsetreg(&grf
->gpio3d_iomux
, GPIO3D2_MASK
,
562 GPIO3D2_PWM3
<< GPIO3D2_SHIFT
);
565 debug("pwm id = %d iomux error!\n", pwm_id
);
570 static void pinctrl_rk322x_i2c_config(struct rk322x_grf
*grf
, int i2c_id
)
574 rk_clrsetreg(&grf
->gpio0a_iomux
,
575 GPIO0A1_MASK
| GPIO0A0_MASK
,
576 GPIO0A1_I2C0_SDA
<< GPIO0A1_SHIFT
|
577 GPIO0A0_I2C0_SCL
<< GPIO0A0_SHIFT
);
581 rk_clrsetreg(&grf
->gpio0a_iomux
,
582 GPIO0A3_MASK
| GPIO0A2_MASK
,
583 GPIO0A3_I2C1_SDA
<< GPIO0A3_SHIFT
|
584 GPIO0A2_I2C1_SCL
<< GPIO0A2_SHIFT
);
587 rk_clrsetreg(&grf
->gpio2c_iomux
,
588 GPIO2C5_MASK
| GPIO2C4_MASK
,
589 GPIO2C5_I2C2_SCL
<< GPIO2C5_SHIFT
|
590 GPIO2C4_I2C2_SDA
<< GPIO2C4_SHIFT
);
593 rk_clrsetreg(&grf
->gpio0a_iomux
,
594 GPIO0A7_MASK
| GPIO0A6_MASK
,
595 GPIO0A7_I2C3_SDA
<< GPIO0A7_SHIFT
|
596 GPIO0A6_I2C3_SCL
<< GPIO0A6_SHIFT
);
602 static void pinctrl_rk322x_spi_config(struct rk322x_grf
*grf
, int cs
)
606 rk_clrsetreg(&grf
->gpio0b_iomux
, GPIO0B6_MASK
,
607 GPIO0B6_SPI_CSN0
<< GPIO0B6_SHIFT
);
610 rk_clrsetreg(&grf
->gpio1b_iomux
, GPIO1B4_MASK
,
611 GPIO1B4_SPI_CSN1
<< GPIO1B4_SHIFT
);
614 rk_clrsetreg(&grf
->gpio0b_iomux
,
615 GPIO0B1_MASK
| GPIO0B3_MASK
| GPIO0B5_MASK
,
616 GPIO0B5_SPI_RXD
<< GPIO0B5_SHIFT
|
617 GPIO0B3_SPI_TXD
<< GPIO0B3_SHIFT
|
618 GPIO0B1_SPI_CLK
<< GPIO0B1_SHIFT
);
621 static void pinctrl_rk322x_uart_config(struct rk322x_grf
*grf
, int uart_id
)
623 u32 mux_con
= readl(&grf
->con_iomux
);
626 case PERIPH_ID_UART1
:
627 if (!(mux_con
& CON_IOMUX_UART1SEL_MASK
))
628 rk_clrsetreg(&grf
->gpio1b_iomux
,
629 GPIO1B1_MASK
| GPIO1B2_MASK
,
630 GPIO1B1_UART1_SOUT
<< GPIO1B1_SHIFT
|
631 GPIO1B2_UART1_SIN
<< GPIO1B2_SHIFT
);
633 case PERIPH_ID_UART2
:
634 if (mux_con
& CON_IOMUX_UART2SEL_MASK
)
635 rk_clrsetreg(&grf
->gpio1b_iomux
,
636 GPIO1B1_MASK
| GPIO1B2_MASK
,
637 GPIO1B1_UART21_SOUT
<< GPIO1B1_SHIFT
|
638 GPIO1B2_UART21_SIN
<< GPIO1B2_SHIFT
);
640 rk_clrsetreg(&grf
->gpio1c_iomux
,
641 GPIO1C3_MASK
| GPIO1C2_MASK
,
642 GPIO1C3_UART2_SIN
<< GPIO1C3_SHIFT
|
643 GPIO1C2_UART2_SOUT
<< GPIO1C2_SHIFT
);
648 static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf
*grf
, int mmc_id
)
652 rk_clrsetreg(&grf
->gpio1d_iomux
, 0xffff,
653 GPIO1D7_EMMC_D7
<< GPIO1D7_SHIFT
|
654 GPIO1D6_EMMC_D6
<< GPIO1D6_SHIFT
|
655 GPIO1D5_EMMC_D5
<< GPIO1D5_SHIFT
|
656 GPIO1D4_EMMC_D4
<< GPIO1D4_SHIFT
|
657 GPIO1D3_EMMC_D3
<< GPIO1D3_SHIFT
|
658 GPIO1D2_EMMC_D2
<< GPIO1D2_SHIFT
|
659 GPIO1D1_EMMC_D1
<< GPIO1D1_SHIFT
|
660 GPIO1D0_EMMC_D0
<< GPIO1D0_SHIFT
);
661 rk_clrsetreg(&grf
->gpio2a_iomux
,
662 GPIO2A5_MASK
| GPIO2A7_MASK
,
663 GPIO2A5_EMMC_PWREN
<< GPIO2A5_SHIFT
|
664 GPIO2A7_EMMC_CLKOUT
<< GPIO2A7_SHIFT
);
665 rk_clrsetreg(&grf
->gpio1c_iomux
,
666 GPIO1C6_MASK
| GPIO1C7_MASK
,
667 GPIO1C6_EMMC_CMD
<< GPIO1C6_SHIFT
|
668 GPIO1C7_EMMC_RSTNOUT
<< GPIO1C6_SHIFT
);
670 case PERIPH_ID_SDCARD
:
671 rk_clrsetreg(&grf
->gpio1b_iomux
,
672 GPIO1B6_MASK
| GPIO1B7_MASK
,
673 GPIO1B6_SDMMC_PWREN
<< GPIO1B6_SHIFT
|
674 GPIO1B7_SDMMC_CMD
<< GPIO1B7_SHIFT
);
675 rk_clrsetreg(&grf
->gpio1c_iomux
, 0xfff,
676 GPIO1C5_SDMMC_D3
<< GPIO1C5_SHIFT
|
677 GPIO1C4_SDMMC_D2
<< GPIO1C4_SHIFT
|
678 GPIO1C3_SDMMC_D1
<< GPIO1C3_SHIFT
|
679 GPIO1C2_SDMMC_D0
<< GPIO1C2_SHIFT
|
680 GPIO1C1_SDMMC_DETN
<< GPIO1C1_SHIFT
|
681 GPIO1C0_SDMMC_CLKOUT
<< GPIO1C0_SHIFT
);
686 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
687 static void pinctrl_rk322x_gmac_config(struct rk322x_grf
*grf
, int gmac_id
)
691 /* set rgmii pins mux */
692 rk_clrsetreg(&grf
->gpio2b_iomux
,
699 GPIO2B0_GMAC_RXDV
<< GPIO2B0_SHIFT
|
700 GPIO2B1_GMAC_TXCLK
<< GPIO2B1_SHIFT
|
701 GPIO2B3_GMAC_RXCLK
<< GPIO2B3_SHIFT
|
702 GPIO2B4_GMAC_MDIO
<< GPIO2B4_SHIFT
|
703 GPIO2B5_GMAC_TXEN
<< GPIO2B5_SHIFT
|
704 GPIO2B6_GMAC_CLK
<< GPIO2B6_SHIFT
);
706 rk_clrsetreg(&grf
->gpio2c_iomux
,
715 GPIO2C0_GMAC_RXD1
<< GPIO2C0_SHIFT
|
716 GPIO2C1_GMAC_RXD0
<< GPIO2C1_SHIFT
|
717 GPIO2C2_GMAC_TXD1
<< GPIO2C2_SHIFT
|
718 GPIO2C3_GMAC_TXD0
<< GPIO2C3_SHIFT
|
719 GPIO2C4_GMAC_RXD3
<< GPIO2C4_SHIFT
|
720 GPIO2C5_GMAC_RXD2
<< GPIO2C5_SHIFT
|
721 GPIO2C6_GMAC_TXD2
<< GPIO2C6_SHIFT
|
722 GPIO2C7_GMAC_TXD3
<< GPIO2C7_SHIFT
);
724 rk_clrsetreg(&grf
->gpio2d_iomux
,
726 GPIO2D1_GMAC_MDC
<< GPIO2D1_SHIFT
);
729 * set rgmii tx pins to 12ma drive-strength,
730 * clean others with 2ma.
732 rk_clrsetreg(&grf
->gpio2_e
[1],
739 GPIO_BIAS_2MA
<< GRF_GPIO2B0_E_SHIFT
|
740 GPIO_BIAS_12MA
<< GRF_GPIO2B1_E_SHIFT
|
741 GPIO_BIAS_2MA
<< GRF_GPIO2B3_E_SHIFT
|
742 GPIO_BIAS_2MA
<< GRF_GPIO2B4_E_SHIFT
|
743 GPIO_BIAS_12MA
<< GRF_GPIO2B5_E_SHIFT
|
744 GPIO_BIAS_2MA
<< GRF_GPIO2B6_E_SHIFT
);
746 rk_clrsetreg(&grf
->gpio2_e
[2],
755 GPIO_BIAS_2MA
<< GRF_GPIO2C0_E_SHIFT
|
756 GPIO_BIAS_2MA
<< GRF_GPIO2C1_E_SHIFT
|
757 GPIO_BIAS_12MA
<< GRF_GPIO2C2_E_SHIFT
|
758 GPIO_BIAS_12MA
<< GRF_GPIO2C3_E_SHIFT
|
759 GPIO_BIAS_2MA
<< GRF_GPIO2C4_E_SHIFT
|
760 GPIO_BIAS_2MA
<< GRF_GPIO2C5_E_SHIFT
|
761 GPIO_BIAS_12MA
<< GRF_GPIO2C6_E_SHIFT
|
762 GPIO_BIAS_12MA
<< GRF_GPIO2C7_E_SHIFT
);
764 rk_clrsetreg(&grf
->gpio2_e
[3],
766 GPIO_BIAS_2MA
<< GRF_GPIO2D1_E_SHIFT
);
769 debug("gmac id = %d iomux error!\n", gmac_id
);
775 static int rk322x_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
777 struct rk322x_pinctrl_priv
*priv
= dev_get_priv(dev
);
779 debug("%s: func=%x, flags=%x\n", __func__
, func
, flags
);
785 pinctrl_rk322x_pwm_config(priv
->grf
, func
);
790 pinctrl_rk322x_i2c_config(priv
->grf
, func
);
793 pinctrl_rk322x_spi_config(priv
->grf
, flags
);
795 case PERIPH_ID_UART0
:
796 case PERIPH_ID_UART1
:
797 case PERIPH_ID_UART2
:
798 pinctrl_rk322x_uart_config(priv
->grf
, func
);
800 case PERIPH_ID_SDMMC0
:
801 case PERIPH_ID_SDMMC1
:
802 pinctrl_rk322x_sdmmc_config(priv
->grf
, func
);
804 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
806 pinctrl_rk322x_gmac_config(priv
->grf
, func
);
816 static int rk322x_pinctrl_get_periph_id(struct udevice
*dev
,
817 struct udevice
*periph
)
822 ret
= fdtdec_get_int_array(gd
->fdt_blob
, dev_of_offset(periph
),
823 "interrupts", cell
, ARRAY_SIZE(cell
));
829 return PERIPH_ID_SDCARD
;
831 return PERIPH_ID_EMMC
;
833 return PERIPH_ID_I2C0
;
835 return PERIPH_ID_I2C1
;
837 return PERIPH_ID_I2C2
;
839 return PERIPH_ID_SPI0
;
841 return PERIPH_ID_PWM0
;
843 return PERIPH_ID_UART0
;
845 return PERIPH_ID_UART1
;
847 return PERIPH_ID_UART2
;
848 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
850 return PERIPH_ID_GMAC
;
856 static int rk322x_pinctrl_set_state_simple(struct udevice
*dev
,
857 struct udevice
*periph
)
861 func
= rk322x_pinctrl_get_periph_id(dev
, periph
);
864 return rk322x_pinctrl_request(dev
, func
, 0);
867 static struct pinctrl_ops rk322x_pinctrl_ops
= {
868 .set_state_simple
= rk322x_pinctrl_set_state_simple
,
869 .request
= rk322x_pinctrl_request
,
870 .get_periph_id
= rk322x_pinctrl_get_periph_id
,
873 static int rk322x_pinctrl_probe(struct udevice
*dev
)
875 struct rk322x_pinctrl_priv
*priv
= dev_get_priv(dev
);
877 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
878 debug("%s: grf=%p\n", __func__
, priv
->grf
);
882 static const struct udevice_id rk322x_pinctrl_ids
[] = {
883 { .compatible
= "rockchip,rk3228-pinctrl" },
887 U_BOOT_DRIVER(pinctrl_rk3228
) = {
888 .name
= "pinctrl_rk3228",
889 .id
= UCLASS_PINCTRL
,
890 .of_match
= rk322x_pinctrl_ids
,
891 .priv_auto_alloc_size
= sizeof(struct rk322x_pinctrl_priv
),
892 .ops
= &rk322x_pinctrl_ops
,
893 .bind
= dm_scan_fdt_dev
,
894 .probe
= rk322x_pinctrl_probe
,