[people/ms/u-boot.git] / drivers / serial / serial_lpuart.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <fsl_lpuart.h>
#include <watchdog.h>
#include <asm/io.h>
#include <serial.h>
#include <linux/compiler.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>

#define US1_TDRE	(1 << 7)
#define US1_RDRF	(1 << 5)
#define US1_OR		(1 << 3)
#define UC2_TE		(1 << 3)
#define UC2_RE		(1 << 2)
#define CFIFO_TXFLUSH	(1 << 7)
#define CFIFO_RXFLUSH	(1 << 6)
#define SFIFO_RXOF	(1 << 2)
#define SFIFO_RXUF	(1 << 0)

#define STAT_LBKDIF	(1 << 31)
#define STAT_RXEDGIF	(1 << 30)
#define STAT_TDRE	(1 << 23)
#define STAT_RDRF	(1 << 21)
#define STAT_IDLE	(1 << 20)
#define STAT_OR		(1 << 19)
#define STAT_NF		(1 << 18)
#define STAT_FE		(1 << 17)
#define STAT_PF		(1 << 16)
#define STAT_MA1F	(1 << 15)
#define STAT_MA2F	(1 << 14)
#define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
			 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)

#define CTRL_TE		(1 << 19)
#define CTRL_RE		(1 << 18)

#define FIFO_TXFE		0x80
#define FIFO_RXFE		0x40

#define WATER_TXWATER_OFF	1
#define WATER_RXWATER_OFF	16

DECLARE_GLOBAL_DATA_PTR;

#define LPUART_FLAG_REGMAP_32BIT_REG	BIT(0)
#define LPUART_FLAG_REGMAP_ENDIAN_BIG	BIT(1)

enum lpuart_devtype {
	DEV_VF610 = 1,
	DEV_LS1021A,
	DEV_MX7ULP
};

struct lpuart_serial_platdata {
	void *reg;
	enum lpuart_devtype devtype;
	ulong flags;
};

static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
{
	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
		if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
			*(u32 *)val = in_be32(addr);
		else
			*(u32 *)val = in_le32(addr);
	}
}

static void lpuart_write32(u32 flags, u32 *addr, u32 val)
{
	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
		if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
			out_be32(addr, val);
		else
			out_le32(addr, val);
	}
}


#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	0
#endif

u32 __weak get_lpuart_clk(void)
{
	return CONFIG_SYS_CLK_FREQ;
}

static bool is_lpuart32(struct udevice *dev)
{
	struct lpuart_serial_platdata *plat = dev->platdata;

	return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
}

static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat,
				  int baudrate)
{
	struct lpuart_fsl *base = plat->reg;
	u32 clk = get_lpuart_clk();
	u16 sbr;

	sbr = (u16)(clk / (16 * baudrate));

	/* place adjustment later - n/32 BRFA */
	__raw_writeb(sbr >> 8, &base->ubdh);
	__raw_writeb(sbr & 0xff, &base->ubdl);
}

static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
{
	struct lpuart_fsl *base = plat->reg;
	while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
		WATCHDOG_RESET();

	barrier();

	return __raw_readb(&base->ud);
}

static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
				const char c)
{
	struct lpuart_fsl *base = plat->reg;

	while (!(__raw_readb(&base->us1) & US1_TDRE))
		WATCHDOG_RESET();

	__raw_writeb(c, &base->ud);
}

/* Test whether a character is in the RX buffer */
static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
{
	struct lpuart_fsl *base = plat->reg;

	if (__raw_readb(&base->urcfifo) == 0)
		return 0;

	return 1;
}

/*
 * Initialise the serial port with the given baudrate. The settings
 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 */
static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)
{
	struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
	u8 ctrl;

	ctrl = __raw_readb(&base->uc2);
	ctrl &= ~UC2_RE;
	ctrl &= ~UC2_TE;
	__raw_writeb(ctrl, &base->uc2);

	__raw_writeb(0, &base->umodem);
	__raw_writeb(0, &base->uc1);

	/* Disable FIFO and flush buffer */
	__raw_writeb(0x0, &base->upfifo);
	__raw_writeb(0x0, &base->utwfifo);
	__raw_writeb(0x1, &base->urwfifo);
	__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);

	/* provide data bits, parity, stop bit, etc */
	_lpuart_serial_setbrg(plat, gd->baudrate);

	__raw_writeb(UC2_RE | UC2_TE, &base->uc2);

	return 0;
}

static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat,
					 int baudrate)
{
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
	u32 clk = get_lpuart_clk();

	baud_diff = baudrate;
	osr = 0;
	sbr = 0;

	for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
		tmp_sbr = (clk / (baudrate * tmp_osr));

		if (tmp_sbr == 0)
			tmp_sbr = 1;

		/*calculate difference in actual buad w/ current values */
		tmp_diff = (clk / (tmp_osr * tmp_sbr));
		tmp_diff = tmp_diff - baudrate;

		/* select best values between sbr and sbr+1 */
		if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
			tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
			tmp_sbr++;
		}

		if (tmp_diff <= baud_diff) {
			baud_diff = tmp_diff;
			osr = tmp_osr;
			sbr = tmp_sbr;
		}
	}

	/*
	 * TODO: handle buadrate outside acceptable rate
	 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
	 * {
	 *   Unacceptable baud rate difference of more than 3%
	 *   return kStatus_LPUART_BaudrateNotSupport;
	 * }
	 */
	tmp = in_le32(&base->baud);

	if ((osr > 3) && (osr < 8))
		tmp |= LPUART_BAUD_BOTHEDGE_MASK;

	tmp &= ~LPUART_BAUD_OSR_MASK;
	tmp |= LPUART_BAUD_OSR(osr-1);

	tmp &= ~LPUART_BAUD_SBR_MASK;
	tmp |= LPUART_BAUD_SBR(sbr);

	/* explicitly disable 10 bit mode & set 1 stop bit */
	tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);

	out_le32(&base->baud, tmp);
}

static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat,
				    int baudrate)
{
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 clk = get_lpuart_clk();
	u32 sbr;

	sbr = (clk / (16 * baudrate));

	/* place adjustment later - n/32 BRFA */
	lpuart_write32(plat->flags, &base->baud, sbr);
}

static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
{
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 stat, val;

	lpuart_read32(plat->flags, &base->stat, &stat);
	while ((stat & STAT_RDRF) == 0) {
		lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
		WATCHDOG_RESET();
		lpuart_read32(plat->flags, &base->stat, &stat);
	}

	lpuart_read32(plat->flags, &base->data, &val);

	lpuart_read32(plat->flags, &base->stat, &stat);
	if (stat & STAT_OR)
		lpuart_write32(plat->flags, &base->stat, STAT_OR);

	return val & 0x3ff;
}

static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
				  const char c)
{
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 stat;

	if (c == '\n')
		serial_putc('\r');

	while (true) {
		lpuart_read32(plat->flags, &base->stat, &stat);

		if ((stat & STAT_TDRE))
			break;

		WATCHDOG_RESET();
	}

	lpuart_write32(plat->flags, &base->data, c);
}

/* Test whether a character is in the RX buffer */
static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
{
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 water;

	lpuart_read32(plat->flags, &base->water, &water);

	if ((water >> 24) == 0)
		return 0;

	return 1;
}

/*
 * Initialise the serial port with the given baudrate. The settings
 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 */
static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
{
	struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
	u32 ctrl;

	lpuart_read32(plat->flags, &base->ctrl, &ctrl);
	ctrl &= ~CTRL_RE;
	ctrl &= ~CTRL_TE;
	lpuart_write32(plat->flags, &base->ctrl, ctrl);

	lpuart_write32(plat->flags, &base->modir, 0);
	lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE));

	lpuart_write32(plat->flags, &base->match, 0);

	if (plat->devtype == DEV_MX7ULP) {
		_lpuart32_serial_setbrg_7ulp(plat, gd->baudrate);
	} else {
		/* provide data bits, parity, stop bit, etc */
		_lpuart32_serial_setbrg(plat, gd->baudrate);
	}

	lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);

	return 0;
}

static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct lpuart_serial_platdata *plat = dev->platdata;

	if (is_lpuart32(dev)) {
		if (plat->devtype == DEV_MX7ULP)
			_lpuart32_serial_setbrg_7ulp(plat, baudrate);
		else
			_lpuart32_serial_setbrg(plat, baudrate);
	} else {
		_lpuart_serial_setbrg(plat, baudrate);
	}

	return 0;
}

static int lpuart_serial_getc(struct udevice *dev)
{
	struct lpuart_serial_platdata *plat = dev->platdata;

	if (is_lpuart32(dev))
		return _lpuart32_serial_getc(plat);

	return _lpuart_serial_getc(plat);
}

static int lpuart_serial_putc(struct udevice *dev, const char c)
{
	struct lpuart_serial_platdata *plat = dev->platdata;

	if (is_lpuart32(dev))
		_lpuart32_serial_putc(plat, c);
	else
		_lpuart_serial_putc(plat, c);

	return 0;
}

static int lpuart_serial_pending(struct udevice *dev, bool input)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;
	struct lpuart_fsl_reg32 *reg32 = plat->reg;
	u32 stat;

	if (is_lpuart32(dev)) {
		if (input) {
			return _lpuart32_serial_tstc(plat);
		} else {
			lpuart_read32(plat->flags, &reg32->stat, &stat);
			return stat & STAT_TDRE ? 0 : 1;
		}
	}

	if (input)
		return _lpuart_serial_tstc(plat);
	else
		return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
}

static int lpuart_serial_probe(struct udevice *dev)
{
	struct lpuart_serial_platdata *plat = dev->platdata;

	if (is_lpuart32(dev))
		return _lpuart32_serial_init(plat);
	else
		return _lpuart_serial_init(plat);
}

static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(dev);
	fdt_addr_t addr;

	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	plat->reg = (void *)addr;
	plat->flags = dev_get_driver_data(dev);

	if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
		plat->devtype = DEV_LS1021A;
	else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
		plat->devtype = DEV_MX7ULP;
	else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
		plat->devtype = DEV_VF610;

	return 0;
}

static const struct dm_serial_ops lpuart_serial_ops = {
	.putc = lpuart_serial_putc,
	.pending = lpuart_serial_pending,
	.getc = lpuart_serial_getc,
	.setbrg = lpuart_serial_setbrg,
};

static const struct udevice_id lpuart_serial_ids[] = {
	{ .compatible = "fsl,ls1021a-lpuart", .data =
		LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
	{ .compatible = "fsl,imx7ulp-lpuart",
		.data = LPUART_FLAG_REGMAP_32BIT_REG },
	{ .compatible = "fsl,vf610-lpuart"},
	{ }
};

U_BOOT_DRIVER(serial_lpuart) = {
	.name	= "serial_lpuart",
	.id	= UCLASS_SERIAL,
	.of_match = lpuart_serial_ids,
	.ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
	.probe = lpuart_serial_probe,
	.ops	= &lpuart_serial_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
427eba70 AW	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
427eba70 AW	5	*/
	6
	7	#include <common.h>
fdbae099	8	#include <dm.h>
c40d612b	9	#include <fsl_lpuart.h>
427eba70 AW	10	#include <watchdog.h>
	11	#include <asm/io.h>
	12	#include <serial.h>
	13	#include <linux/compiler.h>
	14	#include <asm/arch/imx-regs.h>
	15	#include <asm/arch/clock.h>
	16
47f1bfca BM	17	#define US1_TDRE (1 << 7)
	18	#define US1_RDRF (1 << 5)
	19	#define US1_OR (1 << 3)
	20	#define UC2_TE (1 << 3)
	21	#define UC2_RE (1 << 2)
	22	#define CFIFO_TXFLUSH (1 << 7)
	23	#define CFIFO_RXFLUSH (1 << 6)
	24	#define SFIFO_RXOF (1 << 2)
	25	#define SFIFO_RXUF (1 << 0)
427eba70	26
6209e14c JL	27	#define STAT_LBKDIF (1 << 31)
	28	#define STAT_RXEDGIF (1 << 30)
	29	#define STAT_TDRE (1 << 23)
	30	#define STAT_RDRF (1 << 21)
	31	#define STAT_IDLE (1 << 20)
	32	#define STAT_OR (1 << 19)
	33	#define STAT_NF (1 << 18)
	34	#define STAT_FE (1 << 17)
	35	#define STAT_PF (1 << 16)
	36	#define STAT_MA1F (1 << 15)
	37	#define STAT_MA2F (1 << 14)
	38	#define STAT_FLAGS (STAT_LBKDIF \| STAT_RXEDGIF \| STAT_IDLE \| STAT_OR \| \
47f1bfca	39	STAT_NF \| STAT_FE \| STAT_PF \| STAT_MA1F \| STAT_MA2F)
6209e14c JL	40
	41	#define CTRL_TE (1 << 19)
	42	#define CTRL_RE (1 << 18)
	43
	44	#define FIFO_TXFE 0x80
	45	#define FIFO_RXFE 0x40
	46
	47	#define WATER_TXWATER_OFF 1
	48	#define WATER_RXWATER_OFF 16
	49
427eba70 AW	50	DECLARE_GLOBAL_DATA_PTR;
427eba70 AW	51
c40d612b PF	52	#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
	53	#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
	54
7edf5c45 PF	55	enum lpuart_devtype {
	56	DEV_VF610 = 1,
	57	DEV_LS1021A,
	58	DEV_MX7ULP
	59	};
	60
fdbae099	61	struct lpuart_serial_platdata {
c40d612b	62	void *reg;
7edf5c45	63	enum lpuart_devtype devtype;
c40d612b	64	ulong flags;
fdbae099 BM	65	};
fdbae099 BM	66
c40d612b PF	67	static void lpuart_read32(u32 flags, u32 addr, u32 val)
	68	{
	69	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
	70	if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
	71	(u32 )val = in_be32(addr);
	72	else
	73	(u32 )val = in_le32(addr);
	74	}
	75	}
	76
	77	static void lpuart_write32(u32 flags, u32 *addr, u32 val)
	78	{
	79	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
	80	if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
	81	out_be32(addr, val);
	82	else
	83	out_le32(addr, val);
	84	}
	85	}
	86
	87
	88	#ifndef CONFIG_SYS_CLK_FREQ
	89	#define CONFIG_SYS_CLK_FREQ 0
	90	#endif
	91
	92	u32 __weak get_lpuart_clk(void)
427eba70	93	{
c40d612b PF	94	return CONFIG_SYS_CLK_FREQ;
	95	}
	96
	97	static bool is_lpuart32(struct udevice *dev)
	98	{
	99	struct lpuart_serial_platdata *plat = dev->platdata;
	100
	101	return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
	102	}
	103
	104	static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat,
	105	int baudrate)
	106	{
	107	struct lpuart_fsl *base = plat->reg;
	108	u32 clk = get_lpuart_clk();
427eba70 AW	109	u16 sbr;
427eba70 AW	110
6ca13b12	111	sbr = (u16)(clk / (16 * baudrate));
427eba70	112
47f1bfca	113	/* place adjustment later - n/32 BRFA */
427eba70 AW	114	__raw_writeb(sbr >> 8, &base->ubdh);
	115	__raw_writeb(sbr & 0xff, &base->ubdl);
	116	}
	117
c40d612b	118	static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
427eba70	119	{
c40d612b	120	struct lpuart_fsl *base = plat->reg;
a3db78d8	121	while (!(__raw_readb(&base->us1) & (US1_RDRF \| US1_OR)))
427eba70 AW	122	WATCHDOG_RESET();
427eba70 AW	123
a3db78d8	124	barrier();
427eba70 AW	125
	126	return __raw_readb(&base->ud);
	127	}
	128
c40d612b PF	129	static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
c40d612b PF	130	const char c)
427eba70	131	{
c40d612b PF	132	struct lpuart_fsl *base = plat->reg;
c40d612b PF	133
427eba70 AW	134	while (!(__raw_readb(&base->us1) & US1_TDRE))
	135	WATCHDOG_RESET();
	136
	137	__raw_writeb(c, &base->ud);
	138	}
	139
47f1bfca	140	/* Test whether a character is in the RX buffer */
c40d612b	141	static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
427eba70	142	{
c40d612b PF	143	struct lpuart_fsl *base = plat->reg;
c40d612b PF	144
427eba70 AW	145	if (__raw_readb(&base->urcfifo) == 0)
	146	return 0;
	147
	148	return 1;
	149	}
	150
	151	/*
	152	* Initialise the serial port with the given baudrate. The settings
	153	* are always 8 data bits, no parity, 1 stop bit, no start bits.
	154	*/
c40d612b	155	static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)
427eba70	156	{
c40d612b	157	struct lpuart_fsl base = (struct lpuart_fsl )plat->reg;
427eba70 AW	158	u8 ctrl;
	159
	160	ctrl = __raw_readb(&base->uc2);
	161	ctrl &= ~UC2_RE;
	162	ctrl &= ~UC2_TE;
	163	__raw_writeb(ctrl, &base->uc2);
	164
	165	__raw_writeb(0, &base->umodem);
	166	__raw_writeb(0, &base->uc1);
	167
89e69fd4 SA	168	/* Disable FIFO and flush buffer */
	169	__raw_writeb(0x0, &base->upfifo);
	170	__raw_writeb(0x0, &base->utwfifo);
	171	__raw_writeb(0x1, &base->urwfifo);
	172	__raw_writeb(CFIFO_TXFLUSH \| CFIFO_RXFLUSH, &base->ucfifo);
	173
427eba70	174	/* provide data bits, parity, stop bit, etc */
c40d612b	175	_lpuart_serial_setbrg(plat, gd->baudrate);
427eba70 AW	176
	177	__raw_writeb(UC2_RE \| UC2_TE, &base->uc2);
	178
	179	return 0;
	180	}
	181
7edf5c45 PF	182	static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat,
	183	int baudrate)
	184	{
	185	struct lpuart_fsl_reg32 *base = plat->reg;
	186	u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
	187	u32 clk = get_lpuart_clk();
	188
	189	baud_diff = baudrate;
	190	osr = 0;
	191	sbr = 0;
	192
	193	for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
	194	tmp_sbr = (clk / (baudrate * tmp_osr));
	195
	196	if (tmp_sbr == 0)
	197	tmp_sbr = 1;
	198
	199	/calculate difference in actual buad w/ current values /
	200	tmp_diff = (clk / (tmp_osr * tmp_sbr));
	201	tmp_diff = tmp_diff - baudrate;
	202
	203	/* select best values between sbr and sbr+1 */
	204	if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
	205	tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
	206	tmp_sbr++;
	207	}
	208
	209	if (tmp_diff <= baud_diff) {
	210	baud_diff = tmp_diff;
	211	osr = tmp_osr;
	212	sbr = tmp_sbr;
	213	}
	214	}
	215
	216	/*
	217	* TODO: handle buadrate outside acceptable rate
	218	* if (baudDiff > ((config->baudRate_Bps / 100) * 3))
	219	* {
	220	* Unacceptable baud rate difference of more than 3%
	221	* return kStatus_LPUART_BaudrateNotSupport;
	222	* }
	223	*/
	224	tmp = in_le32(&base->baud);
	225
	226	if ((osr > 3) && (osr < 8))
	227	tmp \|= LPUART_BAUD_BOTHEDGE_MASK;
	228
	229	tmp &= ~LPUART_BAUD_OSR_MASK;
	230	tmp \|= LPUART_BAUD_OSR(osr-1);
	231
	232	tmp &= ~LPUART_BAUD_SBR_MASK;
	233	tmp \|= LPUART_BAUD_SBR(sbr);
	234
	235	/* explicitly disable 10 bit mode & set 1 stop bit */
	236	tmp &= ~(LPUART_BAUD_M10_MASK \| LPUART_BAUD_SBNS_MASK);
	237
	238	out_le32(&base->baud, tmp);
	239	}
	240
c40d612b PF	241	static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat,
c40d612b PF	242	int baudrate)
6209e14c	243	{
c40d612b	244	struct lpuart_fsl_reg32 *base = plat->reg;
9b46213b	245	u32 clk = get_lpuart_clk();
6209e14c JL	246	u32 sbr;
6209e14c JL	247
6ca13b12	248	sbr = (clk / (16 * baudrate));
6209e14c	249
47f1bfca	250	/* place adjustment later - n/32 BRFA */
c40d612b	251	lpuart_write32(plat->flags, &base->baud, sbr);
6209e14c JL	252	}
6209e14c JL	253
c40d612b	254	static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
6209e14c	255	{
c40d612b	256	struct lpuart_fsl_reg32 *base = plat->reg;
7edf5c45	257	u32 stat, val;
6209e14c	258
c40d612b PF	259	lpuart_read32(plat->flags, &base->stat, &stat);
	260	while ((stat & STAT_RDRF) == 0) {
	261	lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
6209e14c	262	WATCHDOG_RESET();
c40d612b	263	lpuart_read32(plat->flags, &base->stat, &stat);
6209e14c JL	264	}
6209e14c JL	265
7edf5c45	266	lpuart_read32(plat->flags, &base->data, &val);
c40d612b	267
a2bbfc54 SD	268	lpuart_read32(plat->flags, &base->stat, &stat);
	269	if (stat & STAT_OR)
	270	lpuart_write32(plat->flags, &base->stat, STAT_OR);
7edf5c45 PF	271
7edf5c45 PF	272	return val & 0x3ff;
6209e14c JL	273	}
6209e14c JL	274
c40d612b PF	275	static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
c40d612b PF	276	const char c)
6209e14c	277	{
c40d612b PF	278	struct lpuart_fsl_reg32 *base = plat->reg;
	279	u32 stat;
	280
a2bbfc54 SD	281	if (c == '\n')
a2bbfc54 SD	282	serial_putc('\r');
7edf5c45	283
c40d612b PF	284	while (true) {
	285	lpuart_read32(plat->flags, &base->stat, &stat);
	286
	287	if ((stat & STAT_TDRE))
	288	break;
	289
6209e14c	290	WATCHDOG_RESET();
c40d612b	291	}
6209e14c	292
c40d612b	293	lpuart_write32(plat->flags, &base->data, c);
6209e14c JL	294	}
6209e14c JL	295
47f1bfca	296	/* Test whether a character is in the RX buffer */
c40d612b	297	static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
6209e14c	298	{
c40d612b PF	299	struct lpuart_fsl_reg32 *base = plat->reg;
	300	u32 water;
	301
	302	lpuart_read32(plat->flags, &base->water, &water);
	303
	304	if ((water >> 24) == 0)
6209e14c JL	305	return 0;
	306
	307	return 1;
	308	}
	309
	310	/*
	311	* Initialise the serial port with the given baudrate. The settings
	312	* are always 8 data bits, no parity, 1 stop bit, no start bits.
	313	*/
c40d612b	314	static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
6209e14c	315	{
c40d612b PF	316	struct lpuart_fsl_reg32 base = (struct lpuart_fsl_reg32 )plat->reg;
c40d612b PF	317	u32 ctrl;
6209e14c	318
c40d612b	319	lpuart_read32(plat->flags, &base->ctrl, &ctrl);
6209e14c JL	320	ctrl &= ~CTRL_RE;
6209e14c JL	321	ctrl &= ~CTRL_TE;
c40d612b	322	lpuart_write32(plat->flags, &base->ctrl, ctrl);
6209e14c	323
c40d612b PF	324	lpuart_write32(plat->flags, &base->modir, 0);
c40d612b PF	325	lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE \| FIFO_RXFE));
6209e14c	326
c40d612b	327	lpuart_write32(plat->flags, &base->match, 0);
6209e14c	328
a2bbfc54	329	if (plat->devtype == DEV_MX7ULP) {
7edf5c45 PF	330	_lpuart32_serial_setbrg_7ulp(plat, gd->baudrate);
	331	} else {
	332	/* provide data bits, parity, stop bit, etc */
	333	_lpuart32_serial_setbrg(plat, gd->baudrate);
	334	}
6209e14c	335
c40d612b	336	lpuart_write32(plat->flags, &base->ctrl, CTRL_RE \| CTRL_TE);
6209e14c JL	337
	338	return 0;
	339	}
	340
c40d612b	341	static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
fdbae099 BM	342	{
fdbae099 BM	343	struct lpuart_serial_platdata *plat = dev->platdata;
fdbae099	344
7edf5c45	345	if (is_lpuart32(dev)) {
a2bbfc54	346	if (plat->devtype == DEV_MX7ULP)
7edf5c45 PF	347	_lpuart32_serial_setbrg_7ulp(plat, baudrate);
	348	else
	349	_lpuart32_serial_setbrg(plat, baudrate);
	350	} else {
c40d612b	351	_lpuart_serial_setbrg(plat, baudrate);
7edf5c45	352	}
fdbae099 BM	353
	354	return 0;
	355	}
	356
c40d612b	357	static int lpuart_serial_getc(struct udevice *dev)
fdbae099 BM	358	{
fdbae099 BM	359	struct lpuart_serial_platdata *plat = dev->platdata;
fdbae099	360
c40d612b PF	361	if (is_lpuart32(dev))
	362	return _lpuart32_serial_getc(plat);
	363
	364	return _lpuart_serial_getc(plat);
fdbae099 BM	365	}
fdbae099 BM	366
c40d612b	367	static int lpuart_serial_putc(struct udevice *dev, const char c)
fdbae099 BM	368	{
fdbae099 BM	369	struct lpuart_serial_platdata *plat = dev->platdata;
fdbae099	370
c40d612b PF	371	if (is_lpuart32(dev))
	372	_lpuart32_serial_putc(plat, c);
	373	else
	374	_lpuart_serial_putc(plat, c);
fdbae099 BM	375
	376	return 0;
	377	}
	378
c40d612b	379	static int lpuart_serial_pending(struct udevice *dev, bool input)
fdbae099 BM	380	{
	381	struct lpuart_serial_platdata *plat = dev->platdata;
	382	struct lpuart_fsl *reg = plat->reg;
c40d612b PF	383	struct lpuart_fsl_reg32 *reg32 = plat->reg;
	384	u32 stat;
	385
	386	if (is_lpuart32(dev)) {
	387	if (input) {
	388	return _lpuart32_serial_tstc(plat);
	389	} else {
	390	lpuart_read32(plat->flags, &reg32->stat, &stat);
	391	return stat & STAT_TDRE ? 0 : 1;
	392	}
	393	}
fdbae099 BM	394
fdbae099 BM	395	if (input)
c40d612b	396	return _lpuart_serial_tstc(plat);
fdbae099	397	else
c40d612b	398	return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
fdbae099 BM	399	}
fdbae099 BM	400
c40d612b	401	static int lpuart_serial_probe(struct udevice *dev)
fdbae099 BM	402	{
fdbae099 BM	403	struct lpuart_serial_platdata *plat = dev->platdata;
fdbae099	404
c40d612b PF	405	if (is_lpuart32(dev))
	406	return _lpuart32_serial_init(plat);
	407	else
	408	return _lpuart_serial_init(plat);
fdbae099	409	}
427eba70	410
fdbae099 BM	411	static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
	412	{
	413	struct lpuart_serial_platdata *plat = dev->platdata;
7edf5c45	414	const void *blob = gd->fdt_blob;
da409ccc	415	int node = dev_of_offset(dev);
fdbae099 BM	416	fdt_addr_t addr;
fdbae099 BM	417
a821c4af	418	addr = devfdt_get_addr(dev);
fdbae099 BM	419	if (addr == FDT_ADDR_T_NONE)
	420	return -EINVAL;
	421
c40d612b PF	422	plat->reg = (void *)addr;
c40d612b PF	423	plat->flags = dev_get_driver_data(dev);
fdbae099	424
7edf5c45 PF	425	if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
	426	plat->devtype = DEV_LS1021A;
	427	else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
	428	plat->devtype = DEV_MX7ULP;
	429	else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
	430	plat->devtype = DEV_VF610;
	431
fdbae099 BM	432	return 0;
	433	}
	434
fdbae099 BM	435	static const struct dm_serial_ops lpuart_serial_ops = {
	436	.putc = lpuart_serial_putc,
	437	.pending = lpuart_serial_pending,
	438	.getc = lpuart_serial_getc,
	439	.setbrg = lpuart_serial_setbrg,
	440	};
	441
	442	static const struct udevice_id lpuart_serial_ids[] = {
c40d612b PF	443	{ .compatible = "fsl,ls1021a-lpuart", .data =
c40d612b PF	444	LPUART_FLAG_REGMAP_32BIT_REG \| LPUART_FLAG_REGMAP_ENDIAN_BIG },
7edf5c45 PF	445	{ .compatible = "fsl,imx7ulp-lpuart",
7edf5c45 PF	446	.data = LPUART_FLAG_REGMAP_32BIT_REG },
c40d612b	447	{ .compatible = "fsl,vf610-lpuart"},
fdbae099 BM	448	{ }
	449	};
	450
	451	U_BOOT_DRIVER(serial_lpuart) = {
	452	.name = "serial_lpuart",
	453	.id = UCLASS_SERIAL,
	454	.of_match = lpuart_serial_ids,
	455	.ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
	456	.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
	457	.probe = lpuart_serial_probe,
	458	.ops = &lpuart_serial_ops,
	459	.flags = DM_FLAG_PRE_RELOC,
	460	};