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musb: Program extvbus for OMAP3EVM Rev >= E
[people/ms/u-boot.git] / drivers / usb / host / ohci-hcd.c
CommitLineData
3e326ece 1/*
4dae14ce
ZW		 2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
3 *
4 * Interrupt support is added. Now, it has been tested
5 * on ULI1575 chip and works well with USB keyboard.
6 *
7 * (C) Copyright 2007
8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
3e326ece
MK		 9 *
10 * (C) Copyright 2003
792a09eb 11 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
3e326ece
MK		 12 *
13 * Note: Much of this code has been derived from Linux 2.4
14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
15 * (C) Copyright 2000-2002 David Brownell
16 *
17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
18 * ebenard@eukrea.com - based on s3c24x0's driver
19 *
20 * See file CREDITS for list of people who contributed to this
21 * project.
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
ae0b05df 30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3e326ece
MK		 31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 * MA 02111-1307 USA
37 *
38 */
39/*
40 * IMPORTANT NOTES
fc43be47 41 * 1 - Read doc/README.generic_usb_ohci
3e326ece 42 * 2 - this driver is intended for use with USB Mass Storage Devices
4dae14ce 43 * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
fc43be47 44 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
3e326ece
MK		 45 * to activate workaround for bug #41 or this driver will NOT work!
46 */
47
48#include <common.h>
fc43be47
MK		 49#include <asm/byteorder.h>
50
51#if defined(CONFIG_PCI_OHCI)
4dae14ce 52# include <pci.h>
477434c6
SP		 53#if !defined(CONFIG_PCI_OHCI_DEVNO)
54#define CONFIG_PCI_OHCI_DEVNO 0
55#endif
ddf83a2f 56#endif
3e326ece
MK		 57
58#include <malloc.h>
59#include <usb.h>
2731b9a8
JCPV		 60
61#include "ohci.h"
3e326ece 62
e8da58f2
WD		 63#ifdef CONFIG_AT91RM9200
64#include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
65#endif
66
ddf83a2f 67#if defined(CONFIG_ARM920T) || \
ac67804f 68 defined(CONFIG_S3C24X0) || \
8262813c 69 defined(CONFIG_S3C6400) || \
ae3b770e 70 defined(CONFIG_440EP) || \
4dae14ce 71 defined(CONFIG_PCI_OHCI) || \
2596f5b9 72 defined(CONFIG_MPC5200) || \
6d0f6bcf 73 defined(CONFIG_SYS_OHCI_USE_NPS)
24e37645
MK		 74# define OHCI_USE_NPS /* force NoPowerSwitching mode */
75#endif
76
3e326ece 77#undef OHCI_VERBOSE_DEBUG /* not always helpful */
ae3b770e
MK		 78#undef DEBUG
79#undef SHOW_INFO
80#undef OHCI_FILL_TRACE
3e326ece
MK		 81
82/* For initializing controller (mask in an HCFS mode too) */
83#define OHCI_CONTROL_INIT \
84 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
85
fc43be47
MK		 86/*
87 * e.g. PCI controllers need this
88 */
6d0f6bcf 89#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
f957576c
MK		 90# define readl(a) __swap_32(*((volatile u32 *)(a)))
91# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
fc43be47 92#else
f957576c
MK		 93# define readl(a) (*((volatile u32 *)(a)))
94# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
6d0f6bcf 95#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
3e326ece 96
6f5794a6
RB		 97#define min_t(type, x, y) \
98 ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
3e326ece 99
4dae14ce
ZW		 100#ifdef CONFIG_PCI_OHCI
101static struct pci_device_id ohci_pci_ids[] = {
102 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
97213f32 103 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
3afac79e 104 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */
4dae14ce
ZW		 105 /* Please add supported PCI OHCI controller ids here */
106 {0, 0}
107};
108#endif
109
e90fb6af
YT		 110#ifdef CONFIG_PCI_EHCI_DEVNO
111static struct pci_device_id ehci_pci_ids[] = {
112 {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */
113 /* Please add supported PCI EHCI controller ids here */
114 {0, 0}
115};
116#endif
117
3e326ece
MK		 118#ifdef DEBUG
119#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
120#else
6f5794a6 121#define dbg(format, arg...) do {} while (0)
3e326ece
MK		 122#endif /* DEBUG */
123#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
3e326ece
MK		 124#ifdef SHOW_INFO
125#define info(format, arg...) printf("INFO: " format "\n", ## arg)
126#else
6f5794a6 127#define info(format, arg...) do {} while (0)
3e326ece
MK		 128#endif
129
6d0f6bcf 130#ifdef CONFIG_SYS_OHCI_BE_CONTROLLER
fc43be47
MK		 131# define m16_swap(x) cpu_to_be16(x)
132# define m32_swap(x) cpu_to_be32(x)
ae3b770e 133#else
fc43be47
MK		 134# define m16_swap(x) cpu_to_le16(x)
135# define m32_swap(x) cpu_to_le32(x)
6d0f6bcf 136#endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
3e326ece
MK		 137
138/* global ohci_t */
139static ohci_t gohci;
140/* this must be aligned to a 256 byte boundary */
141struct ohci_hcca ghcca[1];
142/* a pointer to the aligned storage */
143struct ohci_hcca *phcca;
144/* this allocates EDs for all possible endpoints */
145struct ohci_device ohci_dev;
3e326ece
MK		 146/* device which was disconnected */
147struct usb_device *devgone;
148
6f5794a6
RB		 149static inline u32 roothub_a(struct ohci *hc)
150 { return readl(&hc->regs->roothub.a); }
151static inline u32 roothub_b(struct ohci *hc)
152 { return readl(&hc->regs->roothub.b); }
153static inline u32 roothub_status(struct ohci *hc)
154 { return readl(&hc->regs->roothub.status); }
155static inline u32 roothub_portstatus(struct ohci *hc, int i)
156 { return readl(&hc->regs->roothub.portstatus[i]); }
3e326ece 157
3e326ece 158/* forward declaration */
6f5794a6
RB		 159static int hc_interrupt(void);
160static void td_submit_job(struct usb_device *dev, unsigned long pipe,
161 void *buffer, int transfer_len,
162 struct devrequest *setup, urb_priv_t *urb,
163 int interval);
3e326ece
MK		 164
165/*-------------------------------------------------------------------------*
166 * URB support functions
167 *-------------------------------------------------------------------------*/
168
169/* free HCD-private data associated with this URB */
170
6f5794a6 171static void urb_free_priv(urb_priv_t *urb)
3e326ece
MK		 172{
173 int i;
174 int last;
6f5794a6 175 struct td *td;
3e326ece
MK		 176
177 last = urb->length - 1;
178 if (last >= 0) {
179 for (i = 0; i <= last; i++) {
180 td = urb->td[i];
181 if (td) {
182 td->usb_dev = NULL;
183 urb->td[i] = NULL;
184 }
185 }
186 }
4dae14ce 187 free(urb);
3e326ece
MK		 188}
189
190/*-------------------------------------------------------------------------*/
191
192#ifdef DEBUG
6f5794a6 193static int sohci_get_current_frame_number(struct usb_device *dev);
3e326ece
MK		 194
195/* debug| print the main components of an URB
196 * small: 0) header + data packets 1) just header */
197
6f5794a6
RB		 198static void pkt_print(urb_priv_t *purb, struct usb_device *dev,
199 unsigned long pipe, void *buffer, int transfer_len,
200 struct devrequest *setup, char *str, int small)
3e326ece 201{
6f5794a6 202 dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
3e326ece 203 str,
6f5794a6
RB		 204 sohci_get_current_frame_number(dev),
205 usb_pipedevice(pipe),
206 usb_pipeendpoint(pipe),
207 usb_pipeout(pipe)? 'O': 'I',
208 usb_pipetype(pipe) < 2 ? \
209 (usb_pipeint(pipe)? "INTR": "ISOC"): \
210 (usb_pipecontrol(pipe)? "CTRL": "BULK"),
4dae14ce 211 (purb ? purb->actual_length : 0),
3e326ece
MK		 212 transfer_len, dev->status);
213#ifdef OHCI_VERBOSE_DEBUG
214 if (!small) {
215 int i, len;
216
6f5794a6
RB		 217 if (usb_pipecontrol(pipe)) {
218 printf(__FILE__ ": cmd(8):");
3e326ece 219 for (i = 0; i < 8 ; i++)
6f5794a6
RB		 220 printf(" %02x", ((__u8 *) setup) [i]);
221 printf("\n");
3e326ece
MK		 222 }
223 if (transfer_len > 0 && buffer) {
6f5794a6 224 printf(__FILE__ ": data(%d/%d):",
4dae14ce 225 (purb ? purb->actual_length : 0),
3e326ece 226 transfer_len);
6f5794a6 227 len = usb_pipeout(pipe)? transfer_len:
4dae14ce 228 (purb ? purb->actual_length : 0);
3e326ece 229 for (i = 0; i < 16 && i < len; i++)
6f5794a6
RB		 230 printf(" %02x", ((__u8 *) buffer) [i]);
231 printf("%s\n", i < len? "...": "");
3e326ece
MK		 232 }
233 }
234#endif
235}
236
6f5794a6
RB		 237/* just for debugging; prints non-empty branches of the int ed tree
238 * inclusive iso eds */
239void ep_print_int_eds(ohci_t *ohci, char *str)
240{
3e326ece 241 int i, j;
6f5794a6
RB		 242 __u32 *ed_p;
243 for (i = 0; i < 32; i++) {
3e326ece
MK		 244 j = 5;
245 ed_p = &(ohci->hcca->int_table [i]);
246 if (*ed_p == 0)
247 continue;
6f5794a6 248 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
3e326ece
MK		 249 while (*ed_p != 0 && j--) {
250 ed_t *ed = (ed_t *)m32_swap(ed_p);
6f5794a6 251 printf(" ed: %4x;", ed->hwINFO);
3e326ece
MK		 252 ed_p = &ed->hwNextED;
253 }
6f5794a6 254 printf("\n");
3e326ece
MK		 255 }
256}
257
6f5794a6 258static void ohci_dump_intr_mask(char *label, __u32 mask)
3e326ece 259{
6f5794a6 260 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
3e326ece
MK		 261 label,
262 mask,
263 (mask & OHCI_INTR_MIE) ? " MIE" : "",
264 (mask & OHCI_INTR_OC) ? " OC" : "",
265 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
266 (mask & OHCI_INTR_FNO) ? " FNO" : "",
267 (mask & OHCI_INTR_UE) ? " UE" : "",
268 (mask & OHCI_INTR_RD) ? " RD" : "",
269 (mask & OHCI_INTR_SF) ? " SF" : "",
270 (mask & OHCI_INTR_WDH) ? " WDH" : "",
271 (mask & OHCI_INTR_SO) ? " SO" : ""
272 );
273}
274
6f5794a6 275static void maybe_print_eds(char *label, __u32 value)
3e326ece
MK		 276{
277 ed_t *edp = (ed_t *)value;
278
279 if (value) {
6f5794a6
RB		 280 dbg("%s %08x", label, value);
281 dbg("%08x", edp->hwINFO);
282 dbg("%08x", edp->hwTailP);
283 dbg("%08x", edp->hwHeadP);
284 dbg("%08x", edp->hwNextED);
3e326ece
MK		 285 }
286}
287
6f5794a6 288static char *hcfs2string(int state)
3e326ece
MK		 289{
290 switch (state) {
6f5794a6
RB		 291 case OHCI_USB_RESET: return "reset";
292 case OHCI_USB_RESUME: return "resume";
293 case OHCI_USB_OPER: return "operational";
294 case OHCI_USB_SUSPEND: return "suspend";
3e326ece
MK		 295 }
296 return "?";
297}
298
299/* dump control and status registers */
6f5794a6 300static void ohci_dump_status(ohci_t *controller)
3e326ece
MK		 301{
302 struct ohci_regs *regs = controller->regs;
303 __u32 temp;
304
6f5794a6 305 temp = readl(&regs->revision) & 0xff;
3e326ece 306 if (temp != 0x10)
6f5794a6 307 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
3e326ece 308
6f5794a6
RB		 309 temp = readl(&regs->control);
310 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
3e326ece
MK		 311 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
312 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
313 (temp & OHCI_CTRL_IR) ? " IR" : "",
6f5794a6 314 hcfs2string(temp & OHCI_CTRL_HCFS),
3e326ece
MK		 315 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
316 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
317 (temp & OHCI_CTRL_IE) ? " IE" : "",
318 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
319 temp & OHCI_CTRL_CBSR
320 );
321
6f5794a6
RB		 322 temp = readl(&regs->cmdstatus);
323 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
3e326ece
MK		 324 (temp & OHCI_SOC) >> 16,
325 (temp & OHCI_OCR) ? " OCR" : "",
326 (temp & OHCI_BLF) ? " BLF" : "",
327 (temp & OHCI_CLF) ? " CLF" : "",
328 (temp & OHCI_HCR) ? " HCR" : ""
329 );
330
6f5794a6
RB		 331 ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
332 ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
3e326ece 333
6f5794a6 334 maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
3e326ece 335
6f5794a6
RB		 336 maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
337 maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
3e326ece 338
6f5794a6
RB		 339 maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
340 maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
3e326ece 341
6f5794a6 342 maybe_print_eds("donehead", readl(&regs->donehead));
3e326ece
MK		 343}
344
6f5794a6 345static void ohci_dump_roothub(ohci_t *controller, int verbose)
3e326ece
MK		 346{
347 __u32 temp, ndp, i;
348
6f5794a6 349 temp = roothub_a(controller);
3e326ece
MK		 350 ndp = (temp & RH_A_NDP);
351#ifdef CONFIG_AT91C_PQFP_UHPBUG
352 ndp = (ndp == 2) ? 1:0;
3e326ece
MK		 353#endif
354 if (verbose) {
6f5794a6 355 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
3e326ece
MK		 356 ((temp & RH_A_POTPGT) >> 24) & 0xff,
357 (temp & RH_A_NOCP) ? " NOCP" : "",
358 (temp & RH_A_OCPM) ? " OCPM" : "",
359 (temp & RH_A_DT) ? " DT" : "",
360 (temp & RH_A_NPS) ? " NPS" : "",
361 (temp & RH_A_PSM) ? " PSM" : "",
362 ndp
363 );
6f5794a6
RB		 364 temp = roothub_b(controller);
365 dbg("roothub.b: %08x PPCM=%04x DR=%04x",
3e326ece
MK		 366 temp,
367 (temp & RH_B_PPCM) >> 16,
368 (temp & RH_B_DR)
369 );
6f5794a6
RB		 370 temp = roothub_status(controller);
371 dbg("roothub.status: %08x%s%s%s%s%s%s",
3e326ece
MK		 372 temp,
373 (temp & RH_HS_CRWE) ? " CRWE" : "",
374 (temp & RH_HS_OCIC) ? " OCIC" : "",
375 (temp & RH_HS_LPSC) ? " LPSC" : "",
376 (temp & RH_HS_DRWE) ? " DRWE" : "",
377 (temp & RH_HS_OCI) ? " OCI" : "",
378 (temp & RH_HS_LPS) ? " LPS" : ""
379 );
380 }
381
382 for (i = 0; i < ndp; i++) {
6f5794a6
RB		 383 temp = roothub_portstatus(controller, i);
384 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
3e326ece
MK		 385 i,
386 temp,
387 (temp & RH_PS_PRSC) ? " PRSC" : "",
388 (temp & RH_PS_OCIC) ? " OCIC" : "",
389 (temp & RH_PS_PSSC) ? " PSSC" : "",
390 (temp & RH_PS_PESC) ? " PESC" : "",
391 (temp & RH_PS_CSC) ? " CSC" : "",
392
393 (temp & RH_PS_LSDA) ? " LSDA" : "",
394 (temp & RH_PS_PPS) ? " PPS" : "",
395 (temp & RH_PS_PRS) ? " PRS" : "",
396 (temp & RH_PS_POCI) ? " POCI" : "",
397 (temp & RH_PS_PSS) ? " PSS" : "",
398
399 (temp & RH_PS_PES) ? " PES" : "",
400 (temp & RH_PS_CCS) ? " CCS" : ""
401 );
402 }
403}
404
6f5794a6 405static void ohci_dump(ohci_t *controller, int verbose)
3e326ece 406{
6f5794a6 407 dbg("OHCI controller usb-%s state", controller->slot_name);
3e326ece
MK		 408
409 /* dumps some of the state we know about */
6f5794a6 410 ohci_dump_status(controller);
3e326ece 411 if (verbose)
6f5794a6
RB		 412 ep_print_int_eds(controller, "hcca");
413 dbg("hcca frame #%04x", controller->hcca->frame_no);
414 ohci_dump_roothub(controller, 1);
2596f5b9 415}
3e326ece
MK		 416#endif /* DEBUG */
417
418/*-------------------------------------------------------------------------*
419 * Interface functions (URB)
420 *-------------------------------------------------------------------------*/
421
422/* get a transfer request */
423
4dae14ce 424int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
3e326ece
MK		 425{
426 ohci_t *ohci;
6f5794a6 427 ed_t *ed;
4dae14ce 428 urb_priv_t *purb_priv = urb;
3e326ece 429 int i, size = 0;
4dae14ce
ZW		 430 struct usb_device *dev = urb->dev;
431 unsigned long pipe = urb->pipe;
432 void *buffer = urb->transfer_buffer;
433 int transfer_len = urb->transfer_buffer_length;
434 int interval = urb->interval;
3e326ece
MK		 435
436 ohci = &gohci;
437
438 /* when controller's hung, permit only roothub cleanup attempts
439 * such as powering down ports */
440 if (ohci->disabled) {
441 err("sohci_submit_job: EPIPE");
442 return -1;
443 }
ae79f606 444
6f5794a6
RB		 445 /* we're about to begin a new transaction here so mark the
446 * URB unfinished */
4dae14ce 447 urb->finished = 0;
3e326ece
MK		 448
449 /* every endpoint has a ed, locate and fill it */
6f5794a6
RB		 450 ed = ep_add_ed(dev, pipe, interval, 1);
451 if (!ed) {
3e326ece
MK		 452 err("sohci_submit_job: ENOMEM");
453 return -1;
454 }
455
456 /* for the private part of the URB we need the number of TDs (size) */
6f5794a6
RB		 457 switch (usb_pipetype(pipe)) {
458 case PIPE_BULK: /* one TD for every 4096 Byte */
459 size = (transfer_len - 1) / 4096 + 1;
460 break;
461 case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
462 size = (transfer_len == 0)? 2:
463 (transfer_len - 1) / 4096 + 3;
464 break;
465 case PIPE_INTERRUPT: /* 1 TD */
466 size = 1;
467 break;
3e326ece
MK		 468 }
469
4dae14ce
ZW		 470 ed->purb = urb;
471
3e326ece
MK		 472 if (size >= (N_URB_TD - 1)) {
473 err("need %d TDs, only have %d", size, N_URB_TD);
474 return -1;
475 }
3e326ece
MK		 476 purb_priv->pipe = pipe;
477
478 /* fill the private part of the URB */
479 purb_priv->length = size;
480 purb_priv->ed = ed;
481 purb_priv->actual_length = 0;
482
483 /* allocate the TDs */
484 /* note that td[0] was allocated in ep_add_ed */
485 for (i = 0; i < size; i++) {
6f5794a6 486 purb_priv->td[i] = td_alloc(dev);
3e326ece
MK		 487 if (!purb_priv->td[i]) {
488 purb_priv->length = i;
6f5794a6 489 urb_free_priv(purb_priv);
3e326ece
MK		 490 err("sohci_submit_job: ENOMEM");
491 return -1;
492 }
493 }
494
495 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
6f5794a6 496 urb_free_priv(purb_priv);
3e326ece
MK		 497 err("sohci_submit_job: EINVAL");
498 return -1;
499 }
500
501 /* link the ed into a chain if is not already */
502 if (ed->state != ED_OPER)
6f5794a6 503 ep_link(ohci, ed);
3e326ece
MK		 504
505 /* fill the TDs and link it to the ed */
6f5794a6
RB		 506 td_submit_job(dev, pipe, buffer, transfer_len,
507 setup, purb_priv, interval);
3e326ece
MK		 508
509 return 0;
510}
511
4dae14ce
ZW		 512static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
513{
514 struct ohci_regs *regs = hc->regs;
515
6f5794a6 516 switch (usb_pipetype(urb->pipe)) {
4dae14ce
ZW		 517 case PIPE_INTERRUPT:
518 /* implicitly requeued */
519 if (urb->dev->irq_handle &&
520 (urb->dev->irq_act_len = urb->actual_length)) {
6f5794a6
RB		 521 writel(OHCI_INTR_WDH, &regs->intrenable);
522 readl(&regs->intrenable); /* PCI posting flush */
4dae14ce 523 urb->dev->irq_handle(urb->dev);
6f5794a6
RB		 524 writel(OHCI_INTR_WDH, &regs->intrdisable);
525 readl(&regs->intrdisable); /* PCI posting flush */
4dae14ce
ZW		 526 }
527 urb->actual_length = 0;
6f5794a6 528 td_submit_job(
4dae14ce
ZW		 529 urb->dev,
530 urb->pipe,
531 urb->transfer_buffer,
532 urb->transfer_buffer_length,
533 NULL,
534 urb,
535 urb->interval);
536 break;
537 case PIPE_CONTROL:
538 case PIPE_BULK:
539 break;
540 default:
541 return 0;
542 }
543 return 1;
544}
545
3e326ece
MK		 546/*-------------------------------------------------------------------------*/
547
548#ifdef DEBUG
549/* tell us the current USB frame number */
550
6f5794a6 551static int sohci_get_current_frame_number(struct usb_device *usb_dev)
3e326ece
MK		 552{
553 ohci_t *ohci = &gohci;
554
6f5794a6 555 return m16_swap(ohci->hcca->frame_no);
3e326ece
MK		 556}
557#endif
558
4dae14ce
ZW		 559/*-------------------------------------------------------------------------*
560 * ED handling functions
561 *-------------------------------------------------------------------------*/
562
563/* search for the right branch to insert an interrupt ed into the int tree
564 * do some load ballancing;
565 * returns the branch and
566 * sets the interval to interval = 2^integer (ld (interval)) */
567
6f5794a6 568static int ep_int_ballance(ohci_t *ohci, int interval, int load)
4dae14ce
ZW		 569{
570 int i, branch = 0;
571
572 /* search for the least loaded interrupt endpoint
573 * branch of all 32 branches
574 */
575 for (i = 0; i < 32; i++)
576 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
577 branch = i;
578
579 branch = branch % interval;
580 for (i = branch; i < 32; i += interval)
581 ohci->ohci_int_load [i] += load;
582
583 return branch;
584}
585
586/*-------------------------------------------------------------------------*/
587
588/* 2^int( ld (inter)) */
589
6f5794a6 590static int ep_2_n_interval(int inter)
4dae14ce
ZW		 591{
592 int i;
6f5794a6 593 for (i = 0; ((inter >> i) > 1) && (i < 5); i++);
4dae14ce
ZW		 594 return 1 << i;
595}
596
597/*-------------------------------------------------------------------------*/
598
599/* the int tree is a binary tree
6f5794a6
RB		 600 * in order to process it sequentially the indexes of the branches have to
601 * be mapped the mapping reverses the bits of a word of num_bits length */
602static int ep_rev(int num_bits, int word)
4dae14ce
ZW		 603{
604 int i, wout = 0;
605
606 for (i = 0; i < num_bits; i++)
607 wout |= (((word >> i) & 1) << (num_bits - i - 1));
608 return wout;
609}
610
3e326ece
MK		 611/*-------------------------------------------------------------------------*
612 * ED handling functions
613 *-------------------------------------------------------------------------*/
614
615/* link an ed into one of the HC chains */
616
6f5794a6 617static int ep_link(ohci_t *ohci, ed_t *edi)
3e326ece
MK		 618{
619 volatile ed_t *ed = edi;
4dae14ce
ZW		 620 int int_branch;
621 int i;
622 int inter;
623 int interval;
624 int load;
6f5794a6 625 __u32 *ed_p;
3e326ece
MK		 626
627 ed->state = ED_OPER;
4dae14ce 628 ed->int_interval = 0;
3e326ece
MK		 629
630 switch (ed->type) {
631 case PIPE_CONTROL:
632 ed->hwNextED = 0;
6f5794a6
RB		 633 if (ohci->ed_controltail == NULL)
634 writel(ed, &ohci->regs->ed_controlhead);
635 else
636 ohci->ed_controltail->hwNextED =
637 m32_swap((unsigned long)ed);
638
3e326ece
MK		 639 ed->ed_prev = ohci->ed_controltail;
640 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
641 !ohci->ed_rm_list[1] && !ohci->sleeping) {
642 ohci->hc_control |= OHCI_CTRL_CLE;
6f5794a6 643 writel(ohci->hc_control, &ohci->regs->control);
3e326ece
MK		 644 }
645 ohci->ed_controltail = edi;
646 break;
647
648 case PIPE_BULK:
649 ed->hwNextED = 0;
6f5794a6
RB		 650 if (ohci->ed_bulktail == NULL)
651 writel(ed, &ohci->regs->ed_bulkhead);
652 else
653 ohci->ed_bulktail->hwNextED =
654 m32_swap((unsigned long)ed);
655
3e326ece
MK		 656 ed->ed_prev = ohci->ed_bulktail;
657 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
658 !ohci->ed_rm_list[1] && !ohci->sleeping) {
659 ohci->hc_control |= OHCI_CTRL_BLE;
6f5794a6 660 writel(ohci->hc_control, &ohci->regs->control);
3e326ece
MK		 661 }
662 ohci->ed_bulktail = edi;
663 break;
4dae14ce
ZW		 664
665 case PIPE_INTERRUPT:
666 load = ed->int_load;
6f5794a6 667 interval = ep_2_n_interval(ed->int_period);
4dae14ce 668 ed->int_interval = interval;
6f5794a6 669 int_branch = ep_int_ballance(ohci, interval, load);
4dae14ce
ZW		 670 ed->int_branch = int_branch;
671
6f5794a6 672 for (i = 0; i < ep_rev(6, interval); i += inter) {
4dae14ce 673 inter = 1;
6f5794a6
RB		 674 for (ed_p = &(ohci->hcca->int_table[\
675 ep_rev(5, i) + int_branch]);
676 (*ed_p != 0) &&
677 (((ed_t *)ed_p)->int_interval >= interval);
4dae14ce 678 ed_p = &(((ed_t *)ed_p)->hwNextED))
6f5794a6
RB		 679 inter = ep_rev(6,
680 ((ed_t *)ed_p)->int_interval);
4dae14ce 681 ed->hwNextED = *ed_p;
4a8527ef 682 *ed_p = m32_swap((unsigned long)ed);
4dae14ce
ZW		 683 }
684 break;
3e326ece
MK		 685 }
686 return 0;
687}
688
689/*-------------------------------------------------------------------------*/
690
4dae14ce 691/* scan the periodic table to find and unlink this ED */
6f5794a6
RB		 692static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
693 unsigned index, unsigned period)
4dae14ce
ZW		 694{
695 for (; index < NUM_INTS; index += period) {
696 __u32 *ed_p = &ohci->hcca->int_table [index];
697
698 /* ED might have been unlinked through another path */
699 while (*ed_p != 0) {
6f5794a6
RB		 700 if (((struct ed *)
701 m32_swap((unsigned long)ed_p)) == ed) {
4dae14ce
ZW		 702 *ed_p = ed->hwNextED;
703 break;
704 }
6f5794a6
RB		 705 ed_p = &(((struct ed *)
706 m32_swap((unsigned long)ed_p))->hwNextED);
4dae14ce
ZW		 707 }
708 }
709}
710
3e326ece
MK		 711/* unlink an ed from one of the HC chains.
712 * just the link to the ed is unlinked.
713 * the link from the ed still points to another operational ed or 0
714 * so the HC can eventually finish the processing of the unlinked ed */
715
6f5794a6 716static int ep_unlink(ohci_t *ohci, ed_t *edi)
3e326ece 717{
53e336e9 718 volatile ed_t *ed = edi;
4dae14ce 719 int i;
53e336e9 720
6f5794a6 721 ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
3e326ece
MK		 722
723 switch (ed->type) {
724 case PIPE_CONTROL:
725 if (ed->ed_prev == NULL) {
726 if (!ed->hwNextED) {
727 ohci->hc_control &= ~OHCI_CTRL_CLE;
6f5794a6 728 writel(ohci->hc_control, &ohci->regs->control);
3e326ece 729 }
6f5794a6
RB		 730 writel(m32_swap(*((__u32 *)&ed->hwNextED)),
731 &ohci->regs->ed_controlhead);
3e326ece
MK		 732 } else {
733 ed->ed_prev->hwNextED = ed->hwNextED;
734 }
735 if (ohci->ed_controltail == ed) {
736 ohci->ed_controltail = ed->ed_prev;
737 } else {
6f5794a6
RB		 738 ((ed_t *)m32_swap(
739 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
3e326ece
MK		 740 }
741 break;
742
743 case PIPE_BULK:
744 if (ed->ed_prev == NULL) {
745 if (!ed->hwNextED) {
746 ohci->hc_control &= ~OHCI_CTRL_BLE;
6f5794a6 747 writel(ohci->hc_control, &ohci->regs->control);
3e326ece 748 }
6f5794a6
RB		 749 writel(m32_swap(*((__u32 *)&ed->hwNextED)),
750 &ohci->regs->ed_bulkhead);
3e326ece
MK		 751 } else {
752 ed->ed_prev->hwNextED = ed->hwNextED;
753 }
754 if (ohci->ed_bulktail == ed) {
755 ohci->ed_bulktail = ed->ed_prev;
756 } else {
6f5794a6
RB		 757 ((ed_t *)m32_swap(
758 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
3e326ece
MK		 759 }
760 break;
4dae14ce
ZW		 761
762 case PIPE_INTERRUPT:
6f5794a6 763 periodic_unlink(ohci, ed, 0, 1);
4dae14ce
ZW		 764 for (i = ed->int_branch; i < 32; i += ed->int_interval)
765 ohci->ohci_int_load[i] -= ed->int_load;
766 break;
3e326ece
MK		 767 }
768 ed->state = ED_UNLINK;
769 return 0;
770}
771
3e326ece
MK		 772/*-------------------------------------------------------------------------*/
773
ddf83a2f
MK		 774/* add/reinit an endpoint; this should be done once at the
775 * usb_set_configuration command, but the USB stack is a little bit
776 * stateless so we do it at every transaction if the state of the ed
777 * is ED_NEW then a dummy td is added and the state is changed to
778 * ED_UNLINK in all other cases the state is left unchanged the ed
779 * info fields are setted anyway even though most of them should not
780 * change
781 */
6f5794a6
RB		 782static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe,
783 int interval, int load)
3e326ece
MK		 784{
785 td_t *td;
786 ed_t *ed_ret;
787 volatile ed_t *ed;
788
6f5794a6
RB		 789 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
790 (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
3e326ece
MK		 791
792 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
793 err("ep_add_ed: pending delete");
794 /* pending delete request */
795 return NULL;
796 }
797
798 if (ed->state == ED_NEW) {
3e326ece 799 /* dummy td; end of td list for ed */
6f5794a6
RB		 800 td = td_alloc(usb_dev);
801 ed->hwTailP = m32_swap((unsigned long)td);
3e326ece
MK		 802 ed->hwHeadP = ed->hwTailP;
803 ed->state = ED_UNLINK;
6f5794a6 804 ed->type = usb_pipetype(pipe);
3e326ece
MK		 805 ohci_dev.ed_cnt++;
806 }
807
6f5794a6
RB		 808 ed->hwINFO = m32_swap(usb_pipedevice(pipe)
809 | usb_pipeendpoint(pipe) << 7
810 | (usb_pipeisoc(pipe)? 0x8000: 0)
811 | (usb_pipecontrol(pipe)? 0: \
812 (usb_pipeout(pipe)? 0x800: 0x1000))
813 | usb_pipeslow(pipe) << 13
814 | usb_maxpacket(usb_dev, pipe) << 16);
3e326ece 815
4dae14ce
ZW		 816 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
817 ed->int_period = interval;
818 ed->int_load = load;
819 }
820
3e326ece
MK		 821 return ed_ret;
822}
823
824/*-------------------------------------------------------------------------*
825 * TD handling functions
826 *-------------------------------------------------------------------------*/
827
828/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
829
6f5794a6 830static void td_fill(ohci_t *ohci, unsigned int info,
3e326ece
MK		 831 void *data, int len,
832 struct usb_device *dev, int index, urb_priv_t *urb_priv)
833{
834 volatile td_t *td, *td_pt;
835#ifdef OHCI_FILL_TRACE
836 int i;
837#endif
838
839 if (index > urb_priv->length) {
840 err("index > length");
841 return;
842 }
843 /* use this td as the next dummy */
844 td_pt = urb_priv->td [index];
845 td_pt->hwNextTD = 0;
846
847 /* fill the old dummy TD */
6f5794a6
RB		 848 td = urb_priv->td [index] =
849 (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf);
3e326ece
MK		 850
851 td->ed = urb_priv->ed;
852 td->next_dl_td = NULL;
853 td->index = index;
854 td->data = (__u32)data;
855#ifdef OHCI_FILL_TRACE
48867208 856 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
3e326ece 857 for (i = 0; i < len; i++)
6f5794a6 858 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
3e326ece
MK		 859 printf("\n");
860 }
861#endif
862 if (!len)
863 data = 0;
864
6f5794a6
RB		 865 td->hwINFO = m32_swap(info);
866 td->hwCBP = m32_swap((unsigned long)data);
3e326ece 867 if (data)
6f5794a6 868 td->hwBE = m32_swap((unsigned long)(data + len - 1));
3e326ece
MK		 869 else
870 td->hwBE = 0;
6f5794a6
RB		 871
872 td->hwNextTD = m32_swap((unsigned long)td_pt);
3e326ece
MK		 873
874 /* append to queue */
875 td->ed->hwTailP = td->hwNextTD;
876}
877
878/*-------------------------------------------------------------------------*/
879
880/* prepare all TDs of a transfer */
881
6f5794a6
RB		 882static void td_submit_job(struct usb_device *dev, unsigned long pipe,
883 void *buffer, int transfer_len,
884 struct devrequest *setup, urb_priv_t *urb,
885 int interval)
3e326ece
MK		 886{
887 ohci_t *ohci = &gohci;
888 int data_len = transfer_len;
889 void *data;
890 int cnt = 0;
891 __u32 info = 0;
892 unsigned int toggle = 0;
893
6f5794a6
RB		 894 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle
895 * bits for reseting */
896 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
3e326ece
MK		 897 toggle = TD_T_TOGGLE;
898 } else {
899 toggle = TD_T_DATA0;
6f5794a6
RB		 900 usb_settoggle(dev, usb_pipeendpoint(pipe),
901 usb_pipeout(pipe), 1);
3e326ece
MK		 902 }
903 urb->td_cnt = 0;
904 if (data_len)
905 data = buffer;
906 else
907 data = 0;
908
6f5794a6 909 switch (usb_pipetype(pipe)) {
3e326ece 910 case PIPE_BULK:
6f5794a6 911 info = usb_pipeout(pipe)?
3e326ece 912 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
6f5794a6
RB		 913 while (data_len > 4096) {
914 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle),
915 data, 4096, dev, cnt, urb);
3e326ece
MK		 916 data += 4096; data_len -= 4096; cnt++;
917 }
6f5794a6 918 info = usb_pipeout(pipe)?
3e326ece 919 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
6f5794a6
RB		 920 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data,
921 data_len, dev, cnt, urb);
3e326ece
MK		 922 cnt++;
923
6f5794a6
RB		 924 if (!ohci->sleeping) {
925 /* start bulk list */
926 writel(OHCI_BLF, &ohci->regs->cmdstatus);
927 }
3e326ece
MK		 928 break;
929
930 case PIPE_CONTROL:
6f5794a6 931 /* Setup phase */
3e326ece 932 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
6f5794a6
RB		 933 td_fill(ohci, info, setup, 8, dev, cnt++, urb);
934
935 /* Optional Data phase */
3e326ece 936 if (data_len > 0) {
6f5794a6
RB		 937 info = usb_pipeout(pipe)?
938 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
939 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
3e326ece 940 /* NOTE: mishandles transfers >8K, some >4K */
6f5794a6
RB		 941 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
942 }
943
944 /* Status phase */
945 info = usb_pipeout(pipe)?
946 TD_CC | TD_DP_IN | TD_T_DATA1:
947 TD_CC | TD_DP_OUT | TD_T_DATA1;
948 td_fill(ohci, info, data, 0, dev, cnt++, urb);
949
950 if (!ohci->sleeping) {
951 /* start Control list */
952 writel(OHCI_CLF, &ohci->regs->cmdstatus);
3e326ece 953 }
3e326ece 954 break;
4dae14ce
ZW		 955
956 case PIPE_INTERRUPT:
6f5794a6 957 info = usb_pipeout(urb->pipe)?
4dae14ce
ZW		 958 TD_CC | TD_DP_OUT | toggle:
959 TD_CC | TD_R | TD_DP_IN | toggle;
6f5794a6 960 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
4dae14ce 961 break;
3e326ece
MK		 962 }
963 if (urb->length != cnt)
964 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
965}
966
967/*-------------------------------------------------------------------------*
968 * Done List handling functions
969 *-------------------------------------------------------------------------*/
970
3e326ece
MK		 971/* calculate the transfer length and update the urb */
972
6f5794a6 973static void dl_transfer_length(td_t *td)
3e326ece
MK		 974{
975 __u32 tdINFO, tdBE, tdCBP;
4dae14ce 976 urb_priv_t *lurb_priv = td->ed->purb;
3e326ece 977
6f5794a6
RB		 978 tdINFO = m32_swap(td->hwINFO);
979 tdBE = m32_swap(td->hwBE);
980 tdCBP = m32_swap(td->hwCBP);
3e326ece 981
48867208 982 if (!(usb_pipecontrol(lurb_priv->pipe) &&
3e326ece
MK		 983 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
984 if (tdBE != 0) {
985 if (td->hwCBP == 0)
986 lurb_priv->actual_length += tdBE - td->data + 1;
987 else
988 lurb_priv->actual_length += tdCBP - td->data;
989 }
990 }
991}
992
993/*-------------------------------------------------------------------------*/
6f5794a6
RB		 994static void check_status(td_t *td_list)
995{
996 urb_priv_t *lurb_priv = td_list->ed->purb;
997 int urb_len = lurb_priv->length;
998 __u32 *phwHeadP = &td_list->ed->hwHeadP;
999 int cc;
1000
1001 cc = TD_CC_GET(m32_swap(td_list->hwINFO));
1002 if (cc) {
1003 err(" USB-error: %s (%x)", cc_to_string[cc], cc);
1004
1005 if (*phwHeadP & m32_swap(0x1)) {
1006 if (lurb_priv &&
1007 ((td_list->index + 1) < urb_len)) {
1008 *phwHeadP =
1009 (lurb_priv->td[urb_len - 1]->hwNextTD &\
1010 m32_swap(0xfffffff0)) |
1011 (*phwHeadP & m32_swap(0x2));
1012
1013 lurb_priv->td_cnt += urb_len -
1014 td_list->index - 1;
1015 } else
1016 *phwHeadP &= m32_swap(0xfffffff2);
1017 }
1018#ifdef CONFIG_MPC5200
1019 td_list->hwNextTD = 0;
1020#endif
1021 }
1022}
3e326ece
MK		 1023
1024/* replies to the request have to be on a FIFO basis so
1025 * we reverse the reversed done-list */
6f5794a6 1026static td_t *dl_reverse_done_list(ohci_t *ohci)
3e326ece
MK		 1027{
1028 __u32 td_list_hc;
1029 td_t *td_rev = NULL;
1030 td_t *td_list = NULL;
3e326ece 1031
6f5794a6 1032 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
3e326ece
MK		 1033 ohci->hcca->done_head = 0;
1034
1035 while (td_list_hc) {
1036 td_list = (td_t *)td_list_hc;
6f5794a6 1037 check_status(td_list);
3e326ece
MK		 1038 td_list->next_dl_td = td_rev;
1039 td_rev = td_list;
6f5794a6 1040 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
3e326ece
MK		 1041 }
1042 return td_list;
1043}
1044
6f5794a6 1045/*-------------------------------------------------------------------------*/
3e326ece
MK		 1046/*-------------------------------------------------------------------------*/
1047
6f5794a6
RB		 1048static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
1049{
1050 if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
1051 urb->finished = sohci_return_job(ohci, urb);
1052 else
1053 dbg("finish_urb: strange.., ED state %x, \n", status);
1054}
1055
1056/*
1057 * Used to take back a TD from the host controller. This would normally be
1058 * called from within dl_done_list, however it may be called directly if the
1059 * HC no longer sees the TD and it has not appeared on the donelist (after
1060 * two frames). This bug has been observed on ZF Micro systems.
1061 */
1062static int takeback_td(ohci_t *ohci, td_t *td_list)
3e326ece 1063{
3e326ece 1064 ed_t *ed;
6f5794a6 1065 int cc;
3e326ece
MK		 1066 int stat = 0;
1067 /* urb_t *urb; */
1068 urb_priv_t *lurb_priv;
1069 __u32 tdINFO, edHeadP, edTailP;
1070
6f5794a6 1071 tdINFO = m32_swap(td_list->hwINFO);
3e326ece 1072
6f5794a6
RB		 1073 ed = td_list->ed;
1074 lurb_priv = ed->purb;
3e326ece 1075
6f5794a6 1076 dl_transfer_length(td_list);
3e326ece 1077
6f5794a6 1078 lurb_priv->td_cnt++;
3e326ece 1079
6f5794a6
RB		 1080 /* error code of transfer */
1081 cc = TD_CC_GET(tdINFO);
1082 if (cc) {
1083 err("USB-error: %s (%x)", cc_to_string[cc], cc);
1084 stat = cc_to_error[cc];
1085 }
ae79f606 1086
6f5794a6
RB		 1087 /* see if this done list makes for all TD's of current URB,
1088 * and mark the URB finished if so */
1089 if (lurb_priv->td_cnt == lurb_priv->length)
1090 finish_urb(ohci, lurb_priv, ed->state);
1091
1092 dbg("dl_done_list: processing TD %x, len %x\n",
1093 lurb_priv->td_cnt, lurb_priv->length);
1094
48867208 1095 if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) {
6f5794a6
RB		 1096 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
1097 edTailP = m32_swap(ed->hwTailP);
1098
1099 /* unlink eds if they are not busy */
1100 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1101 ep_unlink(ohci, ed);
1102 }
1103 return stat;
1104}
3e326ece 1105
6f5794a6
RB		 1106static int dl_done_list(ohci_t *ohci)
1107{
1108 int stat = 0;
1109 td_t *td_list = dl_reverse_done_list(ohci);
1110
1111 while (td_list) {
1112 td_t *td_next = td_list->next_dl_td;
1113 stat = takeback_td(ohci, td_list);
1114 td_list = td_next;
3e326ece
MK		 1115 }
1116 return stat;
1117}
1118
1119/*-------------------------------------------------------------------------*
1120 * Virtual Root Hub
1121 *-------------------------------------------------------------------------*/
1122
1123/* Device descriptor */
1124static __u8 root_hub_dev_des[] =
1125{
1126 0x12, /* __u8 bLength; */
1127 0x01, /* __u8 bDescriptorType; Device */
1128 0x10, /* __u16 bcdUSB; v1.1 */
1129 0x01,
1130 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
1131 0x00, /* __u8 bDeviceSubClass; */
1132 0x00, /* __u8 bDeviceProtocol; */
1133 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
1134 0x00, /* __u16 idVendor; */
1135 0x00,
1136 0x00, /* __u16 idProduct; */
1137 0x00,
1138 0x00, /* __u16 bcdDevice; */
1139 0x00,
1140 0x00, /* __u8 iManufacturer; */
1141 0x01, /* __u8 iProduct; */
1142 0x00, /* __u8 iSerialNumber; */
1143 0x01 /* __u8 bNumConfigurations; */
1144};
1145
3e326ece
MK		 1146/* Configuration descriptor */
1147static __u8 root_hub_config_des[] =
1148{
1149 0x09, /* __u8 bLength; */
1150 0x02, /* __u8 bDescriptorType; Configuration */
1151 0x19, /* __u16 wTotalLength; */
1152 0x00,
1153 0x01, /* __u8 bNumInterfaces; */
1154 0x01, /* __u8 bConfigurationValue; */
1155 0x00, /* __u8 iConfiguration; */
1156 0x40, /* __u8 bmAttributes;
6f5794a6 1157 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
3e326ece
MK		 1158 0x00, /* __u8 MaxPower; */
1159
1160 /* interface */
1161 0x09, /* __u8 if_bLength; */
1162 0x04, /* __u8 if_bDescriptorType; Interface */
1163 0x00, /* __u8 if_bInterfaceNumber; */
1164 0x00, /* __u8 if_bAlternateSetting; */
1165 0x01, /* __u8 if_bNumEndpoints; */
1166 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
1167 0x00, /* __u8 if_bInterfaceSubClass; */
1168 0x00, /* __u8 if_bInterfaceProtocol; */
1169 0x00, /* __u8 if_iInterface; */
1170
1171 /* endpoint */
1172 0x07, /* __u8 ep_bLength; */
1173 0x05, /* __u8 ep_bDescriptorType; Endpoint */
1174 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
1175 0x03, /* __u8 ep_bmAttributes; Interrupt */
1176 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
1177 0x00,
1178 0xff /* __u8 ep_bInterval; 255 ms */
1179};
1180
1181static unsigned char root_hub_str_index0[] =
1182{
1183 0x04, /* __u8 bLength; */
1184 0x03, /* __u8 bDescriptorType; String-descriptor */
1185 0x09, /* __u8 lang ID */
1186 0x04, /* __u8 lang ID */
1187};
1188
1189static unsigned char root_hub_str_index1[] =
1190{
1191 28, /* __u8 bLength; */
1192 0x03, /* __u8 bDescriptorType; String-descriptor */
1193 'O', /* __u8 Unicode */
1194 0, /* __u8 Unicode */
1195 'H', /* __u8 Unicode */
1196 0, /* __u8 Unicode */
1197 'C', /* __u8 Unicode */
1198 0, /* __u8 Unicode */
1199 'I', /* __u8 Unicode */
1200 0, /* __u8 Unicode */
1201 ' ', /* __u8 Unicode */
1202 0, /* __u8 Unicode */
1203 'R', /* __u8 Unicode */
1204 0, /* __u8 Unicode */
1205 'o', /* __u8 Unicode */
1206 0, /* __u8 Unicode */
1207 'o', /* __u8 Unicode */
1208 0, /* __u8 Unicode */
1209 't', /* __u8 Unicode */
1210 0, /* __u8 Unicode */
1211 ' ', /* __u8 Unicode */
1212 0, /* __u8 Unicode */
1213 'H', /* __u8 Unicode */
1214 0, /* __u8 Unicode */
1215 'u', /* __u8 Unicode */
1216 0, /* __u8 Unicode */
1217 'b', /* __u8 Unicode */
1218 0, /* __u8 Unicode */
1219};
1220
1221/* Hub class-specific descriptor is constructed dynamically */
1222
3e326ece
MK		 1223/*-------------------------------------------------------------------------*/
1224
1225#define OK(x) len = (x); break
1226#ifdef DEBUG
6f5794a6
RB		 1227#define WR_RH_STAT(x) {info("WR:status %#8x", (x)); writel((x), \
1228 &gohci.regs->roothub.status); }
1229#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \
1230 (x)); writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); }
3e326ece
MK		 1231#else
1232#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
6f5794a6
RB		 1233#define WR_RH_PORTSTAT(x) writel((x), \
1234 &gohci.regs->roothub.portstatus[wIndex-1])
3e326ece
MK		 1235#endif
1236#define RD_RH_STAT roothub_status(&gohci)
6f5794a6 1237#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1)
3e326ece
MK		 1238
1239/* request to virtual root hub */
1240
1241int rh_check_port_status(ohci_t *controller)
1242{
1243 __u32 temp, ndp, i;
1244 int res;
1245
1246 res = -1;
6f5794a6 1247 temp = roothub_a(controller);
3e326ece
MK		 1248 ndp = (temp & RH_A_NDP);
1249#ifdef CONFIG_AT91C_PQFP_UHPBUG
1250 ndp = (ndp == 2) ? 1:0;
1251#endif
1252 for (i = 0; i < ndp; i++) {
6f5794a6 1253 temp = roothub_portstatus(controller, i);
3e326ece
MK		 1254 /* check for a device disconnect */
1255 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1256 (RH_PS_PESC | RH_PS_CSC)) &&
1257 ((temp & RH_PS_CCS) == 0)) {
1258 res = i;
1259 break;
1260 }
1261 }
1262 return res;
1263}
1264
1265static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1266 void *buffer, int transfer_len, struct devrequest *cmd)
1267{
6f5794a6 1268 void *data = buffer;
3e326ece
MK		 1269 int leni = transfer_len;
1270 int len = 0;
1271 int stat = 0;
1272 __u32 datab[4];
1273 __u8 *data_buf = (__u8 *)datab;
1274 __u16 bmRType_bReq;
1275 __u16 wValue;
1276 __u16 wIndex;
1277 __u16 wLength;
1278
1279#ifdef DEBUG
6f5794a6
RB		 1280pkt_print(NULL, dev, pipe, buffer, transfer_len,
1281 cmd, "SUB(rh)", usb_pipein(pipe));
3e326ece
MK		 1282#else
1283 wait_ms(1);
1284#endif
48867208 1285 if (usb_pipeint(pipe)) {
3e326ece
MK		 1286 info("Root-Hub submit IRQ: NOT implemented");
1287 return 0;
1288 }
1289
1290 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
6f5794a6
RB		 1291 wValue = le16_to_cpu(cmd->value);
1292 wIndex = le16_to_cpu(cmd->index);
1293 wLength = le16_to_cpu(cmd->length);
3e326ece
MK		 1294
1295 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1296 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1297
1298 switch (bmRType_bReq) {
1299 /* Request Destination:
1300 without flags: Device,
1301 RH_INTERFACE: interface,
1302 RH_ENDPOINT: endpoint,
1303 RH_CLASS means HUB here,
1304 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1305 */
1306
1307 case RH_GET_STATUS:
6f5794a6
RB		 1308 *(__u16 *) data_buf = cpu_to_le16(1);
1309 OK(2);
3e326ece 1310 case RH_GET_STATUS | RH_INTERFACE:
6f5794a6
RB		 1311 *(__u16 *) data_buf = cpu_to_le16(0);
1312 OK(2);
3e326ece 1313 case RH_GET_STATUS | RH_ENDPOINT:
6f5794a6
RB		 1314 *(__u16 *) data_buf = cpu_to_le16(0);
1315 OK(2);
3e326ece 1316 case RH_GET_STATUS | RH_CLASS:
6f5794a6 1317 *(__u32 *) data_buf = cpu_to_le32(
3e326ece 1318 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
6f5794a6 1319 OK(4);
3e326ece 1320 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
6f5794a6
RB		 1321 *(__u32 *) data_buf = cpu_to_le32(RD_RH_PORTSTAT);
1322 OK(4);
3e326ece
MK		 1323
1324 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1325 switch (wValue) {
6f5794a6
RB		 1326 case (RH_ENDPOINT_STALL):
1327 OK(0);
3e326ece
MK		 1328 }
1329 break;
1330
1331 case RH_CLEAR_FEATURE | RH_CLASS:
1332 switch (wValue) {
6f5794a6
RB		 1333 case RH_C_HUB_LOCAL_POWER:
1334 OK(0);
1335 case (RH_C_HUB_OVER_CURRENT):
1336 WR_RH_STAT(RH_HS_OCIC);
1337 OK(0);
3e326ece
MK		 1338 }
1339 break;
1340
1341 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1342 switch (wValue) {
6f5794a6
RB		 1343 case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0);
1344 case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
1345 case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
1346 case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0);
1347 case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
1348 case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
1349 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
1350 case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
3e326ece
MK		 1351 }
1352 break;
1353
1354 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1355 switch (wValue) {
6f5794a6
RB		 1356 case (RH_PORT_SUSPEND):
1357 WR_RH_PORTSTAT(RH_PS_PSS); OK(0);
1358 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1359 if (RD_RH_PORTSTAT & RH_PS_CCS)
1360 WR_RH_PORTSTAT(RH_PS_PRS);
1361 OK(0);
1362 case (RH_PORT_POWER):
1363 WR_RH_PORTSTAT(RH_PS_PPS);
1364 wait_ms(100);
1365 OK(0);
1366 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1367 if (RD_RH_PORTSTAT & RH_PS_CCS)
1368 WR_RH_PORTSTAT(RH_PS_PES);
1369 OK(0);
3e326ece
MK		 1370 }
1371 break;
1372
6f5794a6
RB		 1373 case RH_SET_ADDRESS:
1374 gohci.rh.devnum = wValue;
1375 OK(0);
3e326ece
MK		 1376
1377 case RH_GET_DESCRIPTOR:
1378 switch ((wValue & 0xff00) >> 8) {
6f5794a6
RB		 1379 case (0x01): /* device descriptor */
1380 len = min_t(unsigned int,
1381 leni,
1382 min_t(unsigned int,
1383 sizeof(root_hub_dev_des),
1384 wLength));
1385 data_buf = root_hub_dev_des; OK(len);
1386 case (0x02): /* configuration descriptor */
1387 len = min_t(unsigned int,
1388 leni,
1389 min_t(unsigned int,
1390 sizeof(root_hub_config_des),
1391 wLength));
1392 data_buf = root_hub_config_des; OK(len);
1393 case (0x03): /* string descriptors */
1394 if (wValue == 0x0300) {
3e326ece 1395 len = min_t(unsigned int,
6f5794a6
RB		 1396 leni,
1397 min_t(unsigned int,
1398 sizeof(root_hub_str_index0),
1399 wLength));
1400 data_buf = root_hub_str_index0;
1401 OK(len);
3e326ece 1402 }
6f5794a6
RB		 1403 if (wValue == 0x0301) {
1404 len = min_t(unsigned int,
1405 leni,
1406 min_t(unsigned int,
1407 sizeof(root_hub_str_index1),
1408 wLength));
1409 data_buf = root_hub_str_index1;
1410 OK(len);
1411 }
1412 default:
1413 stat = USB_ST_STALLED;
3e326ece
MK		 1414 }
1415 break;
1416
1417 case RH_GET_DESCRIPTOR | RH_CLASS:
1418 {
6f5794a6 1419 __u32 temp = roothub_a(&gohci);
3e326ece
MK		 1420
1421 data_buf [0] = 9; /* min length; */
1422 data_buf [1] = 0x29;
1423 data_buf [2] = temp & RH_A_NDP;
1424#ifdef CONFIG_AT91C_PQFP_UHPBUG
1425 data_buf [2] = (data_buf [2] == 2) ? 1:0;
1426#endif
3e326ece
MK		 1427 data_buf [3] = 0;
1428 if (temp & RH_A_PSM) /* per-port power switching? */
1429 data_buf [3] |= 0x1;
1430 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1431 data_buf [3] |= 0x10;
6f5794a6 1432 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
3e326ece 1433 data_buf [3] |= 0x8;
3e326ece
MK		 1434
1435 /* corresponds to data_buf[4-7] */
1436 datab [1] = 0;
1437 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
6f5794a6 1438 temp = roothub_b(&gohci);
3e326ece
MK		 1439 data_buf [7] = temp & RH_B_DR;
1440 if (data_buf [2] < 7) {
1441 data_buf [8] = 0xff;
1442 } else {
1443 data_buf [0] += 2;
1444 data_buf [8] = (temp & RH_B_DR) >> 8;
1445 data_buf [10] = data_buf [9] = 0xff;
1446 }
1447
1448 len = min_t(unsigned int, leni,
ddf83a2f 1449 min_t(unsigned int, data_buf [0], wLength));
6f5794a6 1450 OK(len);
3e326ece
MK		 1451 }
1452
6f5794a6 1453 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK(1);
3e326ece 1454
6f5794a6 1455 case RH_SET_CONFIGURATION: WR_RH_STAT(0x10000); OK(0);
3e326ece
MK		 1456
1457 default:
6f5794a6 1458 dbg("unsupported root hub command");
3e326ece
MK		 1459 stat = USB_ST_STALLED;
1460 }
1461
1462#ifdef DEBUG
6f5794a6 1463 ohci_dump_roothub(&gohci, 1);
3e326ece
MK		 1464#else
1465 wait_ms(1);
1466#endif
1467
1468 len = min_t(int, len, leni);
1469 if (data != data_buf)
6f5794a6 1470 memcpy(data, data_buf, len);
3e326ece
MK		 1471 dev->act_len = len;
1472 dev->status = stat;
1473
1474#ifdef DEBUG
6f5794a6
RB		 1475 pkt_print(NULL, dev, pipe, buffer,
1476 transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
3e326ece
MK		 1477#else
1478 wait_ms(1);
1479#endif
1480
1481 return stat;
1482}
1483
1484/*-------------------------------------------------------------------------*/
1485
1486/* common code for handling submit messages - used for all but root hub */
1487/* accesses. */
1488int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1489 int transfer_len, struct devrequest *setup, int interval)
1490{
1491 int stat = 0;
1492 int maxsize = usb_maxpacket(dev, pipe);
1493 int timeout;
4dae14ce
ZW		 1494 urb_priv_t *urb;
1495
1496 urb = malloc(sizeof(urb_priv_t));
1497 memset(urb, 0, sizeof(urb_priv_t));
1498
1499 urb->dev = dev;
1500 urb->pipe = pipe;
1501 urb->transfer_buffer = buffer;
1502 urb->transfer_buffer_length = transfer_len;
1503 urb->interval = interval;
3e326ece
MK		 1504
1505 /* device pulled? Shortcut the action. */
1506 if (devgone == dev) {
1507 dev->status = USB_ST_CRC_ERR;
1508 return 0;
1509 }
1510
1511#ifdef DEBUG
4dae14ce 1512 urb->actual_length = 0;
6f5794a6
RB		 1513 pkt_print(urb, dev, pipe, buffer, transfer_len,
1514 setup, "SUB", usb_pipein(pipe));
3e326ece
MK		 1515#else
1516 wait_ms(1);
1517#endif
1518 if (!maxsize) {
1519 err("submit_common_message: pipesize for pipe %lx is zero",
1520 pipe);
1521 return -1;
1522 }
1523
4dae14ce 1524 if (sohci_submit_job(urb, setup) < 0) {
3e326ece
MK		 1525 err("sohci_submit_job failed");
1526 return -1;
1527 }
1528
ae3b770e 1529#if 0
3e326ece
MK		 1530 wait_ms(10);
1531 /* ohci_dump_status(&gohci); */
ae3b770e 1532#endif
3e326ece
MK		 1533
1534 /* allow more time for a BULK device to react - some are slow */
1535#define BULK_TO 5000 /* timeout in milliseconds */
48867208 1536 if (usb_pipebulk(pipe))
3e326ece
MK		 1537 timeout = BULK_TO;
1538 else
1539 timeout = 100;
1540
1541 /* wait for it to complete */
1542 for (;;) {
1543 /* check whether the controller is done */
1544 stat = hc_interrupt();
1545 if (stat < 0) {
1546 stat = USB_ST_CRC_ERR;
1547 break;
1548 }
ddf83a2f 1549
ddf83a2f
MK		 1550 /* NOTE: since we are not interrupt driven in U-Boot and always
1551 * handle only one URB at a time, we cannot assume the
1552 * transaction finished on the first successful return from
1553 * hc_interrupt().. unless the flag for current URB is set,
1554 * meaning that all TD's to/from device got actually
1555 * transferred and processed. If the current URB is not
1556 * finished we need to re-iterate this loop so as
1557 * hc_interrupt() gets called again as there needs to be some
1558 * more TD's to process still */
4dae14ce 1559 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
3e326ece
MK		 1560 /* 0xff is returned for an SF-interrupt */
1561 break;
1562 }
ddf83a2f 1563
3e326ece
MK		 1564 if (--timeout) {
1565 wait_ms(1);
4dae14ce 1566 if (!urb->finished)
6f5794a6 1567 dbg("*");
4dae14ce 1568
3e326ece
MK		 1569 } else {
1570 err("CTL:TIMEOUT ");
ddf83a2f 1571 dbg("submit_common_msg: TO status %x\n", stat);
4dae14ce 1572 urb->finished = 1;
3e326ece
MK		 1573 stat = USB_ST_CRC_ERR;
1574 break;
1575 }
1576 }
3e326ece
MK		 1577
1578 dev->status = stat;
1579 dev->act_len = transfer_len;
1580
1581#ifdef DEBUG
6f5794a6
RB		 1582 pkt_print(urb, dev, pipe, buffer, transfer_len,
1583 setup, "RET(ctlr)", usb_pipein(pipe));
3e326ece
MK		 1584#else
1585 wait_ms(1);
1586#endif
1587
1588 /* free TDs in urb_priv */
48867208 1589 if (!usb_pipeint(pipe))
6f5794a6 1590 urb_free_priv(urb);
3e326ece
MK		 1591 return 0;
1592}
1593
1594/* submit routines called from usb.c */
1595int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1596 int transfer_len)
1597{
1598 info("submit_bulk_msg");
1599 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1600}
1601
1602int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1603 int transfer_len, struct devrequest *setup)
1604{
1605 int maxsize = usb_maxpacket(dev, pipe);
1606
1607 info("submit_control_msg");
1608#ifdef DEBUG
6f5794a6
RB		 1609 pkt_print(NULL, dev, pipe, buffer, transfer_len,
1610 setup, "SUB", usb_pipein(pipe));
3e326ece
MK		 1611#else
1612 wait_ms(1);
1613#endif
1614 if (!maxsize) {
1615 err("submit_control_message: pipesize for pipe %lx is zero",
1616 pipe);
1617 return -1;
1618 }
1619 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1620 gohci.rh.dev = dev;
1621 /* root hub - redirect */
1622 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1623 setup);
1624 }
1625
1626 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1627}
1628
1629int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1630 int transfer_len, int interval)
1631{
1632 info("submit_int_msg");
4dae14ce
ZW		 1633 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,
1634 interval);
3e326ece
MK		 1635}
1636
1637/*-------------------------------------------------------------------------*
1638 * HC functions
1639 *-------------------------------------------------------------------------*/
1640
1641/* reset the HC and BUS */
1642
6f5794a6 1643static int hc_reset(ohci_t *ohci)
3e326ece 1644{
e90fb6af
YT		 1645#ifdef CONFIG_PCI_EHCI_DEVNO
1646 pci_dev_t pdev;
1647#endif
3e326ece
MK		 1648 int timeout = 30;
1649 int smm_timeout = 50; /* 0,5 sec */
1650
1651 dbg("%s\n", __FUNCTION__);
1652
e90fb6af
YT		 1653#ifdef CONFIG_PCI_EHCI_DEVNO
1654 /*
1655 * Some multi-function controllers (e.g. ISP1562) allow root hub
1656 * resetting via EHCI registers only.
1657 */
1658 pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
1659 if (pdev != -1) {
1660 u32 base;
1661 int timeout = 1000;
1662
1663 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
6f5794a6 1664 writel(readl(base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET,
e90fb6af
YT		 1665 base + EHCI_USBCMD_OFF);
1666
1667 while (readl(base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) {
1668 if (timeout-- <= 0) {
1669 printf("USB RootHub reset timed out!");
1670 break;
1671 }
1672 udelay(1);
1673 }
1674 } else
1675 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
1676#endif
6f5794a6
RB		 1677 if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1678 /* SMM owns the HC */
1679 writel(OHCI_OCR, &ohci->regs->cmdstatus);/* request ownership */
3e326ece 1680 info("USB HC TakeOver from SMM");
6f5794a6
RB		 1681 while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1682 wait_ms(10);
3e326ece
MK		 1683 if (--smm_timeout == 0) {
1684 err("USB HC TakeOver failed!");
1685 return -1;
1686 }
1687 }
1688 }
1689
1690 /* Disable HC interrupts */
6f5794a6 1691 writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
3e326ece
MK		 1692
1693 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1694 ohci->slot_name,
1695 readl(&ohci->regs->control));
1696
1697 /* Reset USB (needed by some controllers) */
53e336e9 1698 ohci->hc_control = 0;
6f5794a6 1699 writel(ohci->hc_control, &ohci->regs->control);
3e326ece
MK		 1700
1701 /* HC Reset requires max 10 us delay */
6f5794a6
RB		 1702 writel(OHCI_HCR, &ohci->regs->cmdstatus);
1703 while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
3e326ece
MK		 1704 if (--timeout == 0) {
1705 err("USB HC reset timed out!");
1706 return -1;
1707 }
6f5794a6 1708 udelay(1);
3e326ece
MK		 1709 }
1710 return 0;
1711}
1712
1713/*-------------------------------------------------------------------------*/
1714
1715/* Start an OHCI controller, set the BUS operational
1716 * enable interrupts
1717 * connect the virtual root hub */
1718
6f5794a6 1719static int hc_start(ohci_t *ohci)
3e326ece
MK		 1720{
1721 __u32 mask;
1722 unsigned int fminterval;
1723
1724 ohci->disabled = 1;
1725
1726 /* Tell the controller where the control and bulk lists are
1727 * The lists are empty now. */
1728
6f5794a6
RB		 1729 writel(0, &ohci->regs->ed_controlhead);
1730 writel(0, &ohci->regs->ed_bulkhead);
3e326ece 1731
6f5794a6 1732 writel((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
3e326ece
MK		 1733
1734 fminterval = 0x2edf;
6f5794a6 1735 writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
3e326ece 1736 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
6f5794a6
RB		 1737 writel(fminterval, &ohci->regs->fminterval);
1738 writel(0x628, &ohci->regs->lsthresh);
3e326ece
MK		 1739
1740 /* start controller operations */
1741 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1742 ohci->disabled = 0;
6f5794a6 1743 writel(ohci->hc_control, &ohci->regs->control);
3e326ece
MK		 1744
1745 /* disable all interrupts */
1746 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1747 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1748 OHCI_INTR_OC | OHCI_INTR_MIE);
6f5794a6 1749 writel(mask, &ohci->regs->intrdisable);
3e326ece
MK		 1750 /* clear all interrupts */
1751 mask &= ~OHCI_INTR_MIE;
6f5794a6 1752 writel(mask, &ohci->regs->intrstatus);
3e326ece
MK		 1753 /* Choose the interrupts we care about now - but w/o MIE */
1754 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
6f5794a6 1755 writel(mask, &ohci->regs->intrenable);
3e326ece
MK		 1756
1757#ifdef OHCI_USE_NPS
1758 /* required for AMD-756 and some Mac platforms */
6f5794a6 1759 writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
3e326ece 1760 &ohci->regs->roothub.a);
6f5794a6 1761 writel(RH_HS_LPSC, &ohci->regs->roothub.status);
3e326ece
MK		 1762#endif /* OHCI_USE_NPS */
1763
6f5794a6 1764#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
3e326ece 1765 /* POTPGT delay is bits 24-31, in 2 ms units. */
6f5794a6 1766 mdelay((roothub_a(ohci) >> 23) & 0x1fe);
3e326ece
MK		 1767
1768 /* connect the virtual root hub */
1769 ohci->rh.devnum = 0;
1770
1771 return 0;
1772}
1773
1774/*-------------------------------------------------------------------------*/
1775
4dae14ce
ZW		 1776/* Poll USB interrupt. */
1777void usb_event_poll(void)
1778{
1779 hc_interrupt();
1780}
1781
3e326ece
MK		 1782/* an interrupt happens */
1783
6f5794a6 1784static int hc_interrupt(void)
3e326ece
MK		 1785{
1786 ohci_t *ohci = &gohci;
1787 struct ohci_regs *regs = ohci->regs;
1788 int ints;
1789 int stat = -1;
1790
ddf83a2f 1791 if ((ohci->hcca->done_head != 0) &&
6f5794a6 1792 !(m32_swap(ohci->hcca->done_head) & 0x01)) {
ddf83a2f 1793 ints = OHCI_INTR_WDH;
6f5794a6
RB		 1794 } else {
1795 ints = readl(&regs->intrstatus);
1796 if (ints == ~(u32)0) {
1797 ohci->disabled++;
1798 err("%s device removed!", ohci->slot_name);
1799 return -1;
1800 } else {
1801 ints &= readl(&regs->intrenable);
1802 if (ints == 0) {
1803 dbg("hc_interrupt: returning..\n");
1804 return 0xff;
1805 }
1806 }
ddf83a2f 1807 }
ae79f606 1808
6f5794a6
RB		 1809 /* dbg("Interrupt: %x frame: %x", ints,
1810 le16_to_cpu(ohci->hcca->frame_no)); */
3e326ece 1811
6f5794a6 1812 if (ints & OHCI_INTR_RHSC)
ddf83a2f 1813 stat = 0xff;
3e326ece
MK		 1814
1815 if (ints & OHCI_INTR_UE) {
1816 ohci->disabled++;
6f5794a6 1817 err("OHCI Unrecoverable Error, controller usb-%s disabled",
3e326ece
MK		 1818 ohci->slot_name);
1819 /* e.g. due to PCI Master/Target Abort */
1820
1821#ifdef DEBUG
6f5794a6 1822 ohci_dump(ohci, 1);
3e326ece 1823#else
6f5794a6 1824 wait_ms(1);
3e326ece
MK		 1825#endif
1826 /* FIXME: be optimistic, hope that bug won't repeat often. */
1827 /* Make some non-interrupt context restart the controller. */
1828 /* Count and limit the retries though; either hardware or */
1829 /* software errors can go forever... */
6f5794a6 1830 hc_reset(ohci);
3e326ece
MK		 1831 return -1;
1832 }
1833
1834 if (ints & OHCI_INTR_WDH) {
1835 wait_ms(1);
6f5794a6
RB		 1836 writel(OHCI_INTR_WDH, &regs->intrdisable);
1837 (void)readl(&regs->intrdisable); /* flush */
1838 stat = dl_done_list(&gohci);
1839 writel(OHCI_INTR_WDH, &regs->intrenable);
1840 (void)readl(&regs->intrdisable); /* flush */
3e326ece
MK		 1841 }
1842
1843 if (ints & OHCI_INTR_SO) {
1844 dbg("USB Schedule overrun\n");
6f5794a6 1845 writel(OHCI_INTR_SO, &regs->intrenable);
3e326ece
MK		 1846 stat = -1;
1847 }
1848
1849 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1850 if (ints & OHCI_INTR_SF) {
6f5794a6 1851 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
3e326ece 1852 wait_ms(1);
6f5794a6 1853 writel(OHCI_INTR_SF, &regs->intrdisable);
3e326ece 1854 if (ohci->ed_rm_list[frame] != NULL)
6f5794a6 1855 writel(OHCI_INTR_SF, &regs->intrenable);
3e326ece
MK		 1856 stat = 0xff;
1857 }
1858
6f5794a6 1859 writel(ints, &regs->intrstatus);
3e326ece
MK		 1860 return stat;
1861}
1862
1863/*-------------------------------------------------------------------------*/
1864
1865/*-------------------------------------------------------------------------*/
1866
1867/* De-allocate all resources.. */
1868
6f5794a6 1869static void hc_release_ohci(ohci_t *ohci)
3e326ece 1870{
6f5794a6 1871 dbg("USB HC release ohci usb-%s", ohci->slot_name);
3e326ece
MK		 1872
1873 if (!ohci->disabled)
6f5794a6 1874 hc_reset(ohci);
3e326ece
MK		 1875}
1876
1877/*-------------------------------------------------------------------------*/
1878
1879/*
1880 * low level initalisation routine, called from usb.c
1881 */
1882static char ohci_inited = 0;
1883
1884int usb_lowlevel_init(void)
1885{
4dae14ce
ZW		 1886#ifdef CONFIG_PCI_OHCI
1887 pci_dev_t pdev;
1888#endif
24e37645 1889
6d0f6bcf 1890#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
24e37645 1891 /* cpu dependant init */
6f5794a6 1892 if (usb_cpu_init())
3e326ece 1893 return -1;
24e37645 1894#endif
3e326ece 1895
6d0f6bcf 1896#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
24e37645 1897 /* board dependant init */
6f5794a6 1898 if (usb_board_init())
24e37645
MK		 1899 return -1;
1900#endif
6f5794a6 1901 memset(&gohci, 0, sizeof(ohci_t));
3e326ece
MK		 1902
1903 /* align the storage */
1904 if ((__u32)&ghcca[0] & 0xff) {
1905 err("HCCA not aligned!!");
1906 return -1;
1907 }
1908 phcca = &ghcca[0];
1909 info("aligned ghcca %p", phcca);
1910 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1911 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1912 err("EDs not aligned!!");
1913 return -1;
1914 }
1915 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1916 if ((__u32)gtd & 0x7) {
1917 err("TDs not aligned!!");
1918 return -1;
1919 }
1920 ptd = gtd;
1921 gohci.hcca = phcca;
6f5794a6 1922 memset(phcca, 0, sizeof(struct ohci_hcca));
3e326ece
MK		 1923
1924 gohci.disabled = 1;
1925 gohci.sleeping = 0;
1926 gohci.irq = -1;
4dae14ce 1927#ifdef CONFIG_PCI_OHCI
477434c6 1928 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
4dae14ce
ZW		 1929
1930 if (pdev != -1) {
1931 u16 vid, did;
1932 u32 base;
1933 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
1934 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
1935 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
1936 vid, did, (pdev >> 16) & 0xff,
1937 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
1938 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1939 printf("OHCI regs address 0x%08x\n", base);
1940 gohci.regs = (struct ohci_regs *)base;
1941 } else
1942 return -1;
1943#else
6d0f6bcf 1944 gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
4dae14ce 1945#endif
3e326ece
MK		 1946
1947 gohci.flags = 0;
6d0f6bcf 1948 gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
3e326ece
MK		 1949
1950 if (hc_reset (&gohci) < 0) {
1951 hc_release_ohci (&gohci);
1952 err ("can't reset usb-%s", gohci.slot_name);
6d0f6bcf 1953#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
24e37645 1954 /* board dependant cleanup */
ddf83a2f 1955 usb_board_init_fail();
24e37645
MK		 1956#endif
1957
6d0f6bcf 1958#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
24e37645 1959 /* cpu dependant cleanup */
ddf83a2f 1960 usb_cpu_init_fail();
24e37645 1961#endif
3e326ece
MK		 1962 return -1;
1963 }
1964
6f5794a6
RB		 1965 if (hc_start(&gohci) < 0) {
1966 err("can't start usb-%s", gohci.slot_name);
1967 hc_release_ohci(&gohci);
3e326ece 1968 /* Initialization failed */
6d0f6bcf 1969#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
24e37645
MK		 1970 /* board dependant cleanup */
1971 usb_board_stop();
1972#endif
1973
6d0f6bcf 1974#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
24e37645
MK		 1975 /* cpu dependant cleanup */
1976 usb_cpu_stop();
1977#endif
3e326ece
MK		 1978 return -1;
1979 }
1980
1981#ifdef DEBUG
6f5794a6 1982 ohci_dump(&gohci, 1);
3e326ece
MK		 1983#else
1984 wait_ms(1);
1985#endif
1986 ohci_inited = 1;
1987 return 0;
1988}
1989
1990int usb_lowlevel_stop(void)
1991{
1992 /* this gets called really early - before the controller has */
1993 /* even been initialized! */
1994 if (!ohci_inited)
1995 return 0;
1996 /* TODO release any interrupts, etc. */
1997 /* call hc_release_ohci() here ? */
6f5794a6 1998 hc_reset(&gohci);
3e326ece 1999
6d0f6bcf 2000#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
3e326ece 2001 /* board dependant cleanup */
6f5794a6 2002 if (usb_board_stop())
3e326ece 2003 return -1;
24e37645
MK		 2004#endif
2005
6d0f6bcf 2006#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
24e37645 2007 /* cpu dependant cleanup */
6f5794a6 2008 if (usb_cpu_stop())
24e37645
MK		 2009 return -1;
2010#endif
eba1f2fc
RB		 2011 /* This driver is no longer initialised. It needs a new low-level
2012 * init (board/cpu) before it can be used again. */
2013 ohci_inited = 0;
3e326ece
MK		 2014 return 0;
2015}
"Das U-Boot" Source Tree