[people/ms/u-boot.git] / drivers / usb / host / xhci-rockchip.c

/*
 * Copyright (c) 2016 Rockchip, Inc.
 * Authors: Daniel Meng <daniel.meng@rock-chips.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <usb.h>
#include <watchdog.h>
#include <linux/errno.h>
#include <linux/compat.h>
#include <linux/usb/dwc3.h>
#include <power/regulator.h>

#include "xhci.h"

DECLARE_GLOBAL_DATA_PTR;

struct rockchip_xhci_platdata {
	fdt_addr_t hcd_base;
	fdt_addr_t phy_base;
	struct udevice *vbus_supply;
};

/*
 * Contains pointers to register base addresses
 * for the usb controller.
 */
struct rockchip_xhci {
	struct usb_platdata usb_plat;
	struct xhci_ctrl ctrl;
	struct xhci_hccr *hcd;
	struct dwc3 *dwc3_reg;
};

static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
{
	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
	struct udevice *child;
	int ret = 0;

	/*
	 * Get the base address for XHCI controller from the device node
	 */
	plat->hcd_base = dev_read_addr(dev);
	if (plat->hcd_base == FDT_ADDR_T_NONE) {
		pr_err("Can't get the XHCI register base address\n");
		return -ENXIO;
	}

	/* Get the base address for usbphy from the device node */
	for (device_find_first_child(dev, &child); child;
	     device_find_next_child(&child)) {
		if (!device_is_compatible(child, "rockchip,rk3399-usb3-phy"))
			continue;
		plat->phy_base = devfdt_get_addr(child);
		break;
	}

	if (plat->phy_base == FDT_ADDR_T_NONE) {
		pr_err("Can't get the usbphy register address\n");
		return -ENXIO;
	}

	/* Vbus regulator */
	ret = device_get_supply_regulator(dev, "vbus-supply",
					  &plat->vbus_supply);
	if (ret)
		debug("Can't get VBus regulator!\n");

	return 0;
}

/*
 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
 * @dwc: Pointer to our controller context structure
 * @dev: Pointer to ulcass device
 */
static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
				    struct udevice *dev)
{
	u32 reg;
	u32 utmi_bits;

	/* Set dwc3 usb2 phy config */
	reg = readl(&dwc3_reg->g_usb2phycfg[0]);

	if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;

	utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
	if (utmi_bits == 16) {
		reg |= DWC3_GUSB2PHYCFG_PHYIF;
		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
	} else if (utmi_bits == 8) {
		reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
	}

	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;

	if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;

	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
}

static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
				   struct udevice *dev)
{
	int ret;

	ret = dwc3_core_init(rkxhci->dwc3_reg);
	if (ret) {
		pr_err("failed to initialize core\n");
		return ret;
	}

	rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);

	/* We are hard-coding DWC3 core to Host Mode */
	dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);

	return 0;
}

static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
{
	return 0;
}

static int xhci_usb_probe(struct udevice *dev)
{
	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
	struct rockchip_xhci *ctx = dev_get_priv(dev);
	struct xhci_hcor *hcor;
	int ret;

	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
	hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
			HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));

	if (plat->vbus_supply) {
		ret = regulator_set_enable(plat->vbus_supply, true);
		if (ret) {
			pr_err("XHCI: failed to set VBus supply\n");
			return ret;
		}
	}

	ret = rockchip_xhci_core_init(ctx, dev);
	if (ret) {
		pr_err("XHCI: failed to initialize controller\n");
		return ret;
	}

	return xhci_register(dev, ctx->hcd, hcor);
}

static int xhci_usb_remove(struct udevice *dev)
{
	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
	struct rockchip_xhci *ctx = dev_get_priv(dev);
	int ret;

	ret = xhci_deregister(dev);
	if (ret)
		return ret;
	ret = rockchip_xhci_core_exit(ctx);
	if (ret)
		return ret;

	if (plat->vbus_supply) {
		ret = regulator_set_enable(plat->vbus_supply, false);
		if (ret)
			pr_err("XHCI: failed to set VBus supply\n");
	}

	return ret;
}

static const struct udevice_id xhci_usb_ids[] = {
	{ .compatible = "rockchip,rk3399-xhci" },
	{ .compatible = "rockchip,rk3328-xhci" },
	{ }
};

U_BOOT_DRIVER(usb_xhci) = {
	.name	= "xhci_rockchip",
	.id	= UCLASS_USB,
	.of_match = xhci_usb_ids,
	.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
	.probe = xhci_usb_probe,
	.remove = xhci_usb_remove,
	.ops	= &xhci_usb_ops,
	.bind	= dm_scan_fdt_dev,
	.platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
	.priv_auto_alloc_size = sizeof(struct rockchip_xhci),
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};

static const struct udevice_id usb_phy_ids[] = {
	{ .compatible = "rockchip,rk3399-usb3-phy" },
	{ .compatible = "rockchip,rk3328-usb3-phy" },
	{ }
};

U_BOOT_DRIVER(usb_phy) = {
	.name = "usb_phy_rockchip",
	.of_match = usb_phy_ids,
};
Commit	Line	Data
b44566c4 M	1	/*
	2	* Copyright (c) 2016 Rockchip, Inc.
	3	* Authors: Daniel Meng <daniel.meng@rock-chips.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7	#include <common.h>
	8	#include <dm.h>
b44566c4 M	9	#include <malloc.h>
	10	#include <usb.h>
	11	#include <watchdog.h>
5d97dff0	12	#include <linux/errno.h>
b44566c4 M	13	#include <linux/compat.h>
b44566c4 M	14	#include <linux/usb/dwc3.h>
d3cb14b9	15	#include <power/regulator.h>
b44566c4 M	16
	17	#include "xhci.h"
	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
	21	struct rockchip_xhci_platdata {
	22	fdt_addr_t hcd_base;
	23	fdt_addr_t phy_base;
d3cb14b9	24	struct udevice *vbus_supply;
b44566c4 M	25	};
	26
	27	/*
	28	* Contains pointers to register base addresses
	29	* for the usb controller.
	30	*/
	31	struct rockchip_xhci {
	32	struct usb_platdata usb_plat;
	33	struct xhci_ctrl ctrl;
	34	struct xhci_hccr *hcd;
	35	struct dwc3 *dwc3_reg;
	36	};
	37
	38	static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
	39	{
	40	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
	41	struct udevice *child;
	42	int ret = 0;
	43
	44	/*
	45	* Get the base address for XHCI controller from the device node
	46	*/
32c8eee3	47	plat->hcd_base = dev_read_addr(dev);
b44566c4	48	if (plat->hcd_base == FDT_ADDR_T_NONE) {
9b643e31	49	pr_err("Can't get the XHCI register base address\n");
b44566c4 M	50	return -ENXIO;
	51	}
	52
	53	/* Get the base address for usbphy from the device node */
	54	for (device_find_first_child(dev, &child); child;
	55	device_find_next_child(&child)) {
911f3aef	56	if (!device_is_compatible(child, "rockchip,rk3399-usb3-phy"))
b44566c4	57	continue;
a821c4af	58	plat->phy_base = devfdt_get_addr(child);
b44566c4 M	59	break;
	60	}
	61
	62	if (plat->phy_base == FDT_ADDR_T_NONE) {
9b643e31	63	pr_err("Can't get the usbphy register address\n");
b44566c4 M	64	return -ENXIO;
	65	}
	66
d3cb14b9 MD	67	/* Vbus regulator */
	68	ret = device_get_supply_regulator(dev, "vbus-supply",
	69	&plat->vbus_supply);
b44566c4	70	if (ret)
26a8b80f	71	debug("Can't get VBus regulator!\n");
b44566c4 M	72
	73	return 0;
	74	}
	75
	76	/*
	77	* rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
	78	* @dwc: Pointer to our controller context structure
	79	* @dev: Pointer to ulcass device
	80	*/
	81	static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
	82	struct udevice *dev)
	83	{
	84	u32 reg;
b44566c4 M	85	u32 utmi_bits;
	86
	87	/* Set dwc3 usb2 phy config */
	88	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
	89
f2708c97	90	if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
b44566c4 M	91	reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
b44566c4 M	92
f2708c97	93	utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
b44566c4 M	94	if (utmi_bits == 16) {
	95	reg \|= DWC3_GUSB2PHYCFG_PHYIF;
	96	reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
	97	reg \|= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
	98	} else if (utmi_bits == 8) {
	99	reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
	100	reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
	101	reg \|= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
	102	}
	103
f2708c97	104	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
b44566c4 M	105	reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
b44566c4 M	106
f2708c97	107	if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
b44566c4 M	108	reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
	109
	110	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
	111	}
	112
	113	static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
	114	struct udevice *dev)
	115	{
	116	int ret;
	117
	118	ret = dwc3_core_init(rkxhci->dwc3_reg);
	119	if (ret) {
9b643e31	120	pr_err("failed to initialize core\n");
b44566c4 M	121	return ret;
	122	}
	123
	124	rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
	125
	126	/* We are hard-coding DWC3 core to Host Mode */
	127	dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
	128
	129	return 0;
	130	}
	131
	132	static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
	133	{
	134	return 0;
	135	}
	136
	137	static int xhci_usb_probe(struct udevice *dev)
	138	{
	139	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
	140	struct rockchip_xhci *ctx = dev_get_priv(dev);
	141	struct xhci_hcor *hcor;
	142	int ret;
	143
	144	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
	145	ctx->dwc3_reg = (struct dwc3 )((char )(ctx->hcd) + DWC3_REG_OFFSET);
	146	hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
	147	HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
	148
26a8b80f MD	149	if (plat->vbus_supply) {
	150	ret = regulator_set_enable(plat->vbus_supply, true);
	151	if (ret) {
9b643e31	152	pr_err("XHCI: failed to set VBus supply\n");
26a8b80f MD	153	return ret;
	154	}
	155	}
b44566c4 M	156
	157	ret = rockchip_xhci_core_init(ctx, dev);
	158	if (ret) {
9b643e31	159	pr_err("XHCI: failed to initialize controller\n");
b44566c4 M	160	return ret;
	161	}
	162
	163	return xhci_register(dev, ctx->hcd, hcor);
	164	}
	165
	166	static int xhci_usb_remove(struct udevice *dev)
	167	{
d3cb14b9	168	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
b44566c4 M	169	struct rockchip_xhci *ctx = dev_get_priv(dev);
	170	int ret;
	171
	172	ret = xhci_deregister(dev);
	173	if (ret)
	174	return ret;
	175	ret = rockchip_xhci_core_exit(ctx);
	176	if (ret)
	177	return ret;
	178
26a8b80f MD	179	if (plat->vbus_supply) {
	180	ret = regulator_set_enable(plat->vbus_supply, false);
	181	if (ret)
9b643e31	182	pr_err("XHCI: failed to set VBus supply\n");
26a8b80f	183	}
d3cb14b9	184
26a8b80f	185	return ret;
b44566c4 M	186	}
	187
	188	static const struct udevice_id xhci_usb_ids[] = {
	189	{ .compatible = "rockchip,rk3399-xhci" },
d3cb14b9	190	{ .compatible = "rockchip,rk3328-xhci" },
b44566c4 M	191	{ }
	192	};
	193
	194	U_BOOT_DRIVER(usb_xhci) = {
	195	.name = "xhci_rockchip",
	196	.id = UCLASS_USB,
	197	.of_match = xhci_usb_ids,
	198	.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
	199	.probe = xhci_usb_probe,
	200	.remove = xhci_usb_remove,
	201	.ops = &xhci_usb_ops,
	202	.bind = dm_scan_fdt_dev,
	203	.platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
	204	.priv_auto_alloc_size = sizeof(struct rockchip_xhci),
	205	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	206	};
	207
	208	static const struct udevice_id usb_phy_ids[] = {
	209	{ .compatible = "rockchip,rk3399-usb3-phy" },
d3cb14b9	210	{ .compatible = "rockchip,rk3328-usb3-phy" },
b44566c4 M	211	{ }
	212	};
	213
	214	U_BOOT_DRIVER(usb_phy) = {
	215	.name = "usb_phy_rockchip",
	216	.of_match = usb_phy_ids,
	217	};