[people/ms/u-boot.git] / drivers / video / rockchip / rk_vop.c

/*
 * Copyright (c) 2015 Google, Inc
 * Copyright 2014 Rockchip Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <edid.h>
#include <regmap.h>
#include <syscon.h>
#include <video.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3288.h>
#include <asm/arch/grf_rk3288.h>
#include <asm/arch/edp_rk3288.h>
#include <asm/arch/vop_rk3288.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <power/regulator.h>

DECLARE_GLOBAL_DATA_PTR;

struct rk_vop_priv {
	struct rk3288_vop *regs;
	struct rk3288_grf *grf;
};

void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
		  int fb_bits_per_pixel, const struct display_timing *edid)
{
	u32 lb_mode;
	u32 rgb_mode;
	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;

	writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
	       &regs->win0_act_info);

	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
	       V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
	       &regs->win0_dsp_st);

	writel(V_DSP_WIDTH(hactive - 1) |
		V_DSP_HEIGHT(vactive - 1),
		&regs->win0_dsp_info);

	clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
			V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));

	switch (fb_bits_per_pixel) {
	case 16:
		rgb_mode = RGB565;
		writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	case 24:
		rgb_mode = RGB888;
		writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	case 32:
	default:
		rgb_mode = ARGB8888;
		writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	}

	if (hactive > 2560)
		lb_mode = LB_RGB_3840X2;
	else if (hactive > 1920)
		lb_mode = LB_RGB_2560X4;
	else if (hactive > 1280)
		lb_mode = LB_RGB_1920X5;
	else
		lb_mode = LB_RGB_1280X8;

	clrsetbits_le32(&regs->win0_ctrl0,
			M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
			V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
			V_WIN0_EN(1));

	writel(fbbase, &regs->win0_yrgb_mst);
	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
}

void rkvop_mode_set(struct rk3288_vop *regs,
		    const struct display_timing *edid, enum vop_modes mode)
{
	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;
	u32 hsync_len = edid->hsync_len.typ;
	u32 hback_porch = edid->hback_porch.typ;
	u32 vsync_len = edid->vsync_len.typ;
	u32 vback_porch = edid->vback_porch.typ;
	u32 hfront_porch = edid->hfront_porch.typ;
	u32 vfront_porch = edid->vfront_porch.typ;
	uint flags;
	int mode_flags;

	switch (mode) {
	case VOP_MODE_HDMI:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_HDMI_OUT_EN(1));
		break;
	case VOP_MODE_EDP:
	default:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_EDP_OUT_EN(1));
		break;
	case VOP_MODE_LVDS:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_RGB_OUT_EN(1));
		break;
	case VOP_MODE_MIPI:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_MIPI_OUT_EN(1));
		 break;
	}

	if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
		/* RGBaaa */
		mode_flags = 15;
	else
		/* RGB888 */
		mode_flags = 0;

	flags = V_DSP_OUT_MODE(mode_flags) |
		V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) |
		V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH));

	clrsetbits_le32(&regs->dsp_ctrl0,
			M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
			flags);

	writel(V_HSYNC(hsync_len) |
	       V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
			&regs->dsp_htotal_hs_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &regs->dsp_hact_st_end);

	writel(V_VSYNC(vsync_len) |
	       V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
	       &regs->dsp_vtotal_vs_end);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &regs->dsp_vact_st_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &regs->post_dsp_hact_info);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &regs->post_dsp_vact_info);

	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
}

/**
 * rk_display_init() - Try to enable the given display device
 *
 * This function performs many steps:
 * - Finds the display device being referenced by @ep_node
 * - Puts the VOP's ID into its uclass platform data
 * - Probes the device to set it up
 * - Reads the EDID timing information
 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
 * - Enables the display (the display device handles this and will do different
 *     things depending on the display type)
 * - Tells the uclass about the display resolution so that the console will
 *     appear correctly
 *
 * @dev:	VOP device that we want to connect to the display
 * @fbbase:	Frame buffer address
 * @l2bpp	Log2 of bits-per-pixels for the display
 * @ep_node:	Device tree node to process - this is the offset of an endpoint
 *		node within the VOP's 'port' list.
 * @return 0 if OK, -ve if something went wrong
 */
int rk_display_init(struct udevice *dev, ulong fbbase,
		    enum video_log2_bpp l2bpp, int ep_node)
{
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	const void *blob = gd->fdt_blob;
	struct rk_vop_priv *priv = dev_get_priv(dev);
	int vop_id, remote_vop_id;
	struct rk3288_vop *regs = priv->regs;
	struct display_timing timing;
	struct udevice *disp;
	int ret, remote, i, offset;
	struct display_plat *disp_uc_plat;
	struct clk clk;

	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
	debug("vop_id=%d\n", vop_id);
	remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
	if (remote < 0)
		return -EINVAL;
	remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
	debug("remote vop_id=%d\n", remote_vop_id);

	for (i = 0, offset = remote; i < 3 && offset > 0; i++)
		offset = fdt_parent_offset(blob, offset);
	if (offset < 0) {
		debug("%s: Invalid remote-endpoint position\n", dev->name);
		return -EINVAL;
	}

	ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
	if (ret) {
		debug("%s: device '%s' display not found (ret=%d)\n", __func__,
		      dev->name, ret);
		return ret;
	}

	disp_uc_plat = dev_get_uclass_platdata(disp);
	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
	if (display_in_use(disp)) {
		debug("   - device in use\n");
		return -EBUSY;
	}

	disp_uc_plat->source_id = remote_vop_id;
	disp_uc_plat->src_dev = dev;

	ret = device_probe(disp);
	if (ret) {
		debug("%s: device '%s' display won't probe (ret=%d)\n",
		      __func__, dev->name, ret);
		return ret;
	}

	ret = display_read_timing(disp, &timing);
	if (ret) {
		debug("%s: Failed to read timings\n", __func__);
		return ret;
	}

	ret = clk_get_by_index(dev, 1, &clk);
	if (!ret)
		ret = clk_set_rate(&clk, timing.pixelclock.typ);
	if (IS_ERR_VALUE(ret)) {
		debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
		return ret;
	}

	rkvop_mode_set(regs, &timing, vop_id);

	rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);

	ret = display_enable(disp, 1 << l2bpp, &timing);
	if (ret)
		return ret;

	uc_priv->xsize = timing.hactive.typ;
	uc_priv->ysize = timing.vactive.typ;
	uc_priv->bpix = l2bpp;
	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);

	return 0;
}

static int rk_vop_probe(struct udevice *dev)
{
	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	const void *blob = gd->fdt_blob;
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct udevice *reg;
	int ret, port, node;

	/* Before relocation we don't need to do anything */
	if (!(gd->flags & GD_FLG_RELOC))
		return 0;

	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	priv->regs = (struct rk3288_vop *)dev_get_addr(dev);

	/* lcdc(vop) iodomain select 1.8V */
	rk_setreg(&priv->grf->io_vsel, 1 << 0);

	/*
	 * Try some common regulators. We should really get these from the
	 * device tree somehow.
	 */
	ret = regulator_autoset_by_name("vcc18_lcd", &reg);
	if (ret)
		debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__);
	ret = regulator_autoset_by_name("VCC18_LCD", &reg);
	if (ret)
		debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__);
	ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", &reg);
	if (ret) {
		debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n",
		      __func__);
	}
	ret = regulator_autoset_by_name("vdd10_lcd", &reg);
	if (ret) {
		debug("%s: Cannot autoset regulator vdd10_lcd\n",
		      __func__);
	}
	ret = regulator_autoset_by_name("VDD10_LCD", &reg);
	if (ret) {
		debug("%s: Cannot autoset regulator VDD10_LCD\n",
		      __func__);
	}
	ret = regulator_autoset_by_name("vcc33_lcd", &reg);
	if (ret)
		debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__);

	/*
	 * Try all the ports until we find one that works. In practice this
	 * tries EDP first if available, then HDMI.
	 *
	 * Note that rockchip_vop_set_clk() always uses NPLL as the source
	 * clock so it is currently not possible to use more than one display
	 * device simultaneously.
	 */
	port = fdt_subnode_offset(blob, dev_of_offset(dev), "port");
	if (port < 0)
		return -EINVAL;
	for (node = fdt_first_subnode(blob, port);
	     node > 0;
	     node = fdt_next_subnode(blob, node)) {
		ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
		if (ret)
			debug("Device failed: ret=%d\n", ret);
		if (!ret)
			break;
	}
	video_set_flush_dcache(dev, 1);

	return ret;
}

static int rk_vop_bind(struct udevice *dev)
{
	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);

	plat->size = 1920 * 1080 * 2;

	return 0;
}

static const struct video_ops rk_vop_ops = {
};

static const struct udevice_id rk_vop_ids[] = {
	{ .compatible = "rockchip,rk3399-vop-big" },
	{ .compatible = "rockchip,rk3399-vop-lit" },
	{ .compatible = "rockchip,rk3288-vop" },
	{ }
};

U_BOOT_DRIVER(rk_vop) = {
	.name	= "rk_vop",
	.id	= UCLASS_VIDEO,
	.of_match = rk_vop_ids,
	.ops	= &rk_vop_ops,
	.bind	= rk_vop_bind,
	.probe	= rk_vop_probe,
	.priv_auto_alloc_size	= sizeof(struct rk_vop_priv),
};
Commit	Line	Data
7b7ad5c3 SG	1	/*
	2	* Copyright (c) 2015 Google, Inc
	3	* Copyright 2014 Rockchip Inc.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <clk.h>
	10	#include <display.h>
	11	#include <dm.h>
	12	#include <edid.h>
	13	#include <regmap.h>
	14	#include <syscon.h>
	15	#include <video.h>
	16	#include <asm/gpio.h>
	17	#include <asm/hardware.h>
	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/cru_rk3288.h>
	21	#include <asm/arch/grf_rk3288.h>
	22	#include <asm/arch/edp_rk3288.h>
7b7ad5c3 SG	23	#include <asm/arch/vop_rk3288.h>
	24	#include <dm/device-internal.h>
	25	#include <dm/uclass-internal.h>
	26	#include <dt-bindings/clock/rk3288-cru.h>
	27	#include <power/regulator.h>
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	struct rk_vop_priv {
	32	struct rk3288_vop *regs;
	33	struct rk3288_grf *grf;
	34	};
	35
	36	void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
	37	int fb_bits_per_pixel, const struct display_timing *edid)
	38	{
	39	u32 lb_mode;
	40	u32 rgb_mode;
	41	u32 hactive = edid->hactive.typ;
	42	u32 vactive = edid->vactive.typ;
	43
	44	writel(V_ACT_WIDTH(hactive - 1) \| V_ACT_HEIGHT(vactive - 1),
	45	&regs->win0_act_info);
	46
	47	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) \|
	48	V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
	49	&regs->win0_dsp_st);
	50
	51	writel(V_DSP_WIDTH(hactive - 1) \|
	52	V_DSP_HEIGHT(vactive - 1),
	53	&regs->win0_dsp_info);
	54
	55	clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN \| M_WIN0_KEY_COLOR,
	56	V_WIN0_KEY_EN(0) \| V_WIN0_KEY_COLOR(0));
	57
	58	switch (fb_bits_per_pixel) {
	59	case 16:
	60	rgb_mode = RGB565;
	61	writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
	62	break;
	63	case 24:
	64	rgb_mode = RGB888;
	65	writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
	66	break;
	67	case 32:
	68	default:
	69	rgb_mode = ARGB8888;
	70	writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
	71	break;
	72	}
	73
	74	if (hactive > 2560)
	75	lb_mode = LB_RGB_3840X2;
	76	else if (hactive > 1920)
	77	lb_mode = LB_RGB_2560X4;
	78	else if (hactive > 1280)
	79	lb_mode = LB_RGB_1920X5;
	80	else
	81	lb_mode = LB_RGB_1280X8;
	82
	83	clrsetbits_le32(&regs->win0_ctrl0,
	84	M_WIN0_LB_MODE \| M_WIN0_DATA_FMT \| M_WIN0_EN,
	85	V_WIN0_LB_MODE(lb_mode) \| V_WIN0_DATA_FMT(rgb_mode) \|
	86	V_WIN0_EN(1));
87
88	writel(fbbase, &regs->win0_yrgb_mst);
89	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
90	}
91
92	void rkvop_mode_set(struct rk3288_vop *regs,
93	const struct display_timing *edid, enum vop_modes mode)
94	{
95	u32 hactive = edid->hactive.typ;
96	u32 vactive = edid->vactive.typ;
97	u32 hsync_len = edid->hsync_len.typ;
98	u32 hback_porch = edid->hback_porch.typ;
99	u32 vsync_len = edid->vsync_len.typ;
100	u32 vback_porch = edid->vback_porch.typ;
101	u32 hfront_porch = edid->hfront_porch.typ;
102	u32 vfront_porch = edid->vfront_porch.typ;
103	uint flags;
85307835	104	int mode_flags;
7b7ad5c3 SG	105
	106	switch (mode) {
	107	case VOP_MODE_HDMI:
	108	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	109	V_HDMI_OUT_EN(1));
	110	break;
	111	case VOP_MODE_EDP:
	112	default:
	113	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	114	V_EDP_OUT_EN(1));
	115	break;
85307835 JC	116	case VOP_MODE_LVDS:
	117	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	118	V_RGB_OUT_EN(1));
	119	break;
9f819931 EG	120	case VOP_MODE_MIPI:
	121	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	122	V_MIPI_OUT_EN(1));
	123	break;
7b7ad5c3 SG	124	}
7b7ad5c3 SG	125
85307835 JC	126	if (mode == VOP_MODE_HDMI \|\| mode == VOP_MODE_EDP)
	127	/* RGBaaa */
	128	mode_flags = 15;
	129	else
	130	/* RGB888 */
	131	mode_flags = 0;
	132
	133	flags = V_DSP_OUT_MODE(mode_flags) \|
7b7ad5c3 SG	134	V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) \|
	135	V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH));
	136
	137	clrsetbits_le32(&regs->dsp_ctrl0,
	138	M_DSP_OUT_MODE \| M_DSP_VSYNC_POL \| M_DSP_HSYNC_POL,
	139	flags);
	140
	141	writel(V_HSYNC(hsync_len) \|
	142	V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
	143	&regs->dsp_htotal_hs_end);
	144
	145	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	146	V_HASP(hsync_len + hback_porch),
	147	&regs->dsp_hact_st_end);
	148
	149	writel(V_VSYNC(vsync_len) \|
	150	V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
	151	&regs->dsp_vtotal_vs_end);
	152
	153	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	154	V_VASP(vsync_len + vback_porch),
	155	&regs->dsp_vact_st_end);
	156
	157	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	158	V_HASP(hsync_len + hback_porch),
	159	&regs->post_dsp_hact_info);
	160
	161	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	162	V_VASP(vsync_len + vback_porch),
	163	&regs->post_dsp_vact_info);
	164
	165	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
	166	}
	167
	168	/**
	169	* rk_display_init() - Try to enable the given display device
	170	*
	171	* This function performs many steps:
	172	* - Finds the display device being referenced by @ep_node
	173	* - Puts the VOP's ID into its uclass platform data
	174	* - Probes the device to set it up
	175	* - Reads the EDID timing information
	176	* - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
	177	* - Enables the display (the display device handles this and will do different
	178	* things depending on the display type)
	179	* - Tells the uclass about the display resolution so that the console will
	180	* appear correctly
	181	*
	182	* @dev: VOP device that we want to connect to the display
	183	* @fbbase: Frame buffer address
	184	* @l2bpp Log2 of bits-per-pixels for the display
	185	* @ep_node: Device tree node to process - this is the offset of an endpoint
	186	* node within the VOP's 'port' list.
	187	* @return 0 if OK, -ve if something went wrong
	188	*/
	189	int rk_display_init(struct udevice *dev, ulong fbbase,
	190	enum video_log2_bpp l2bpp, int ep_node)
	191	{
	192	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	193	const void *blob = gd->fdt_blob;
	194	struct rk_vop_priv *priv = dev_get_priv(dev);
	195	int vop_id, remote_vop_id;
	196	struct rk3288_vop *regs = priv->regs;
	197	struct display_timing timing;
198	struct udevice *disp;
199	int ret, remote, i, offset;
200	struct display_plat *disp_uc_plat;
135aa950	201	struct clk clk;
7b7ad5c3 SG	202
	203	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
	204	debug("vop_id=%d\n", vop_id);
	205	remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
	206	if (remote < 0)
	207	return -EINVAL;
	208	remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
	209	debug("remote vop_id=%d\n", remote_vop_id);
	210
	211	for (i = 0, offset = remote; i < 3 && offset > 0; i++)
	212	offset = fdt_parent_offset(blob, offset);
	213	if (offset < 0) {
	214	debug("%s: Invalid remote-endpoint position\n", dev->name);
	215	return -EINVAL;
	216	}
	217
	218	ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
	219	if (ret) {
	220	debug("%s: device '%s' display not found (ret=%d)\n", __func__,
	221	dev->name, ret);
	222	return ret;
	223	}
	224
	225	disp_uc_plat = dev_get_uclass_platdata(disp);
	226	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
987a404a SG	227	if (display_in_use(disp)) {
	228	debug(" - device in use\n");
	229	return -EBUSY;
	230	}
	231
7b7ad5c3 SG	232	disp_uc_plat->source_id = remote_vop_id;
	233	disp_uc_plat->src_dev = dev;
	234
	235	ret = device_probe(disp);
	236	if (ret) {
	237	debug("%s: device '%s' display won't probe (ret=%d)\n",
	238	__func__, dev->name, ret);
	239	return ret;
	240	}
	241
	242	ret = display_read_timing(disp, &timing);
	243	if (ret) {
	244	debug("%s: Failed to read timings\n", __func__);
	245	return ret;
	246	}
	247
9ed68260	248	ret = clk_get_by_index(dev, 1, &clk);
135aa950 SW	249	if (!ret)
135aa950 SW	250	ret = clk_set_rate(&clk, timing.pixelclock.typ);
e07e5bde	251	if (IS_ERR_VALUE(ret)) {
7b7ad5c3 SG	252	debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
	253	return ret;
	254	}
	255
	256	rkvop_mode_set(regs, &timing, vop_id);
	257
	258	rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
	259
	260	ret = display_enable(disp, 1 << l2bpp, &timing);
	261	if (ret)
	262	return ret;
	263
	264	uc_priv->xsize = timing.hactive.typ;
	265	uc_priv->ysize = timing.vactive.typ;
	266	uc_priv->bpix = l2bpp;
	267	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
	268
	269	return 0;
	270	}
	271
	272	static int rk_vop_probe(struct udevice *dev)
	273	{
	274	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	275	const void *blob = gd->fdt_blob;
	276	struct rk_vop_priv *priv = dev_get_priv(dev);
	277	struct udevice *reg;
	278	int ret, port, node;
	279
	280	/* Before relocation we don't need to do anything */
	281	if (!(gd->flags & GD_FLG_RELOC))
	282	return 0;
	283
	284	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	285	priv->regs = (struct rk3288_vop *)dev_get_addr(dev);
	286
	287	/* lcdc(vop) iodomain select 1.8V */
	288	rk_setreg(&priv->grf->io_vsel, 1 << 0);
	289
	290	/*
	291	* Try some common regulators. We should really get these from the
	292	* device tree somehow.
	293	*/
	294	ret = regulator_autoset_by_name("vcc18_lcd", &reg);
	295	if (ret)
	296	debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__);
	297	ret = regulator_autoset_by_name("VCC18_LCD", &reg);
	298	if (ret)
	299	debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__);
	300	ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", &reg);
	301	if (ret) {
	302	debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n",
	303	__func__);
	304	}
	305	ret = regulator_autoset_by_name("vdd10_lcd", &reg);
	306	if (ret) {
	307	debug("%s: Cannot autoset regulator vdd10_lcd\n",
	308	__func__);
	309	}
	310	ret = regulator_autoset_by_name("VDD10_LCD", &reg);
	311	if (ret) {
	312	debug("%s: Cannot autoset regulator VDD10_LCD\n",
	313	__func__);
	314	}
	315	ret = regulator_autoset_by_name("vcc33_lcd", &reg);
316	if (ret)
317	debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__);
318
319	/*
320	* Try all the ports until we find one that works. In practice this
321	* tries EDP first if available, then HDMI.
987a404a SG	322	*
	323	* Note that rockchip_vop_set_clk() always uses NPLL as the source
	324	* clock so it is currently not possible to use more than one display
	325	* device simultaneously.
7b7ad5c3	326	*/
e160f7d4	327	port = fdt_subnode_offset(blob, dev_of_offset(dev), "port");
7b7ad5c3 SG	328	if (port < 0)
	329	return -EINVAL;
	330	for (node = fdt_first_subnode(blob, port);
	331	node > 0;
	332	node = fdt_next_subnode(blob, node)) {
	333	ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
	334	if (ret)
	335	debug("Device failed: ret=%d\n", ret);
	336	if (!ret)
	337	break;
	338	}
b55e04a0	339	video_set_flush_dcache(dev, 1);
7b7ad5c3 SG	340
	341	return ret;
	342	}
	343
	344	static int rk_vop_bind(struct udevice *dev)
	345	{
	346	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	347
	348	plat->size = 1920 * 1080 * 2;
	349
	350	return 0;
	351	}
	352
	353	static const struct video_ops rk_vop_ops = {
	354	};
	355
	356	static const struct udevice_id rk_vop_ids[] = {
9f819931 EG	357	{ .compatible = "rockchip,rk3399-vop-big" },
9f819931 EG	358	{ .compatible = "rockchip,rk3399-vop-lit" },
7b7ad5c3 SG	359	{ .compatible = "rockchip,rk3288-vop" },
	360	{ }
	361	};
	362
	363	U_BOOT_DRIVER(rk_vop) = {
	364	.name = "rk_vop",
	365	.id = UCLASS_VIDEO,
	366	.of_match = rk_vop_ids,
	367	.ops = &rk_vop_ops,
	368	.bind = rk_vop_bind,
	369	.probe = rk_vop_probe,
	370	.priv_auto_alloc_size = sizeof(struct rk_vop_priv),
	371	};