[people/ms/u-boot.git] / include / configs / CPCI2DP.h

/*
 * (C) Copyright 2005
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
#define CONFIG_SYS_PCI_CLASSCODE       0x0280	/* PCI Class Code: Network/Other*/

#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CONFIG_SYS_PCI_PTM2LA	0xef000000	/* point to internal regs + PB0/1 */
#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/

#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

#define CONFIG_SYS_EEPROM_WREN         1

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0               /* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (PB0) initialization					*/
#define CONFIG_SYS_EBC_PB2AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
#define CONFIG_SYS_EBC_PB2CR		0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (PB1) initialization				*/
#define CONFIG_SYS_EBC_PB3AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
#define CONFIG_SYS_EBC_PB3CR		0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */

#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * GPIO definitions
 */
#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 13)   /* GPIO13 */
#define CONFIG_SYS_SELF_RST		(0x80000000 >> 14)   /* GPIO14 */
#define CONFIG_SYS_PB_LED		(0x80000000 >> 16)   /* GPIO16 */
#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 23)   /* GPIO23 */

#endif	/* __CONFIG_H */
Commit	Line	Data
7644f16f SR	1	/*
	2	* (C) Copyright 2005
	3	* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
7644f16f SR	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
7644f16f	21
2ae18241	22	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
37ea0092	23	#define CONFIG_DISPLAY_BOARDINFO
2ae18241	24
7644f16f SR	25	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
	26
	27	#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
	28
	29	#define CONFIG_BAUDRATE 9600
7644f16f SR	30
	31	#undef CONFIG_BOOTARGS
	32	#undef CONFIG_BOOTCOMMAND
	33
	34	#define CONFIG_PREBOOT /* enable preboot variable */
	35
	36	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	37	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
7644f16f SR	38
	39	#define CONFIG_MII 1 /* MII PHY management */
	40	#define CONFIG_PHY_ADDR 0 /* PHY address */
	41
11799434 JL	42	/*
	43	* BOOTP options
	44	*/
	45	#define CONFIG_BOOTP_BOOTFILESIZE
	46	#define CONFIG_BOOTP_BOOTPATH
	47	#define CONFIG_BOOTP_GATEWAY
	48	#define CONFIG_BOOTP_HOSTNAME
	49
49cf7e8e JL	50	/*
	51	* Command line configuration.
	52	*/
49cf7e8e JL	53	#define CONFIG_CMD_PCI
49cf7e8e JL	54	#define CONFIG_CMD_IRQ
49cf7e8e JL	55	#define CONFIG_CMD_BSP
	56	#define CONFIG_CMD_EEPROM
	57
7644f16f SR	58	#undef CONFIG_WATCHDOG /* watchdog disabled */
	59
	60	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	61
	62	/*
	63	* Miscellaneous configurable options
	64	*/
6d0f6bcf	65	#define CONFIG_SYS_LONGHELP /* undef to save memory */
7644f16f	66
49cf7e8e	67	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	68	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
7644f16f	69	#else
6d0f6bcf	70	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
7644f16f	71	#endif
6d0f6bcf JCPV	72	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	73	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	74	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
7644f16f	75
6d0f6bcf	76	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
7644f16f	77
6d0f6bcf	78	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
7644f16f SR	79
	80	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
	81
6d0f6bcf JCPV	82	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	83	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
7644f16f	84
550650dd	85	#define CONFIG_CONS_INDEX 2 /* Use UART1 */
550650dd SR	86	#define CONFIG_SYS_NS16550_SERIAL
	87	#define CONFIG_SYS_NS16550_REG_SIZE 1
	88	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	89
6d0f6bcf	90	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf	91	#define CONFIG_SYS_BASE_BAUD 691200
7644f16f SR	92
7644f16f SR	93	/* The following table includes the supported baudrates */
6d0f6bcf	94	#define CONFIG_SYS_BAUDRATE_TABLE \
7644f16f SR	95	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	96	57600, 115200, 230400, 460800, 921600 }
	97
6d0f6bcf JCPV	98	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	99	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
7644f16f	100
6d0f6bcf	101	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
7644f16f SR	102
	103	/*-----------------------------------------------------------------------
	104	* PCI stuff
	105	*-----------------------------------------------------------------------
	106	*/
	107	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	108	#define PCI_HOST_FORCE 1 /* configure as pci host */
	109	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	110
	111	#define CONFIG_PCI /* include pci support */
842033e6	112	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
7644f16f SR	113	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	114	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	115	/* resource configuration */
	116
	117	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	118
	119	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
	120
	121	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	124	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */
	125	#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
2076d0a1	126
6d0f6bcf JCPV	127	#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
	128	#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) \| 1) /* memsize, enable hard-wired to 1 */
	129	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	130	#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */
	131	#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
	132	#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
7644f16f SR	133
	134	/*-----------------------------------------------------------------------
	135	* Start addresses for the final memory configuration
	136	* (Set up by the startup code)
6d0f6bcf	137	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
7644f16f	138	*/
6d0f6bcf JCPV	139	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	140	#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
	141	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	142	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	143	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
7644f16f SR	144
	145	/*
	146	* For booting Linux, the board info and command line data
	147	* have to be in the first 8 MB of memory, since this is
	148	* the maximum mapped by the Linux kernel during initialization.
	149	*/
6d0f6bcf	150	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
7644f16f SR	151	/*-----------------------------------------------------------------------
	152	* FLASH organization
	153	*/
6d0f6bcf JCPV	154	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	155	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
7644f16f	156
6d0f6bcf JCPV	157	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	158	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
7644f16f	159
6d0f6bcf JCPV	160	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	161	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	162	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
7644f16f	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	165	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	166	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
7644f16f	167
6d0f6bcf	168	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
7644f16f	169
bb1f8b4f	170	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	171	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	172	#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
7644f16f SR	173
	174	/*-----------------------------------------------------------------------
	175	* I2C EEPROM (CAT24WC16) for environment
	176	*/
880540de DE	177	#define CONFIG_SYS_I2C
	178	#define CONFIG_SYS_I2C_PPC4XX
	179	#define CONFIG_SYS_I2C_PPC4XX_CH0
	180	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	181	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
7644f16f	182
6d0f6bcf JCPV	183	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	184	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
7644f16f	185	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	186	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	187	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
7644f16f SR	188	/* 16 byte page write mode using*/
7644f16f SR	189	/* last 4 bits of the address */
6d0f6bcf	190	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
7644f16f	191
6d0f6bcf	192	#define CONFIG_SYS_EEPROM_WREN 1
7644f16f	193
7644f16f SR	194	/*
	195	* Init Memory Controller:
	196	*
	197	* BR0/1 and OR0/1 (FLASH)
	198	*/
	199	#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
	200	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	201
	202	/*-----------------------------------------------------------------------
	203	* External Bus Controller (EBC) Setup
	204	*/
	205
	206	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	207	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	208	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
7644f16f SR	209
7644f16f SR	210	/* Memory Bank 2 (PB0) initialization */
6d0f6bcf JCPV	211	#define CONFIG_SYS_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
6d0f6bcf JCPV	212	#define CONFIG_SYS_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
7644f16f SR	213
7644f16f SR	214	/* Memory Bank 3 (PB1) initialization */
6d0f6bcf JCPV	215	#define CONFIG_SYS_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
6d0f6bcf JCPV	216	#define CONFIG_SYS_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
7644f16f SR	217
	218	/*-----------------------------------------------------------------------
	219	* Definitions for initial stack pointer and data area (in data cache)
	220	*/
6d0f6bcf	221	#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
7644f16f	222
6d0f6bcf	223	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
553f0982	224	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
25ddd1fb	225	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	226	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
7644f16f SR	227
	228	/*-----------------------------------------------------------------------
	229	* GPIO definitions
	230	*/
6d0f6bcf JCPV	231	#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */
	232	#define CONFIG_SYS_SELF_RST (0x80000000 >> 14) /* GPIO14 */
	233	#define CONFIG_SYS_PB_LED (0x80000000 >> 16) /* GPIO16 */
	234	#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */
7644f16f	235
7644f16f	236	#endif /* __CONFIG_H */