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1552af70 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF52277 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
1552af70 TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M52277EVB_H | |
15 | #define _M52277EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
1552af70 TL |
21 | #define CONFIG_M52277EVB /* M52277EVB board */ |
22 | ||
1552af70 | 23 | #define CONFIG_MCFUART |
6d0f6bcf | 24 | #define CONFIG_SYS_UART_PORT (0) |
1552af70 TL |
25 | |
26 | #undef CONFIG_WATCHDOG | |
27 | ||
28 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
29 | ||
30 | /* | |
31 | * BOOTP options | |
32 | */ | |
33 | #define CONFIG_BOOTP_BOOTFILESIZE | |
34 | #define CONFIG_BOOTP_BOOTPATH | |
35 | #define CONFIG_BOOTP_GATEWAY | |
36 | #define CONFIG_BOOTP_HOSTNAME | |
37 | ||
a21d0c2c TL |
38 | #define CONFIG_HOSTNAME M52277EVB |
39 | #define CONFIG_SYS_UBOOT_END 0x3FFFF | |
40 | #define CONFIG_SYS_LOAD_ADDR2 0x40010007 | |
41 | #ifdef CONFIG_SYS_STMICRO_BOOT | |
42 | /* ST Micro serial flash */ | |
1552af70 | 43 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d | 44 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
a21d0c2c TL |
45 | "loadaddr=0x40010000\0" \ |
46 | "uboot=u-boot.bin\0" \ | |
47 | "load=loadb ${loadaddr} ${baudrate};" \ | |
5368c55d | 48 | "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ |
1552af70 | 49 | "upd=run load; run prog\0" \ |
a21d0c2c TL |
50 | "prog=sf probe 0:2 10000 1;" \ |
51 | "sf erase 0 30000;" \ | |
52 | "sf write ${loadaddr} 0 30000;" \ | |
1552af70 TL |
53 | "save\0" \ |
54 | "" | |
a21d0c2c TL |
55 | #endif |
56 | #ifdef CONFIG_SYS_SPANSION_BOOT | |
57 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5368c55d | 58 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
a21d0c2c TL |
59 | "loadaddr=0x40010000\0" \ |
60 | "uboot=u-boot.bin\0" \ | |
61 | "load=loadb ${loadaddr} ${baudrate}\0" \ | |
62 | "upd=run load; run prog\0" \ | |
5368c55d MV |
63 | "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
64 | " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
65 | "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ | |
66 | __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
67 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
a21d0c2c TL |
68 | " ${filesize}; save\0" \ |
69 | "updsbf=run loadsbf; run progsbf\0" \ | |
70 | "loadsbf=loadb ${loadaddr} ${baudrate};" \ | |
5368c55d | 71 | "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ |
a21d0c2c TL |
72 | "progsbf=sf probe 0:2 10000 1;" \ |
73 | "sf erase 0 30000;" \ | |
74 | "sf write ${loadaddr} 0 30000;" \ | |
75 | "" | |
76 | #endif | |
1552af70 TL |
77 | |
78 | /* LCD */ | |
79 | #ifdef CONFIG_CMD_BMP | |
1552af70 TL |
80 | #define CONFIG_SPLASH_SCREEN |
81 | #define CONFIG_LCD_LOGO | |
82 | #define CONFIG_SHARP_LQ035Q7DH06 | |
83 | #endif | |
84 | ||
85 | /* USB */ | |
86 | #ifdef CONFIG_CMD_USB | |
a21d0c2c | 87 | #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 |
6d0f6bcf | 88 | #define CONFIG_SYS_USB_EHCI_CPU_INIT |
1552af70 TL |
89 | #endif |
90 | ||
91 | /* Realtime clock */ | |
92 | #define CONFIG_MCFRTC | |
93 | #undef RTC_DEBUG | |
6d0f6bcf | 94 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
1552af70 TL |
95 | |
96 | /* Timer */ | |
97 | #define CONFIG_MCFTMR | |
98 | #undef CONFIG_MCFPIT | |
99 | ||
100 | /* I2c */ | |
00f792e0 HS |
101 | #define CONFIG_SYS_I2C |
102 | #define CONFIG_SYS_I2C_FSL | |
103 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
104 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
105 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
a21d0c2c TL |
106 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
107 | ||
108 | /* DSPI and Serial Flash */ | |
ee0a8462 | 109 | #define CONFIG_CF_SPI |
a21d0c2c TL |
110 | #define CONFIG_CF_DSPI |
111 | #define CONFIG_HARD_SPI | |
a21d0c2c TL |
112 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 |
113 | #ifdef CONFIG_CMD_SPI | |
114 | # define CONFIG_SYS_DSPI_CS2 | |
a21d0c2c | 115 | |
ee0a8462 TL |
116 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
117 | DSPI_CTAR_PCSSCK_1CLK | \ | |
118 | DSPI_CTAR_PASC(0) | \ | |
119 | DSPI_CTAR_PDT(0) | \ | |
120 | DSPI_CTAR_CSSCK(0) | \ | |
121 | DSPI_CTAR_ASC(0) | \ | |
122 | DSPI_CTAR_DT(1)) | |
a21d0c2c | 123 | #endif |
1552af70 TL |
124 | |
125 | /* Input, PCI, Flexbus, and VCO */ | |
126 | #define CONFIG_EXTRA_CLOCK | |
127 | ||
6d0f6bcf | 128 | #define CONFIG_SYS_INPUT_CLKSRC 16000000 |
1552af70 | 129 | |
a21d0c2c | 130 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
1552af70 | 131 | |
6d0f6bcf | 132 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
1552af70 | 133 | |
a21d0c2c | 134 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
1552af70 | 135 | |
6d0f6bcf | 136 | #define CONFIG_SYS_MBAR 0xFC000000 |
1552af70 TL |
137 | |
138 | /* | |
139 | * Low Level Configuration Settings | |
140 | * (address mappings, register initial values, etc.) | |
141 | * You should know what you are doing if you make changes here. | |
142 | */ | |
143 | ||
a21d0c2c | 144 | /* |
1552af70 TL |
145 | * Definitions for initial stack pointer and data area (in DPRAM) |
146 | */ | |
6d0f6bcf | 147 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 148 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
a21d0c2c | 149 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 150 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
a21d0c2c | 151 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) |
553f0982 | 152 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
1552af70 | 153 | |
a21d0c2c | 154 | /* |
1552af70 TL |
155 | * Start addresses for the final memory configuration |
156 | * (Set up by the startup code) | |
6d0f6bcf | 157 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
1552af70 | 158 | */ |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
160 | #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ | |
161 | #define CONFIG_SYS_SDRAM_CFG1 0x43711630 | |
162 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
163 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 | |
164 | #define CONFIG_SYS_SDRAM_EMOD 0x81810000 | |
165 | #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 | |
a21d0c2c | 166 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 |
6d0f6bcf JCPV |
167 | |
168 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
169 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
170 | ||
a21d0c2c | 171 | #ifdef CONFIG_CF_SBF |
14d0a02a | 172 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
a21d0c2c TL |
173 | #else |
174 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
175 | #endif | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
177 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
178 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
1552af70 TL |
179 | |
180 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 181 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 182 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
1552af70 | 183 | |
a21d0c2c TL |
184 | /* |
185 | * Configuration for environment | |
27f7ae70 JJ |
186 | * Environment is not embedded in u-boot. First time runing may have env |
187 | * crc error warning if there is no correct environment on the flash. | |
1552af70 | 188 | */ |
a21d0c2c | 189 | #ifdef CONFIG_CF_SBF |
a21d0c2c | 190 | # define CONFIG_ENV_SPI_CS 2 |
a21d0c2c TL |
191 | #endif |
192 | #define CONFIG_ENV_OVERWRITE 1 | |
1552af70 TL |
193 | |
194 | /*----------------------------------------------------------------------- | |
195 | * FLASH organization | |
196 | */ | |
a21d0c2c | 197 | #ifdef CONFIG_SYS_STMICRO_BOOT |
ee0a8462 | 198 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
27f7ae70 | 199 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE |
a21d0c2c TL |
200 | # define CONFIG_ENV_OFFSET 0x30000 |
201 | # define CONFIG_ENV_SIZE 0x1000 | |
202 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
203 | #endif | |
204 | #ifdef CONFIG_SYS_SPANSION_BOOT | |
205 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
206 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
27f7ae70 | 207 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
a21d0c2c TL |
208 | # define CONFIG_ENV_SIZE 0x1000 |
209 | # define CONFIG_ENV_SECT_SIZE 0x8000 | |
210 | #endif | |
1552af70 | 211 | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_FLASH_CFI |
213 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 214 | # define CONFIG_FLASH_CFI_DRIVER 1 |
bbf6bbff TL |
215 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
216 | # define CONFIG_FLASH_SPANSION_S29WS_N 1 | |
6d0f6bcf JCPV |
217 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
218 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
219 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
220 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
221 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
222 | # define CONFIG_SYS_FLASH_CHECKSUM | |
a21d0c2c | 223 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } |
1552af70 TL |
224 | #endif |
225 | ||
5296cb1d | 226 | #define LDS_BOARD_TEXT \ |
227 | arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ | |
228 | arch/m68k/lib/built-in.o (.text*) | |
229 | ||
1552af70 TL |
230 | /* |
231 | * This is setting for JFFS2 support in u-boot. | |
232 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
233 | */ | |
234 | #ifdef CONFIG_CMD_JFFS2 | |
235 | # define CONFIG_JFFS2_DEV "nor0" | |
236 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) | |
6d0f6bcf | 237 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) |
1552af70 TL |
238 | #endif |
239 | ||
240 | /*----------------------------------------------------------------------- | |
241 | * Cache Configuration | |
242 | */ | |
a21d0c2c | 243 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
1552af70 | 244 | |
dd9f054e | 245 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 246 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 247 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 248 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
249 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
250 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
251 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
252 | CF_ACR_EN | CF_ACR_SM_ALL) | |
253 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
254 | CF_CACR_DISD | CF_CACR_INVI | \ | |
255 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
256 | CF_CACR_EUSP) | |
257 | ||
1552af70 TL |
258 | /*----------------------------------------------------------------------- |
259 | * Memory bank definitions | |
260 | */ | |
261 | /* | |
262 | * CS0 - NOR Flash | |
263 | * CS1 - Available | |
264 | * CS2 - Available | |
265 | * CS3 - Available | |
266 | * CS4 - Available | |
267 | * CS5 - Available | |
268 | */ | |
269 | ||
a21d0c2c TL |
270 | #ifdef CONFIG_CF_SBF |
271 | #define CONFIG_SYS_CS0_BASE 0x04000000 | |
272 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
273 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
274 | #else | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
276 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
277 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
a21d0c2c | 278 | #endif |
1552af70 TL |
279 | |
280 | #endif /* _M52277EVB_H */ |