[people/ms/u-boot.git] / include / configs / M52277EVB.h

/*
 * Configuation settings for the Freescale MCF52277 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M52277EVB_H
#define _M52277EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M52277EVB	/* M52277EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO

#define CONFIG_HOSTNAME			M52277EVB
#define CONFIG_SYS_UBOOT_END		0x3FFFF
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	"updsbf=run loadsbf; run progsbf\0"	\
	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"progsbf=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	""
#endif

/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_SPLASH_SCREEN
#define CONFIG_LCD_LOGO
#define CONFIG_SHARP_LQ035Q7DH06
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
#define CONFIG_SYS_USB_EHCI_CPU_INIT
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SYS_DSPI_CS2

#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_SYS_INPUT_CLKSRC	16000000

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x81810000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*
 * Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_IS_IN_SPI_FLASH
#	define CONFIG_ENV_SPI_CS	2
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif
#define CONFIG_ENV_OVERWRITE		1

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_OFFSET	0x30000
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x8000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_FLASH_SPANSION_S29WS_N	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
#endif

#define LDS_BOARD_TEXT \
        arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
	arch/m68k/lib/built-in.o            (.text*)

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

#ifdef CONFIG_CF_SBF
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#else
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#endif

#endif				/* _M52277EVB_H */
Commit	Line	Data
1552af70 TL	1	/*
	2	* Configuation settings for the Freescale MCF52277 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
1552af70 TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M52277EVB_H
	15	#define _M52277EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
1552af70 TL	21	#define CONFIG_M52277EVB /* M52277EVB board */
1552af70 TL	22
1552af70	23	#define CONFIG_MCFUART
6d0f6bcf	24	#define CONFIG_SYS_UART_PORT (0)
1552af70 TL	25
	26	#undef CONFIG_WATCHDOG
	27
	28	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	29
	30	/*
	31	* BOOTP options
	32	*/
	33	#define CONFIG_BOOTP_BOOTFILESIZE
	34	#define CONFIG_BOOTP_BOOTPATH
	35	#define CONFIG_BOOTP_GATEWAY
	36	#define CONFIG_BOOTP_HOSTNAME
	37
	38	/* Command line configuration */
1552af70	39	#define CONFIG_CMD_JFFS2
1552af70	40	#define CONFIG_CMD_REGINFO
a21d0c2c TL	41
	42	#define CONFIG_HOSTNAME M52277EVB
	43	#define CONFIG_SYS_UBOOT_END 0x3FFFF
	44	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
	45	#ifdef CONFIG_SYS_STMICRO_BOOT
	46	/* ST Micro serial flash */
1552af70	47	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	48	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	49	"loadaddr=0x40010000\0" \
	50	"uboot=u-boot.bin\0" \
	51	"load=loadb ${loadaddr} ${baudrate};" \
5368c55d	52	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
1552af70	53	"upd=run load; run prog\0" \
a21d0c2c TL	54	"prog=sf probe 0:2 10000 1;" \
	55	"sf erase 0 30000;" \
	56	"sf write ${loadaddr} 0 30000;" \
1552af70 TL	57	"save\0" \
1552af70 TL	58	""
a21d0c2c TL	59	#endif
	60	#ifdef CONFIG_SYS_SPANSION_BOOT
	61	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	62	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	63	"loadaddr=0x40010000\0" \
	64	"uboot=u-boot.bin\0" \
	65	"load=loadb ${loadaddr} ${baudrate}\0" \
	66	"upd=run load; run prog\0" \
5368c55d MV	67	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
	68	" " __stringify(CONFIG_SYS_UBOOT_END) ";" \
	69	"era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
	70	__stringify(CONFIG_SYS_UBOOT_END) ";" \
	71	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
a21d0c2c TL	72	" ${filesize}; save\0" \
	73	"updsbf=run loadsbf; run progsbf\0" \
	74	"loadsbf=loadb ${loadaddr} ${baudrate};" \
5368c55d	75	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
a21d0c2c TL	76	"progsbf=sf probe 0:2 10000 1;" \
	77	"sf erase 0 30000;" \
	78	"sf write ${loadaddr} 0 30000;" \
	79	""
	80	#endif
1552af70 TL	81
	82	/* LCD */
	83	#ifdef CONFIG_CMD_BMP
1552af70 TL	84	#define CONFIG_SPLASH_SCREEN
	85	#define CONFIG_LCD_LOGO
	86	#define CONFIG_SHARP_LQ035Q7DH06
	87	#endif
	88
	89	/* USB */
	90	#ifdef CONFIG_CMD_USB
a21d0c2c	91	#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
6d0f6bcf	92	#define CONFIG_SYS_USB_EHCI_CPU_INIT
1552af70 TL	93	#endif
	94
	95	/* Realtime clock */
	96	#define CONFIG_MCFRTC
	97	#undef RTC_DEBUG
6d0f6bcf	98	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
1552af70 TL	99
	100	/* Timer */
	101	#define CONFIG_MCFTMR
	102	#undef CONFIG_MCFPIT
	103
	104	/* I2c */
00f792e0 HS	105	#define CONFIG_SYS_I2C
	106	#define CONFIG_SYS_I2C_FSL
	107	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	108	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	109	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
a21d0c2c TL	110	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	111
	112	/* DSPI and Serial Flash */
ee0a8462	113	#define CONFIG_CF_SPI
a21d0c2c TL	114	#define CONFIG_CF_DSPI
a21d0c2c TL	115	#define CONFIG_HARD_SPI
a21d0c2c TL	116	#define CONFIG_SYS_SBFHDR_SIZE 0x7
	117	#ifdef CONFIG_CMD_SPI
	118	# define CONFIG_SYS_DSPI_CS2
a21d0c2c	119
ee0a8462 TL	120	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	121	DSPI_CTAR_PCSSCK_1CLK \| \
	122	DSPI_CTAR_PASC(0) \| \
	123	DSPI_CTAR_PDT(0) \| \
	124	DSPI_CTAR_CSSCK(0) \| \
	125	DSPI_CTAR_ASC(0) \| \
	126	DSPI_CTAR_DT(1))
a21d0c2c	127	#endif
1552af70 TL	128
	129	/* Input, PCI, Flexbus, and VCO */
	130	#define CONFIG_EXTRA_CLOCK
	131
6d0f6bcf	132	#define CONFIG_SYS_INPUT_CLKSRC 16000000
1552af70	133
a21d0c2c	134	#define CONFIG_PRAM 2048 /* 2048 KB */
1552af70	135
6d0f6bcf	136	#define CONFIG_SYS_LONGHELP /* undef to save memory */
1552af70 TL	137
1552af70 TL	138	#if defined(CONFIG_CMD_KGDB)
a21d0c2c	139	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
1552af70	140	#else
a21d0c2c	141	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1552af70	142	#endif
a21d0c2c TL	143	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	144	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	145	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1552af70	146
a21d0c2c	147	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
1552af70	148
6d0f6bcf	149	#define CONFIG_SYS_MBAR 0xFC000000
1552af70 TL	150
	151	/*
	152	* Low Level Configuration Settings
	153	* (address mappings, register initial values, etc.)
	154	* You should know what you are doing if you make changes here.
	155	*/
	156
a21d0c2c	157	/*
1552af70 TL	158	* Definitions for initial stack pointer and data area (in DPRAM)
1552af70 TL	159	*/
6d0f6bcf	160	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	161	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
a21d0c2c	162	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	163	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
a21d0c2c	164	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
553f0982	165	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
1552af70	166
a21d0c2c	167	/*
1552af70 TL	168	* Start addresses for the final memory configuration
1552af70 TL	169	* (Set up by the startup code)
6d0f6bcf	170	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
1552af70	171	*/
6d0f6bcf JCPV	172	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	173	#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
	174	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	175	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	176	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
	177	#define CONFIG_SYS_SDRAM_EMOD 0x81810000
	178	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
a21d0c2c	179	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
6d0f6bcf JCPV	180
	181	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	182	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	183
a21d0c2c	184	#ifdef CONFIG_CF_SBF
14d0a02a	185	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
a21d0c2c TL	186	#else
	187	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	188	#endif
6d0f6bcf JCPV	189	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	190	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	191	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
1552af70 TL	192
1552af70 TL	193	/* Initial Memory map for Linux */
6d0f6bcf	194	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	195	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
1552af70	196
a21d0c2c TL	197	/*
a21d0c2c TL	198	* Configuration for environment
27f7ae70 JJ	199	* Environment is not embedded in u-boot. First time runing may have env
27f7ae70 JJ	200	* crc error warning if there is no correct environment on the flash.
1552af70	201	*/
a21d0c2c TL	202	#ifdef CONFIG_CF_SBF
	203	# define CONFIG_ENV_IS_IN_SPI_FLASH
	204	# define CONFIG_ENV_SPI_CS 2
	205	#else
	206	# define CONFIG_ENV_IS_IN_FLASH 1
	207	#endif
	208	#define CONFIG_ENV_OVERWRITE 1
1552af70 TL	209
	210	/*-----------------------------------------------------------------------
	211	* FLASH organization
	212	*/
a21d0c2c	213	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462	214	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
27f7ae70	215	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
a21d0c2c TL	216	# define CONFIG_ENV_OFFSET 0x30000
	217	# define CONFIG_ENV_SIZE 0x1000
	218	# define CONFIG_ENV_SECT_SIZE 0x10000
	219	#endif
	220	#ifdef CONFIG_SYS_SPANSION_BOOT
	221	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	222	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
27f7ae70	223	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
a21d0c2c TL	224	# define CONFIG_ENV_SIZE 0x1000
	225	# define CONFIG_ENV_SECT_SIZE 0x8000
	226	#endif
1552af70	227
6d0f6bcf JCPV	228	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	229	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	230	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff TL	231	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
bbf6bbff TL	232	# define CONFIG_FLASH_SPANSION_S29WS_N 1
6d0f6bcf JCPV	233	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	234	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	235	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	236	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	237	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	238	# define CONFIG_SYS_FLASH_CHECKSUM
a21d0c2c	239	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
1552af70 TL	240	#endif
1552af70 TL	241
5296cb1d	242	#define LDS_BOARD_TEXT \
	243	arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
	244	arch/m68k/lib/built-in.o (.text*)
	245
1552af70 TL	246	/*
	247	* This is setting for JFFS2 support in u-boot.
	248	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	249	*/
	250	#ifdef CONFIG_CMD_JFFS2
	251	# define CONFIG_JFFS2_DEV "nor0"
	252	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
6d0f6bcf	253	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
1552af70 TL	254	#endif
	255
	256	/*-----------------------------------------------------------------------
	257	* Cache Configuration
	258	*/
a21d0c2c	259	#define CONFIG_SYS_CACHELINE_SIZE 16
1552af70	260
dd9f054e	261	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	262	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	263	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	264	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	265	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	266	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	267	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	268	CF_ACR_EN \| CF_ACR_SM_ALL)
	269	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	270	CF_CACR_DISD \| CF_CACR_INVI \| \
	271	CF_CACR_CEIB \| CF_CACR_DCM \| \
	272	CF_CACR_EUSP)
	273
1552af70 TL	274	/*-----------------------------------------------------------------------
	275	* Memory bank definitions
	276	*/
	277	/*
	278	* CS0 - NOR Flash
	279	* CS1 - Available
	280	* CS2 - Available
	281	* CS3 - Available
	282	* CS4 - Available
	283	* CS5 - Available
	284	*/
	285
a21d0c2c TL	286	#ifdef CONFIG_CF_SBF
	287	#define CONFIG_SYS_CS0_BASE 0x04000000
	288	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	289	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	290	#else
6d0f6bcf JCPV	291	#define CONFIG_SYS_CS0_BASE 0x00000000
	292	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	293	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
a21d0c2c	294	#endif
1552af70 TL	295
1552af70 TL	296	#endif /* _M52277EVB_H */