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bf9e3b38 WD |
1 | /* |
2 | * Configuation settings for the Motorola MC5282EVB board. | |
3 | * | |
4 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
26 | * board/config.h - configuration options, board specific | |
27 | */ | |
28 | ||
4e5ca3eb WD |
29 | #ifndef _CONFIG_M5282EVB_H |
30 | #define _CONFIG_M5282EVB_H | |
31 | ||
bf9e3b38 WD |
32 | /* |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
f28e1bd9 TL |
36 | #define CONFIG_MCF52x2 /* define processor family */ |
37 | #define CONFIG_M5282 /* define processor type */ | |
bf9e3b38 | 38 | |
f28e1bd9 | 39 | #define CONFIG_MCFTMR |
bf9e3b38 | 40 | |
f28e1bd9 | 41 | #define CONFIG_MCFUART |
6d0f6bcf | 42 | #define CONFIG_SYS_UART_PORT (0) |
79e0799c | 43 | #define CONFIG_BAUDRATE 115200 |
4e5ca3eb | 44 | |
f28e1bd9 | 45 | #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ |
bf9e3b38 WD |
46 | |
47 | /* Configuration for environment | |
48 | * Environment is embedded in u-boot in the second sector of the flash | |
49 | */ | |
0e8d1586 JCPV |
50 | #define CONFIG_ENV_ADDR 0xffe04000 |
51 | #define CONFIG_ENV_SIZE 0x2000 | |
5a1aceb0 | 52 | #define CONFIG_ENV_IS_IN_FLASH 1 |
bf9e3b38 | 53 | |
659e2f67 JL |
54 | /* |
55 | * BOOTP options | |
56 | */ | |
57 | #define CONFIG_BOOTP_BOOTFILESIZE | |
58 | #define CONFIG_BOOTP_BOOTPATH | |
59 | #define CONFIG_BOOTP_GATEWAY | |
60 | #define CONFIG_BOOTP_HOSTNAME | |
61 | ||
8353e139 JL |
62 | /* |
63 | * Command line configuration. | |
64 | */ | |
65 | #include <config_cmd_default.h> | |
dd9f054e | 66 | #define CONFIG_CMD_CACHE |
f28e1bd9 TL |
67 | #define CONFIG_CMD_NET |
68 | #define CONFIG_CMD_PING | |
69 | #define CONFIG_CMD_MII | |
8353e139 JL |
70 | |
71 | #undef CONFIG_CMD_LOADS | |
72 | #undef CONFIG_CMD_LOADB | |
73 | ||
f28e1bd9 TL |
74 | #define CONFIG_MCFFEC |
75 | #ifdef CONFIG_MCFFEC | |
f28e1bd9 | 76 | # define CONFIG_MII 1 |
0f3ba7e9 | 77 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
78 | # define CONFIG_SYS_DISCOVER_PHY |
79 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
80 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
f28e1bd9 | 81 | |
6d0f6bcf JCPV |
82 | # define CONFIG_SYS_FEC0_PINMUX 0 |
83 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 84 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
85 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
86 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
f28e1bd9 TL |
87 | # define FECDUPLEX FULL |
88 | # define FECSPEED _100BASET | |
89 | # else | |
6d0f6bcf JCPV |
90 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
91 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
f28e1bd9 | 92 | # endif |
6d0f6bcf | 93 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
f28e1bd9 | 94 | #endif |
bf9e3b38 | 95 | |
bf9e3b38 | 96 | #define CONFIG_BOOTDELAY 5 |
f28e1bd9 TL |
97 | #ifdef CONFIG_MCFFEC |
98 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 | |
99 | # define CONFIG_IPADDR 192.162.1.2 | |
100 | # define CONFIG_NETMASK 255.255.255.0 | |
101 | # define CONFIG_SERVERIP 192.162.1.1 | |
102 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
103 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
104 | #endif /* CONFIG_MCFFEC */ | |
105 | ||
4cb4e654 | 106 | #define CONFIG_HOSTNAME M5282EVB |
f28e1bd9 TL |
107 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
108 | "netdev=eth0\0" \ | |
109 | "loadaddr=10000\0" \ | |
110 | "u-boot=u-boot.bin\0" \ | |
111 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
112 | "upd=run load; run prog\0" \ | |
113 | "prog=prot off ffe00000 ffe3ffff;" \ | |
114 | "era ffe00000 ffe3ffff;" \ | |
115 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
116 | "save\0" \ | |
117 | "" | |
bf9e3b38 | 118 | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_PROMPT "-> " |
120 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
bf9e3b38 | 121 | |
8353e139 | 122 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 123 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
bf9e3b38 | 124 | #else |
6d0f6bcf | 125 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
bf9e3b38 | 126 | #endif |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
128 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
129 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
bf9e3b38 | 130 | |
6d0f6bcf | 131 | #define CONFIG_SYS_LOAD_ADDR 0x20000 |
bf9e3b38 | 132 | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_MEMTEST_START 0x400 |
134 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
bf9e3b38 | 135 | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_HZ 1000 |
137 | #define CONFIG_SYS_CLK 64000000 | |
bf9e3b38 | 138 | |
f28e1bd9 TL |
139 | /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ |
140 | ||
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ |
142 | #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ | |
bf9e3b38 WD |
143 | |
144 | /* | |
145 | * Low Level Configuration Settings | |
146 | * (address mappings, register initial values, etc.) | |
147 | * You should know what you are doing if you make changes here. | |
148 | */ | |
6d0f6bcf | 149 | #define CONFIG_SYS_MBAR 0x40000000 |
bf9e3b38 | 150 | |
bf9e3b38 WD |
151 | /*----------------------------------------------------------------------- |
152 | * Definitions for initial stack pointer and data area (in DPRAM) | |
153 | */ | |
6d0f6bcf | 154 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 155 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 156 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 157 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
bf9e3b38 WD |
158 | |
159 | /*----------------------------------------------------------------------- | |
160 | * Start addresses for the final memory configuration | |
161 | * (Set up by the startup code) | |
6d0f6bcf | 162 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
bf9e3b38 | 163 | */ |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
165 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
012522fe | 166 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 |
168 | #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 | |
bf9e3b38 WD |
169 | |
170 | /* If M5282 port is fully implemented the monitor base will be behind | |
171 | * the vector table. */ | |
14d0a02a | 172 | #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) |
6d0f6bcf | 173 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
f28e1bd9 | 174 | #else |
14d0a02a | 175 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ |
f28e1bd9 | 176 | #endif |
bf9e3b38 | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
179 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
180 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
bf9e3b38 | 181 | |
bf9e3b38 WD |
182 | /* |
183 | * For booting Linux, the board info and command line data | |
184 | * have to be in the first 8 MB of memory, since this is | |
185 | * the maximum mapped by the Linux kernel during initialization ?? | |
186 | */ | |
6d0f6bcf | 187 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
bf9e3b38 WD |
188 | |
189 | /*----------------------------------------------------------------------- | |
190 | * FLASH organization | |
191 | */ | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_FLASH_CFI |
193 | #ifdef CONFIG_SYS_FLASH_CFI | |
f28e1bd9 | 194 | |
00b1883a | 195 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
196 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
197 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
198 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
199 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
200 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
201 | # define CONFIG_SYS_FLASH_CHECKSUM | |
202 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
f28e1bd9 | 203 | #endif |
bf9e3b38 WD |
204 | |
205 | /*----------------------------------------------------------------------- | |
206 | * Cache Configuration | |
207 | */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
bf9e3b38 | 209 | |
dd9f054e | 210 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 211 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 212 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 213 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
214 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) |
215 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
216 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
217 | CF_ACR_EN | CF_ACR_SM_ALL) | |
218 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ | |
219 | CF_CACR_CEIB | CF_CACR_DBWE | \ | |
220 | CF_CACR_EUSP) | |
221 | ||
bf9e3b38 WD |
222 | /*----------------------------------------------------------------------- |
223 | * Memory bank definitions | |
224 | */ | |
012522fe TL |
225 | #define CONFIG_SYS_CS0_BASE 0xFFE00000 |
226 | #define CONFIG_SYS_CS0_CTRL 0x00001980 | |
227 | #define CONFIG_SYS_CS0_MASK 0x001F0001 | |
228 | ||
bf9e3b38 WD |
229 | /*----------------------------------------------------------------------- |
230 | * Port configuration | |
231 | */ | |
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ |
233 | #define CONFIG_SYS_PADDR 0x0000000 | |
234 | #define CONFIG_SYS_PADAT 0x0000000 | |
235 | ||
236 | #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ | |
237 | #define CONFIG_SYS_PBDDR 0x0000000 | |
238 | #define CONFIG_SYS_PBDAT 0x0000000 | |
239 | ||
240 | #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ | |
241 | #define CONFIG_SYS_PCDDR 0x0000000 | |
242 | #define CONFIG_SYS_PCDAT 0x0000000 | |
243 | ||
244 | #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ | |
245 | #define CONFIG_SYS_PCDDR 0x0000000 | |
246 | #define CONFIG_SYS_PCDAT 0x0000000 | |
247 | ||
248 | #define CONFIG_SYS_PEHLPAR 0xC0 | |
249 | #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ | |
250 | #define CONFIG_SYS_DDRUA 0x05 | |
251 | #define CONFIG_SYS_PJPAR 0xFF | |
4e5ca3eb | 252 | |
f28e1bd9 | 253 | #endif /* _CONFIG_M5282EVB_H */ |