[people/ms/u-boot.git] / include / configs / M5373EVB.h

/*
 * Configuation settings for the Freescale MCF5373 FireEngine board.
 *
 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5373EVB_H
#define _M5373EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO

#ifdef CONFIG_NANDFLASH_SIZE
#      define CONFIG_CMD_NAND
#endif

#define CONFIG_SYS_UNIFY_CACHE

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_MCFRTC
#undef RTC_DEBUG

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M5373EVB
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"			\
	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"	\
	"u-boot=u-boot.bin\0"	\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"	\
	"prog=prot off 0 3ffff;"	\
	"era 0 3ffff;"	\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"	\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#ifdef CONFIG_CMD_KGDB
#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
#define CONFIG_SYS_LOAD_ADDR		0x40010000

#define CONFIG_SYS_CLK			80000000
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3

#define CONFIG_SYS_MBAR		0xFC000000

#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x53722730
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x018D0000

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

#ifdef CONFIG_NANDFLASH_SIZE
#	define CONFIG_SYS_MAX_NAND_DEVICE	1
#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
#	define CONFIG_SYS_NAND_SIZE		1
#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#	define NAND_ALLOW_ERASE_ALL	1
#	define CONFIG_JFFS2_NAND	1
#	define CONFIG_JFFS2_DEV		"nand0"
#	define CONFIG_JFFS2_PART_SIZE	(CONFIG_SYS_CS2_MASK & ~1)
#	define CONFIG_JFFS2_PART_OFFSET	0x00000000
#endif

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
					 CF_CACR_DCM_P)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - CompactFlash and registers
 * CS2 - NAND Flash 16, 32, or 64MB
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0
#define CONFIG_SYS_CS0_MASK		0x007f0001
#define CONFIG_SYS_CS0_CTRL		0x00001fa0

#define CONFIG_SYS_CS1_BASE		0x10000000
#define CONFIG_SYS_CS1_MASK		0x001f0001
#define CONFIG_SYS_CS1_CTRL		0x002A3780

#ifdef CONFIG_NANDFLASH_SIZE
#define CONFIG_SYS_CS2_BASE		0x20000000
#define CONFIG_SYS_CS2_MASK		((CONFIG_NANDFLASH_SIZE << 20) | 1)
#define CONFIG_SYS_CS2_CTRL		0x00001f60
#endif

#endif				/* _M5373EVB_H */
Commit	Line	Data
aa5f1f9d TL	1	/*
	2	* Configuation settings for the Freescale MCF5373 FireEngine board.
	3	*
2ee03c6e	4	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
aa5f1f9d TL	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
aa5f1f9d TL	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
aa5f1f9d TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M5373EVB_H
	15	#define _M5373EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
aa5f1f9d	21
aa5f1f9d	22	#define CONFIG_MCFUART
6d0f6bcf	23	#define CONFIG_SYS_UART_PORT (0)
aa5f1f9d	24	#define CONFIG_BAUDRATE 115200
aa5f1f9d TL	25
	26	#undef CONFIG_WATCHDOG
	27	#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
	28
	29	/* Command line configuration */
	30	#include <config_cmd_default.h>
	31
	32	#define CONFIG_CMD_CACHE
	33	#define CONFIG_CMD_DATE
	34	#define CONFIG_CMD_ELF
	35	#define CONFIG_CMD_FLASH
	36	#define CONFIG_CMD_I2C
	37	#define CONFIG_CMD_MEMORY
	38	#define CONFIG_CMD_MISC
	39	#define CONFIG_CMD_MII
	40	#define CONFIG_CMD_NET
	41	#define CONFIG_CMD_PING
	42	#define CONFIG_CMD_REGINFO
	43
2ee03c6e	44	#ifdef CONFIG_NANDFLASH_SIZE
aa5f1f9d TL	45	# define CONFIG_CMD_NAND
	46	#endif
	47
6d0f6bcf	48	#define CONFIG_SYS_UNIFY_CACHE
aa5f1f9d TL	49
	50	#define CONFIG_MCFFEC
	51	#ifdef CONFIG_MCFFEC
aa5f1f9d	52	# define CONFIG_MII 1
0f3ba7e9	53	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	54	# define CONFIG_SYS_DISCOVER_PHY
	55	# define CONFIG_SYS_RX_ETH_BUFFER 8
	56	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
aa5f1f9d	57
6d0f6bcf JCPV	58	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	59	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	60	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	61	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	62	# ifndef CONFIG_SYS_DISCOVER_PHY
aa5f1f9d TL	63	# define FECDUPLEX FULL
	64	# define FECSPEED _100BASET
	65	# else
6d0f6bcf JCPV	66	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	67	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
aa5f1f9d	68	# endif
6d0f6bcf	69	# endif /* CONFIG_SYS_DISCOVER_PHY */
aa5f1f9d TL	70	#endif
	71
	72	#define CONFIG_MCFRTC
	73	#undef RTC_DEBUG
	74
	75	/* Timer */
	76	#define CONFIG_MCFTMR
	77	#undef CONFIG_MCFPIT
	78
	79	/* I2C */
00f792e0 HS	80	#define CONFIG_SYS_I2C
	81	#define CONFIG_SYS_I2C_FSL
	82	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	83	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	84	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
6d0f6bcf	85	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
aa5f1f9d TL	86
	87	#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	88	#define CONFIG_UDP_CHECKSUM
	89
	90	#ifdef CONFIG_MCFFEC
	91	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	92	# define CONFIG_IPADDR 192.162.1.2
	93	# define CONFIG_NETMASK 255.255.255.0
	94	# define CONFIG_SERVERIP 192.162.1.1
	95	# define CONFIG_GATEWAYIP 192.162.1.1
	96	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	97	#endif /* FEC_ENET */
	98
	99	#define CONFIG_HOSTNAME M5373EVB
	100	#define CONFIG_EXTRA_ENV_SETTINGS \
	101	"netdev=eth0\0" \
5368c55d	102	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
aa5f1f9d TL	103	"u-boot=u-boot.bin\0" \
	104	"load=tftp ${loadaddr) ${u-boot}\0" \
	105	"upd=run load; run prog\0" \
09933fb0 JJ	106	"prog=prot off 0 3ffff;" \
09933fb0 JJ	107	"era 0 3ffff;" \
aa5f1f9d TL	108	"cp.b ${loadaddr} 0 ${filesize};" \
	109	"save\0" \
	110	""
	111
	112	#define CONFIG_PRAM 512 /* 512 KB */
6d0f6bcf JCPV	113	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	114	#define CONFIG_SYS_LONGHELP /* undef to save memory */
aa5f1f9d TL	115
aa5f1f9d TL	116	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	117	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
aa5f1f9d	118	#else
6d0f6bcf	119	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
aa5f1f9d TL	120	#endif
aa5f1f9d TL	121
6d0f6bcf JCPV	122	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	123	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	124	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	125	#define CONFIG_SYS_LOAD_ADDR 0x40010000
aa5f1f9d	126
6d0f6bcf JCPV	127	#define CONFIG_SYS_CLK 80000000
6d0f6bcf JCPV	128	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
aa5f1f9d	129
6d0f6bcf	130	#define CONFIG_SYS_MBAR 0xFC000000
aa5f1f9d	131
6d0f6bcf	132	#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
aa5f1f9d TL	133
	134	/*
	135	* Low Level Configuration Settings
	136	* (address mappings, register initial values, etc.)
	137	* You should know what you are doing if you make changes here.
	138	*/
	139	/*-----------------------------------------------------------------------
	140	* Definitions for initial stack pointer and data area (in DPRAM)
	141	*/
6d0f6bcf	142	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	143	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	144	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	145	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
6d0f6bcf	146	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
aa5f1f9d TL	147
	148	/*-----------------------------------------------------------------------
	149	* Start addresses for the final memory configuration
	150	* (Set up by the startup code)
6d0f6bcf	151	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
aa5f1f9d	152	*/
6d0f6bcf JCPV	153	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	154	#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
	155	#define CONFIG_SYS_SDRAM_CFG1 0x53722730
	156	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	157	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
	158	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	159	#define CONFIG_SYS_SDRAM_MODE 0x018D0000
aa5f1f9d	160
6d0f6bcf JCPV	161	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	162	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
aa5f1f9d	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	165	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
aa5f1f9d	166
6d0f6bcf JCPV	167	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	168	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
aa5f1f9d TL	169
	170	/*
	171	* For booting Linux, the board info and command line data
	172	* have to be in the first 8 MB of memory, since this is
	173	* the maximum mapped by the Linux kernel during initialization ??
	174	*/
6d0f6bcf	175	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	176	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
aa5f1f9d TL	177
	178	/*-----------------------------------------------------------------------
	179	* FLASH organization
	180	*/
6d0f6bcf JCPV	181	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	182	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	183	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	184	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
	185	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	186	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	187	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	188	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
aa5f1f9d TL	189	#endif
aa5f1f9d TL	190
2ee03c6e	191	#ifdef CONFIG_NANDFLASH_SIZE
6d0f6bcf JCPV	192	# define CONFIG_SYS_MAX_NAND_DEVICE 1
	193	# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
	194	# define CONFIG_SYS_NAND_SIZE 1
	195	# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
aa5f1f9d TL	196	# define NAND_ALLOW_ERASE_ALL 1
	197	# define CONFIG_JFFS2_NAND 1
	198	# define CONFIG_JFFS2_DEV "nand0"
6d0f6bcf	199	# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
aa5f1f9d TL	200	# define CONFIG_JFFS2_PART_OFFSET 0x00000000
	201	#endif
	202
6d0f6bcf	203	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
aa5f1f9d TL	204
	205	/* Configuration for environment
	206	* Environment is embedded in u-boot in the second sector of the flash
	207	*/
0e8d1586 JCPV	208	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	209	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	210	#define CONFIG_ENV_IS_IN_FLASH 1
aa5f1f9d TL	211
	212	/*-----------------------------------------------------------------------
	213	* Cache Configuration
	214	*/
6d0f6bcf	215	#define CONFIG_SYS_CACHELINE_SIZE 16
aa5f1f9d	216
dd9f054e	217	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	218	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	219	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	220	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	221	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
	222	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	223	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	224	CF_ACR_EN \| CF_ACR_SM_ALL)
	225	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC \| CF_CACR_CINVA \| \
	226	CF_CACR_DCM_P)
	227
aa5f1f9d TL	228	/*-----------------------------------------------------------------------
	229	* Chipselect bank definitions
	230	*/
	231	/*
	232	* CS0 - NOR Flash 1, 2, 4, or 8MB
	233	* CS1 - CompactFlash and registers
	234	* CS2 - NAND Flash 16, 32, or 64MB
	235	* CS3 - Available
	236	* CS4 - Available
	237	* CS5 - Available
	238	*/
6d0f6bcf JCPV	239	#define CONFIG_SYS_CS0_BASE 0
	240	#define CONFIG_SYS_CS0_MASK 0x007f0001
	241	#define CONFIG_SYS_CS0_CTRL 0x00001fa0
aa5f1f9d	242
6d0f6bcf JCPV	243	#define CONFIG_SYS_CS1_BASE 0x10000000
	244	#define CONFIG_SYS_CS1_MASK 0x001f0001
	245	#define CONFIG_SYS_CS1_CTRL 0x002A3780
aa5f1f9d	246
2ee03c6e	247	#ifdef CONFIG_NANDFLASH_SIZE
6d0f6bcf	248	#define CONFIG_SYS_CS2_BASE 0x20000000
2ee03c6e	249	#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) \| 1)
6d0f6bcf	250	#define CONFIG_SYS_CS2_CTRL 0x00001f60
aa5f1f9d TL	251	#endif
	252
	253	#endif /* _M5373EVB_H */