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aa5f1f9d TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF5373 FireEngine board. | |
3 | * | |
2ee03c6e | 4 | * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. |
aa5f1f9d TL |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
aa5f1f9d TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M5373EVB_H | |
15 | #define _M5373EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
aa5f1f9d | 21 | |
aa5f1f9d | 22 | #define CONFIG_MCFUART |
6d0f6bcf | 23 | #define CONFIG_SYS_UART_PORT (0) |
aa5f1f9d | 24 | #define CONFIG_BAUDRATE 115200 |
aa5f1f9d TL |
25 | |
26 | #undef CONFIG_WATCHDOG | |
27 | #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ | |
28 | ||
29 | /* Command line configuration */ | |
aa5f1f9d | 30 | #define CONFIG_CMD_DATE |
aa5f1f9d TL |
31 | #define CONFIG_CMD_REGINFO |
32 | ||
2ee03c6e | 33 | #ifdef CONFIG_NANDFLASH_SIZE |
aa5f1f9d TL |
34 | # define CONFIG_CMD_NAND |
35 | #endif | |
36 | ||
6d0f6bcf | 37 | #define CONFIG_SYS_UNIFY_CACHE |
aa5f1f9d TL |
38 | |
39 | #define CONFIG_MCFFEC | |
40 | #ifdef CONFIG_MCFFEC | |
aa5f1f9d | 41 | # define CONFIG_MII 1 |
0f3ba7e9 | 42 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
43 | # define CONFIG_SYS_DISCOVER_PHY |
44 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
45 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
aa5f1f9d | 46 | |
6d0f6bcf JCPV |
47 | # define CONFIG_SYS_FEC0_PINMUX 0 |
48 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 49 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
50 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
51 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
aa5f1f9d TL |
52 | # define FECDUPLEX FULL |
53 | # define FECSPEED _100BASET | |
54 | # else | |
6d0f6bcf JCPV |
55 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
56 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
aa5f1f9d | 57 | # endif |
6d0f6bcf | 58 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
aa5f1f9d TL |
59 | #endif |
60 | ||
61 | #define CONFIG_MCFRTC | |
62 | #undef RTC_DEBUG | |
63 | ||
64 | /* Timer */ | |
65 | #define CONFIG_MCFTMR | |
66 | #undef CONFIG_MCFPIT | |
67 | ||
68 | /* I2C */ | |
00f792e0 HS |
69 | #define CONFIG_SYS_I2C |
70 | #define CONFIG_SYS_I2C_FSL | |
71 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
72 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
73 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
6d0f6bcf | 74 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
aa5f1f9d TL |
75 | |
76 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
77 | #define CONFIG_UDP_CHECKSUM | |
78 | ||
79 | #ifdef CONFIG_MCFFEC | |
aa5f1f9d TL |
80 | # define CONFIG_IPADDR 192.162.1.2 |
81 | # define CONFIG_NETMASK 255.255.255.0 | |
82 | # define CONFIG_SERVERIP 192.162.1.1 | |
83 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
aa5f1f9d TL |
84 | #endif /* FEC_ENET */ |
85 | ||
86 | #define CONFIG_HOSTNAME M5373EVB | |
87 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
88 | "netdev=eth0\0" \ | |
5368c55d | 89 | "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
aa5f1f9d TL |
90 | "u-boot=u-boot.bin\0" \ |
91 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
92 | "upd=run load; run prog\0" \ | |
09933fb0 JJ |
93 | "prog=prot off 0 3ffff;" \ |
94 | "era 0 3ffff;" \ | |
aa5f1f9d TL |
95 | "cp.b ${loadaddr} 0 ${filesize};" \ |
96 | "save\0" \ | |
97 | "" | |
98 | ||
99 | #define CONFIG_PRAM 512 /* 512 KB */ | |
6d0f6bcf | 100 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
aa5f1f9d TL |
101 | |
102 | #ifdef CONFIG_CMD_KGDB | |
6d0f6bcf | 103 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
aa5f1f9d | 104 | #else |
6d0f6bcf | 105 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
aa5f1f9d TL |
106 | #endif |
107 | ||
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
109 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
110 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
111 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 | |
aa5f1f9d | 112 | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_CLK 80000000 |
114 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 | |
aa5f1f9d | 115 | |
6d0f6bcf | 116 | #define CONFIG_SYS_MBAR 0xFC000000 |
aa5f1f9d | 117 | |
6d0f6bcf | 118 | #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) |
aa5f1f9d TL |
119 | |
120 | /* | |
121 | * Low Level Configuration Settings | |
122 | * (address mappings, register initial values, etc.) | |
123 | * You should know what you are doing if you make changes here. | |
124 | */ | |
125 | /*----------------------------------------------------------------------- | |
126 | * Definitions for initial stack pointer and data area (in DPRAM) | |
127 | */ | |
6d0f6bcf | 128 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 129 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 130 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 131 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
6d0f6bcf | 132 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
aa5f1f9d TL |
133 | |
134 | /*----------------------------------------------------------------------- | |
135 | * Start addresses for the final memory configuration | |
136 | * (Set up by the startup code) | |
6d0f6bcf | 137 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
aa5f1f9d | 138 | */ |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
140 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ | |
141 | #define CONFIG_SYS_SDRAM_CFG1 0x53722730 | |
142 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
143 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 | |
144 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
145 | #define CONFIG_SYS_SDRAM_MODE 0x018D0000 | |
aa5f1f9d | 146 | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
148 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
aa5f1f9d | 149 | |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
151 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
aa5f1f9d | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
154 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
aa5f1f9d TL |
155 | |
156 | /* | |
157 | * For booting Linux, the board info and command line data | |
158 | * have to be in the first 8 MB of memory, since this is | |
159 | * the maximum mapped by the Linux kernel during initialization ?? | |
160 | */ | |
6d0f6bcf | 161 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 162 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
aa5f1f9d TL |
163 | |
164 | /*----------------------------------------------------------------------- | |
165 | * FLASH organization | |
166 | */ | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_FLASH_CFI |
168 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 169 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
170 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
171 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
172 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
173 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
174 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
aa5f1f9d TL |
175 | #endif |
176 | ||
2ee03c6e | 177 | #ifdef CONFIG_NANDFLASH_SIZE |
6d0f6bcf JCPV |
178 | # define CONFIG_SYS_MAX_NAND_DEVICE 1 |
179 | # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE | |
180 | # define CONFIG_SYS_NAND_SIZE 1 | |
181 | # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
aa5f1f9d TL |
182 | # define NAND_ALLOW_ERASE_ALL 1 |
183 | # define CONFIG_JFFS2_NAND 1 | |
184 | # define CONFIG_JFFS2_DEV "nand0" | |
6d0f6bcf | 185 | # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) |
aa5f1f9d TL |
186 | # define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
187 | #endif | |
188 | ||
6d0f6bcf | 189 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
aa5f1f9d TL |
190 | |
191 | /* Configuration for environment | |
192 | * Environment is embedded in u-boot in the second sector of the flash | |
193 | */ | |
0e8d1586 JCPV |
194 | #define CONFIG_ENV_OFFSET 0x4000 |
195 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 196 | #define CONFIG_ENV_IS_IN_FLASH 1 |
aa5f1f9d | 197 | |
5296cb1d | 198 | #define LDS_BOARD_TEXT \ |
199 | . = DEFINED(env_offset) ? env_offset : .; \ | |
200 | common/env_embedded.o (.text*); | |
201 | ||
aa5f1f9d TL |
202 | /*----------------------------------------------------------------------- |
203 | * Cache Configuration | |
204 | */ | |
6d0f6bcf | 205 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
aa5f1f9d | 206 | |
dd9f054e | 207 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 208 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 209 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 210 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
211 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
212 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
213 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
214 | CF_ACR_EN | CF_ACR_SM_ALL) | |
215 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ | |
216 | CF_CACR_DCM_P) | |
217 | ||
aa5f1f9d TL |
218 | /*----------------------------------------------------------------------- |
219 | * Chipselect bank definitions | |
220 | */ | |
221 | /* | |
222 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
223 | * CS1 - CompactFlash and registers | |
224 | * CS2 - NAND Flash 16, 32, or 64MB | |
225 | * CS3 - Available | |
226 | * CS4 - Available | |
227 | * CS5 - Available | |
228 | */ | |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_CS0_BASE 0 |
230 | #define CONFIG_SYS_CS0_MASK 0x007f0001 | |
231 | #define CONFIG_SYS_CS0_CTRL 0x00001fa0 | |
aa5f1f9d | 232 | |
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_CS1_BASE 0x10000000 |
234 | #define CONFIG_SYS_CS1_MASK 0x001f0001 | |
235 | #define CONFIG_SYS_CS1_CTRL 0x002A3780 | |
aa5f1f9d | 236 | |
2ee03c6e | 237 | #ifdef CONFIG_NANDFLASH_SIZE |
6d0f6bcf | 238 | #define CONFIG_SYS_CS2_BASE 0x20000000 |
2ee03c6e | 239 | #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) |
6d0f6bcf | 240 | #define CONFIG_SYS_CS2_CTRL 0x00001f60 |
aa5f1f9d TL |
241 | #endif |
242 | ||
243 | #endif /* _M5373EVB_H */ |