[people/ms/u-boot.git] / include / configs / M54451EVB.h

/*
 * Configuation settings for the Freescale MCF54451 EVB board.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54451EVB_H
#define _M54451EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M54451EVB	/* M54451EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#define LDS_BOARD_TEXT                  board/freescale/m54451evb/sbf_dram_init.o (.text*)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP 50000

#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		M54451EVB
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 1000000 3;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#else
#define CONFIG_SYS_UBOOT_END	0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)	\
	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"	\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI

#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM			2048	/* 2048 KB */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR			0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x33633F30
#define CONFIG_SYS_SDRAM_CFG2		0x57670000
#define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
#define CONFIG_SYS_SDRAM_EMOD		0x80810000
#define CONFIG_SYS_SDRAM_MODE		0x008D0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SERIAL_BOOT
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/* Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#if defined(CONFIG_SYS_STMICRO_BOOT)
#	define CONFIG_ENV_SPI_CS		1
#	define CONFIG_ENV_OFFSET		0x20000
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#else
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x20000
#endif
#undef CONFIG_ENV_OVERWRITE

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }

#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE		16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 16MB
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

 /* Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00004D80

#define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE

#endif				/* _M54451EVB_H */
Commit	Line	Data
05316f8e TL	1	/*
	2	* Configuation settings for the Freescale MCF54451 EVB board.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
05316f8e TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M54451EVB_H
	15	#define _M54451EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
05316f8e TL	21	#define CONFIG_M54451EVB /* M54451EVB board */
	22
	23	#define CONFIG_MCFUART
6d0f6bcf	24	#define CONFIG_SYS_UART_PORT (0)
05316f8e	25
c74dda8b AD	26	#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
c74dda8b AD	27
05316f8e TL	28	#undef CONFIG_WATCHDOG
	29
	30	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	31
	32	/*
	33	* BOOTP options
	34	*/
	35	#define CONFIG_BOOTP_BOOTFILESIZE
	36	#define CONFIG_BOOTP_BOOTPATH
	37	#define CONFIG_BOOTP_GATEWAY
	38	#define CONFIG_BOOTP_HOSTNAME
	39
05316f8e TL	40	/* Network configuration */
	41	#define CONFIG_MCFFEC
	42	#ifdef CONFIG_MCFFEC
05316f8e TL	43	# define CONFIG_MII 1
05316f8e TL	44	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	45	# define CONFIG_SYS_DISCOVER_PHY
	46	# define CONFIG_SYS_RX_ETH_BUFFER 8
	47	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e	48
6d0f6bcf JCPV	49	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	50	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
05316f8e TL	51	# define MCFFEC_TOUT_LOOP 50000
05316f8e TL	52
05316f8e TL	53	# define CONFIG_ETHPRIME "FEC0"
	54	# define CONFIG_IPADDR 192.162.1.2
	55	# define CONFIG_NETMASK 255.255.255.0
	56	# define CONFIG_SERVERIP 192.162.1.1
	57	# define CONFIG_GATEWAYIP 192.162.1.1
05316f8e	58
6d0f6bcf JCPV	59	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	60	# ifndef CONFIG_SYS_DISCOVER_PHY
05316f8e TL	61	# define FECDUPLEX FULL
	62	# define FECSPEED _100BASET
	63	# else
6d0f6bcf JCPV	64	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	65	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e	66	# endif
6d0f6bcf	67	# endif /* CONFIG_SYS_DISCOVER_PHY */
05316f8e TL	68	#endif
	69
	70	#define CONFIG_HOSTNAME M54451EVB
6d0f6bcf	71	#ifdef CONFIG_SYS_STMICRO_BOOT
05316f8e	72	/* ST Micro serial flash */
6d0f6bcf	73	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
05316f8e TL	74	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	75	"netdev=eth0\0" \
5368c55d	76	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	77	"loadaddr=0x40010000\0" \
	78	"sbfhdr=sbfhdr.bin\0" \
	79	"uboot=u-boot.bin\0" \
	80	"load=tftp ${loadaddr} ${sbfhdr};" \
5368c55d	81	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
05316f8e	82	"upd=run load; run prog\0" \
09933fb0	83	"prog=sf probe 0:1 1000000 3;" \
05316f8e TL	84	"sf erase 0 30000;" \
	85	"sf write ${loadaddr} 0 30000;" \
	86	"save\0" \
	87	""
	88	#else
6d0f6bcf	89	#define CONFIG_SYS_UBOOT_END 0x3FFFF
05316f8e TL	90	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	91	"netdev=eth0\0" \
5368c55d	92	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	93	"loadaddr=40010000\0" \
	94	"u-boot=u-boot.bin\0" \
	95	"load=tftp ${loadaddr) ${u-boot}\0" \
	96	"upd=run load; run prog\0" \
5368c55d MV	97	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
5368c55d MV	98	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
05316f8e TL	99	"cp.b ${loadaddr} 0 ${filesize};" \
	100	"save\0" \
	101	""
	102	#endif
	103
	104	/* Realtime clock */
	105	#define CONFIG_MCFRTC
	106	#undef RTC_DEBUG
6d0f6bcf	107	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
05316f8e TL	108
	109	/* Timer */
	110	#define CONFIG_MCFTMR
	111	#undef CONFIG_MCFPIT
	112
	113	/* I2c */
00f792e0 HS	114	#define CONFIG_SYS_I2C
	115	#define CONFIG_SYS_I2C_FSL
	116	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	117	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	118	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
709b384b	119	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
05316f8e TL	120
	121	/* DSPI and Serial Flash */
	122	#define CONFIG_CF_DSPI
	123	#define CONFIG_SERIAL_FLASH
	124	#define CONFIG_HARD_SPI
6d0f6bcf	125	#define CONFIG_SYS_SBFHDR_SIZE 0x7
05316f8e	126	#ifdef CONFIG_CMD_SPI
05316f8e	127
ee0a8462 TL	128	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	129	DSPI_CTAR_PCSSCK_1CLK \| \
	130	DSPI_CTAR_PASC(0) \| \
	131	DSPI_CTAR_PDT(0) \| \
	132	DSPI_CTAR_CSSCK(0) \| \
	133	DSPI_CTAR_ASC(0) \| \
	134	DSPI_CTAR_DT(1))
	135	# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
	136	# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
05316f8e TL	137	#endif
	138
	139	/* Input, PCI, Flexbus, and VCO */
	140	#define CONFIG_EXTRA_CLOCK
	141
709b384b	142	#define CONFIG_PRAM 2048 /* 2048 KB */
05316f8e	143
6d0f6bcf	144	#define CONFIG_SYS_LONGHELP /* undef to save memory */
05316f8e	145
6d0f6bcf	146	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
05316f8e	147
6d0f6bcf	148	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
05316f8e	149
709b384b	150	#define CONFIG_SYS_MBAR 0xFC000000
05316f8e TL	151
	152	/*
	153	* Low Level Configuration Settings
	154	* (address mappings, register initial values, etc.)
	155	* You should know what you are doing if you make changes here.
	156	*/
	157
	158	/*-----------------------------------------------------------------------
	159	* Definitions for initial stack pointer and data area (in DPRAM)
	160	*/
6d0f6bcf	161	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	162	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	163	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	164	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
6d0f6bcf	165	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
553f0982	166	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
05316f8e TL	167
	168	/*-----------------------------------------------------------------------
	169	* Start addresses for the final memory configuration
	170	* (Set up by the startup code)
6d0f6bcf	171	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
05316f8e	172	*/
6d0f6bcf JCPV	173	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	174	#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
	175	#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
	176	#define CONFIG_SYS_SDRAM_CFG2 0x57670000
	177	#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
	178	#define CONFIG_SYS_SDRAM_EMOD 0x80810000
	179	#define CONFIG_SYS_SDRAM_MODE 0x008D0000
	180	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
	181
	182	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	183	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
05316f8e TL	184
05316f8e TL	185	#ifdef CONFIG_CF_SBF
09933fb0	186	# define CONFIG_SERIAL_BOOT
14d0a02a	187	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
05316f8e	188	#else
6d0f6bcf	189	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
05316f8e	190	#endif
6d0f6bcf JCPV	191	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	192	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
05316f8e	193
09933fb0 JJ	194	/* Reserve 256 kB for malloc() */
09933fb0 JJ	195	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
05316f8e TL	196	/*
	197	* For booting Linux, the board info and command line data
	198	* have to be in the first 8 MB of memory, since this is
	199	* the maximum mapped by the Linux kernel during initialization ??
	200	*/
	201	/* Initial Memory map for Linux */
6d0f6bcf	202	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
05316f8e TL	203
05316f8e TL	204	/* Configuration for environment
09933fb0 JJ	205	* Environment is not embedded in u-boot. First time runing may have env
09933fb0 JJ	206	* crc error warning if there is no correct environment on the flash.
05316f8e	207	*/
709b384b	208	#if defined(CONFIG_SYS_STMICRO_BOOT)
0e8d1586 JCPV	209	# define CONFIG_ENV_SPI_CS 1
	210	# define CONFIG_ENV_OFFSET 0x20000
	211	# define CONFIG_ENV_SIZE 0x2000
	212	# define CONFIG_ENV_SECT_SIZE 0x10000
05316f8e	213	#else
09933fb0	214	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
709b384b	215	# define CONFIG_ENV_SIZE 0x2000
09933fb0	216	# define CONFIG_ENV_SECT_SIZE 0x20000
05316f8e TL	217	#endif
05316f8e TL	218	#undef CONFIG_ENV_OVERWRITE
05316f8e	219
ee0a8462 TL	220	/* FLASH organization */
ee0a8462 TL	221	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
05316f8e	222
6d0f6bcf JCPV	223	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	224	#ifdef CONFIG_SYS_FLASH_CFI
05316f8e TL	225
05316f8e TL	226	# define CONFIG_FLASH_CFI_DRIVER 1
709b384b	227	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
6d0f6bcf JCPV	228	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	229	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	230	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	231	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	232	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	233	# define CONFIG_SYS_FLASH_CHECKSUM
	234	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
05316f8e TL	235
	236	#endif
	237
	238	/*
	239	* This is setting for JFFS2 support in u-boot.
	240	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	241	*/
709b384b	242	#ifdef CONFIG_CMD_JFFS2
05316f8e TL	243	# define CONFIG_JFFS2_DEV "nor0"
05316f8e TL	244	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	245	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
05316f8e TL	246	#endif
05316f8e TL	247
709b384b	248	/* Cache Configuration */
6d0f6bcf	249	#define CONFIG_SYS_CACHELINE_SIZE 16
05316f8e	250
dd9f054e	251	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	252	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	253	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	254	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	255	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	256	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	257	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	258	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	259	CF_ACR_EN \| CF_ACR_SM_ALL)
	260	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	261	CF_CACR_ICINVA \| CF_CACR_EUSP)
	262	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	263	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	264	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	265
05316f8e TL	266	/*-----------------------------------------------------------------------
	267	* Memory bank definitions
	268	*/
	269	/*
709b384b	270	* CS0 - NOR Flash 16MB
05316f8e TL	271	* CS1 - Available
	272	* CS2 - Available
	273	* CS3 - Available
	274	* CS4 - Available
	275	* CS5 - Available
	276	*/
	277
709b384b	278	/* Flash */
6d0f6bcf	279	#define CONFIG_SYS_CS0_BASE 0x00000000
709b384b TL	280	#define CONFIG_SYS_CS0_MASK 0x00FF0001
709b384b TL	281	#define CONFIG_SYS_CS0_CTRL 0x00004D80
05316f8e	282
6d0f6bcf	283	#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
05316f8e TL	284
05316f8e TL	285	#endif /* _M54451EVB_H */