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8ae158cd TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF54455 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /* | |
27 | * board/config.h - configuration options, board specific | |
28 | */ | |
29 | ||
e8ee8f3a TL |
30 | #ifndef _M54455EVB_H |
31 | #define _M54455EVB_H | |
8ae158cd TL |
32 | |
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | #define CONFIG_MCF5445x /* define processor family */ | |
38 | #define CONFIG_M54455 /* define processor type */ | |
39 | #define CONFIG_M54455EVB /* M54455EVB board */ | |
40 | ||
8ae158cd | 41 | #define CONFIG_MCFUART |
6d0f6bcf | 42 | #define CONFIG_SYS_UART_PORT (0) |
8ae158cd | 43 | #define CONFIG_BAUDRATE 115200 |
8ae158cd TL |
44 | |
45 | #undef CONFIG_WATCHDOG | |
46 | ||
47 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
48 | ||
49 | /* | |
50 | * BOOTP options | |
51 | */ | |
52 | #define CONFIG_BOOTP_BOOTFILESIZE | |
53 | #define CONFIG_BOOTP_BOOTPATH | |
54 | #define CONFIG_BOOTP_GATEWAY | |
55 | #define CONFIG_BOOTP_HOSTNAME | |
56 | ||
57 | /* Command line configuration */ | |
58 | #include <config_cmd_default.h> | |
59 | ||
60 | #define CONFIG_CMD_BOOTD | |
61 | #define CONFIG_CMD_CACHE | |
62 | #define CONFIG_CMD_DATE | |
63 | #define CONFIG_CMD_DHCP | |
64 | #define CONFIG_CMD_ELF | |
65 | #define CONFIG_CMD_EXT2 | |
66 | #define CONFIG_CMD_FAT | |
67 | #define CONFIG_CMD_FLASH | |
68 | #define CONFIG_CMD_I2C | |
69 | #define CONFIG_CMD_IDE | |
70 | #define CONFIG_CMD_JFFS2 | |
71 | #define CONFIG_CMD_MEMORY | |
72 | #define CONFIG_CMD_MISC | |
73 | #define CONFIG_CMD_MII | |
74 | #define CONFIG_CMD_NET | |
e8ee8f3a | 75 | #undef CONFIG_CMD_PCI |
8ae158cd TL |
76 | #define CONFIG_CMD_PING |
77 | #define CONFIG_CMD_REGINFO | |
a7323bba | 78 | #define CONFIG_CMD_SPI |
922cd751 | 79 | #define CONFIG_CMD_SF |
8ae158cd TL |
80 | |
81 | #undef CONFIG_CMD_LOADB | |
82 | #undef CONFIG_CMD_LOADS | |
83 | ||
84 | /* Network configuration */ | |
85 | #define CONFIG_MCFFEC | |
86 | #ifdef CONFIG_MCFFEC | |
8ae158cd | 87 | # define CONFIG_MII 1 |
0f3ba7e9 | 88 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
89 | # define CONFIG_SYS_DISCOVER_PHY |
90 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
91 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
92 | ||
93 | # define CONFIG_SYS_FEC0_PINMUX 0 | |
94 | # define CONFIG_SYS_FEC1_PINMUX 0 | |
95 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
96 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
8ae158cd TL |
97 | # define MCFFEC_TOUT_LOOP 50000 |
98 | # define CONFIG_HAS_ETH1 | |
99 | ||
100 | # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
101 | # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" | |
102 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 | |
103 | # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 | |
104 | # define CONFIG_ETHPRIME "FEC0" | |
105 | # define CONFIG_IPADDR 192.162.1.2 | |
106 | # define CONFIG_NETMASK 255.255.255.0 | |
107 | # define CONFIG_SERVERIP 192.162.1.1 | |
108 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
109 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
110 | ||
6d0f6bcf JCPV |
111 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
112 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
8ae158cd TL |
113 | # define FECDUPLEX FULL |
114 | # define FECSPEED _100BASET | |
115 | # else | |
6d0f6bcf JCPV |
116 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
117 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8ae158cd | 118 | # endif |
6d0f6bcf | 119 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
8ae158cd TL |
120 | #endif |
121 | ||
122 | #define CONFIG_HOSTNAME M54455EVB | |
6d0f6bcf | 123 | #ifdef CONFIG_SYS_STMICRO_BOOT |
9f751551 | 124 | /* ST Micro serial flash */ |
6d0f6bcf | 125 | #define CONFIG_SYS_LOAD_ADDR2 0x40010013 |
8ae158cd TL |
126 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
127 | "netdev=eth0\0" \ | |
5368c55d | 128 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
129 | "loadaddr=0x40010000\0" \ |
130 | "sbfhdr=sbfhdr.bin\0" \ | |
131 | "uboot=u-boot.bin\0" \ | |
132 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
5368c55d | 133 | "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ |
8ae158cd | 134 | "upd=run load; run prog\0" \ |
09933fb0 | 135 | "prog=sf probe 0:1 1000000 3;" \ |
9f751551 TL |
136 | "sf erase 0 30000;" \ |
137 | "sf write ${loadaddr} 0 0x30000;" \ | |
8ae158cd TL |
138 | "save\0" \ |
139 | "" | |
9f751551 TL |
140 | #else |
141 | /* Atmel and Intel */ | |
6d0f6bcf JCPV |
142 | #ifdef CONFIG_SYS_ATMEL_BOOT |
143 | # define CONFIG_SYS_UBOOT_END 0x0403FFFF | |
144 | #elif defined(CONFIG_SYS_INTEL_BOOT) | |
145 | # define CONFIG_SYS_UBOOT_END 0x3FFFF | |
9f751551 TL |
146 | #endif |
147 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
148 | "netdev=eth0\0" \ | |
5368c55d | 149 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
150 | "loadaddr=0x40010000\0" \ |
151 | "uboot=u-boot.bin\0" \ | |
152 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
153 | "upd=run load; run prog\0" \ | |
5368c55d MV |
154 | "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
155 | " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
156 | "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ | |
157 | __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
158 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
9f751551 TL |
159 | " ${filesize}; save\0" \ |
160 | "" | |
161 | #endif | |
8ae158cd TL |
162 | |
163 | /* ATA configuration */ | |
164 | #define CONFIG_ISO_PARTITION | |
165 | #define CONFIG_DOS_PARTITION | |
166 | #define CONFIG_IDE_RESET 1 | |
167 | #define CONFIG_IDE_PREINIT 1 | |
168 | #define CONFIG_ATAPI | |
169 | #undef CONFIG_LBA48 | |
170 | ||
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_IDE_MAXBUS 1 |
172 | #define CONFIG_SYS_IDE_MAXDEVICE 2 | |
8ae158cd | 173 | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 |
175 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
8ae158cd | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
178 | #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
179 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
180 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
8ae158cd TL |
181 | |
182 | /* Realtime clock */ | |
183 | #define CONFIG_MCFRTC | |
184 | #undef RTC_DEBUG | |
6d0f6bcf | 185 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
8ae158cd TL |
186 | |
187 | /* Timer */ | |
188 | #define CONFIG_MCFTMR | |
189 | #undef CONFIG_MCFPIT | |
190 | ||
191 | /* I2c */ | |
00f792e0 HS |
192 | #define CONFIG_SYS_I2C |
193 | #define CONFIG_SYS_I2C_FSL | |
194 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
195 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
196 | #define CONFIG_SYS_FSLI2C_OFFSET 0x58000 | |
6d0f6bcf | 197 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
8ae158cd | 198 | |
bae61eef | 199 | /* DSPI and Serial Flash */ |
ee0a8462 | 200 | #define CONFIG_CF_SPI |
bae61eef | 201 | #define CONFIG_CF_DSPI |
a7323bba | 202 | #define CONFIG_HARD_SPI |
6d0f6bcf | 203 | #define CONFIG_SYS_SBFHDR_SIZE 0x13 |
a7323bba | 204 | #ifdef CONFIG_CMD_SPI |
922cd751 TL |
205 | # define CONFIG_SPI_FLASH |
206 | # define CONFIG_SPI_FLASH_STMICRO | |
207 | ||
ee0a8462 TL |
208 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
209 | DSPI_CTAR_PCSSCK_1CLK | \ | |
210 | DSPI_CTAR_PASC(0) | \ | |
211 | DSPI_CTAR_PDT(0) | \ | |
212 | DSPI_CTAR_CSSCK(0) | \ | |
213 | DSPI_CTAR_ASC(0) | \ | |
214 | DSPI_CTAR_DT(1)) | |
a7323bba | 215 | #endif |
bae61eef | 216 | |
8ae158cd | 217 | /* PCI */ |
e8ee8f3a | 218 | #ifdef CONFIG_CMD_PCI |
8ae158cd | 219 | #define CONFIG_PCI 1 |
2e72ad06 | 220 | #define CONFIG_PCI_PNP 1 |
f33fca22 | 221 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2e72ad06 | 222 | |
6d0f6bcf | 223 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 |
8ae158cd | 224 | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 |
226 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS | |
227 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 | |
8ae158cd | 228 | |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 |
230 | #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS | |
231 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 | |
8ae158cd | 232 | |
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 |
234 | #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS | |
235 | #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 | |
e8ee8f3a | 236 | #endif |
8ae158cd TL |
237 | |
238 | /* FPGA - Spartan 2 */ | |
239 | /* experiment | |
b03b25ca | 240 | #define CONFIG_FPGA |
8ae158cd | 241 | #define CONFIG_FPGA_COUNT 1 |
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_FPGA_PROG_FEEDBACK |
243 | #define CONFIG_SYS_FPGA_CHECK_CTRLC | |
8ae158cd TL |
244 | */ |
245 | ||
246 | /* Input, PCI, Flexbus, and VCO */ | |
247 | #define CONFIG_EXTRA_CLOCK | |
248 | ||
9f751551 | 249 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
8ae158cd | 250 | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_PROMPT "-> " |
252 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
8ae158cd TL |
253 | |
254 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 255 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8ae158cd | 256 | #else |
6d0f6bcf | 257 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8ae158cd | 258 | #endif |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
260 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
261 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8ae158cd | 262 | |
6d0f6bcf | 263 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
8ae158cd | 264 | |
6d0f6bcf | 265 | #define CONFIG_SYS_HZ 1000 |
8ae158cd | 266 | |
6d0f6bcf | 267 | #define CONFIG_SYS_MBAR 0xFC000000 |
8ae158cd TL |
268 | |
269 | /* | |
270 | * Low Level Configuration Settings | |
271 | * (address mappings, register initial values, etc.) | |
272 | * You should know what you are doing if you make changes here. | |
273 | */ | |
274 | ||
275 | /*----------------------------------------------------------------------- | |
276 | * Definitions for initial stack pointer and data area (in DPRAM) | |
277 | */ | |
6d0f6bcf | 278 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 279 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 280 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 281 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
6d0f6bcf | 282 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
553f0982 | 283 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
8ae158cd TL |
284 | |
285 | /*----------------------------------------------------------------------- | |
286 | * Start addresses for the final memory configuration | |
287 | * (Set up by the startup code) | |
6d0f6bcf | 288 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
8ae158cd | 289 | */ |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
291 | #define CONFIG_SYS_SDRAM_BASE1 0x48000000 | |
292 | #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ | |
293 | #define CONFIG_SYS_SDRAM_CFG1 0x65311610 | |
294 | #define CONFIG_SYS_SDRAM_CFG2 0x59670000 | |
295 | #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 | |
296 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
297 | #define CONFIG_SYS_SDRAM_MODE 0x00010033 | |
298 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA | |
299 | ||
300 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
301 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
8ae158cd | 302 | |
9f751551 | 303 | #ifdef CONFIG_CF_SBF |
09933fb0 | 304 | # define CONFIG_SERIAL_BOOT |
14d0a02a | 305 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
9f751551 | 306 | #else |
6d0f6bcf | 307 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
9f751551 | 308 | #endif |
6d0f6bcf JCPV |
309 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
310 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
09933fb0 JJ |
311 | |
312 | /* Reserve 256 kB for malloc() */ | |
313 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
8ae158cd TL |
314 | |
315 | /* | |
316 | * For booting Linux, the board info and command line data | |
317 | * have to be in the first 8 MB of memory, since this is | |
318 | * the maximum mapped by the Linux kernel during initialization ?? | |
319 | */ | |
320 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 321 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
8ae158cd | 322 | |
9f751551 TL |
323 | /* |
324 | * Configuration for environment | |
09933fb0 JJ |
325 | * Environment is not embedded in u-boot. First time runing may have env |
326 | * crc error warning if there is no correct environment on the flash. | |
8ae158cd | 327 | */ |
9f751551 | 328 | #ifdef CONFIG_CF_SBF |
0b5099a8 | 329 | # define CONFIG_ENV_IS_IN_SPI_FLASH |
0e8d1586 | 330 | # define CONFIG_ENV_SPI_CS 1 |
9f751551 | 331 | #else |
5a1aceb0 | 332 | # define CONFIG_ENV_IS_IN_FLASH 1 |
9f751551 TL |
333 | #endif |
334 | #undef CONFIG_ENV_OVERWRITE | |
8ae158cd TL |
335 | |
336 | /*----------------------------------------------------------------------- | |
337 | * FLASH organization | |
338 | */ | |
6d0f6bcf | 339 | #ifdef CONFIG_SYS_STMICRO_BOOT |
ee0a8462 TL |
340 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
341 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE | |
0e8d1586 JCPV |
342 | # define CONFIG_ENV_OFFSET 0x30000 |
343 | # define CONFIG_ENV_SIZE 0x2000 | |
344 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 345 | #endif |
6d0f6bcf JCPV |
346 | #ifdef CONFIG_SYS_ATMEL_BOOT |
347 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
348 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
349 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
09933fb0 JJ |
350 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
351 | # define CONFIG_ENV_SIZE 0x2000 | |
352 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 353 | #endif |
6d0f6bcf JCPV |
354 | #ifdef CONFIG_SYS_INTEL_BOOT |
355 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
356 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
357 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
358 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) | |
0e8d1586 JCPV |
359 | # define CONFIG_ENV_SIZE 0x2000 |
360 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
8ae158cd TL |
361 | #endif |
362 | ||
6d0f6bcf JCPV |
363 | #define CONFIG_SYS_FLASH_CFI |
364 | #ifdef CONFIG_SYS_FLASH_CFI | |
8ae158cd | 365 | |
00b1883a | 366 | # define CONFIG_FLASH_CFI_DRIVER 1 |
bbf6bbff | 367 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
6d0f6bcf JCPV |
368 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
369 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
370 | # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
371 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
372 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
373 | # define CONFIG_SYS_FLASH_CHECKSUM | |
374 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } | |
b2d022d1 | 375 | # define CONFIG_FLASH_CFI_LEGACY |
8ae158cd | 376 | |
b2d022d1 | 377 | #ifdef CONFIG_FLASH_CFI_LEGACY |
6d0f6bcf JCPV |
378 | # define CONFIG_SYS_ATMEL_REGION 4 |
379 | # define CONFIG_SYS_ATMEL_TOTALSECT 11 | |
380 | # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} | |
381 | # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} | |
bae61eef | 382 | #endif |
8ae158cd TL |
383 | #endif |
384 | ||
385 | /* | |
386 | * This is setting for JFFS2 support in u-boot. | |
387 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
388 | */ | |
9f751551 TL |
389 | #ifdef CONFIG_CMD_JFFS2 |
390 | #ifdef CF_STMICRO_BOOT | |
391 | # define CONFIG_JFFS2_DEV "nor1" | |
392 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
6d0f6bcf | 393 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) |
9f751551 | 394 | #endif |
6d0f6bcf | 395 | #ifdef CONFIG_SYS_ATMEL_BOOT |
e8ee8f3a | 396 | # define CONFIG_JFFS2_DEV "nor1" |
8ae158cd | 397 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 |
6d0f6bcf | 398 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) |
9f751551 | 399 | #endif |
6d0f6bcf | 400 | #ifdef CONFIG_SYS_INTEL_BOOT |
8ae158cd TL |
401 | # define CONFIG_JFFS2_DEV "nor0" |
402 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) | |
6d0f6bcf | 403 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) |
8ae158cd | 404 | #endif |
9f751551 | 405 | #endif |
8ae158cd TL |
406 | |
407 | /*----------------------------------------------------------------------- | |
408 | * Cache Configuration | |
409 | */ | |
6d0f6bcf | 410 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
8ae158cd | 411 | |
dd9f054e | 412 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 413 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 414 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 415 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
416 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
417 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
418 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
419 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
420 | CF_ACR_EN | CF_ACR_SM_ALL) | |
421 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ | |
422 | CF_CACR_ICINVA | CF_CACR_EUSP) | |
423 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
424 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
425 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
426 | ||
8ae158cd TL |
427 | /*----------------------------------------------------------------------- |
428 | * Memory bank definitions | |
429 | */ | |
430 | /* | |
431 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
432 | * CS1 - CompactFlash and registers | |
433 | * CS2 - CPLD | |
434 | * CS3 - FPGA | |
435 | * CS4 - Available | |
436 | * CS5 - Available | |
437 | */ | |
438 | ||
6d0f6bcf | 439 | #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) |
8ae158cd | 440 | /* Atmel Flash */ |
6d0f6bcf JCPV |
441 | #define CONFIG_SYS_CS0_BASE 0x04000000 |
442 | #define CONFIG_SYS_CS0_MASK 0x00070001 | |
443 | #define CONFIG_SYS_CS0_CTRL 0x00001140 | |
8ae158cd | 444 | /* Intel Flash */ |
6d0f6bcf JCPV |
445 | #define CONFIG_SYS_CS1_BASE 0x00000000 |
446 | #define CONFIG_SYS_CS1_MASK 0x01FF0001 | |
447 | #define CONFIG_SYS_CS1_CTRL 0x00000D60 | |
8ae158cd | 448 | |
6d0f6bcf | 449 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE |
8ae158cd TL |
450 | #else |
451 | /* Intel Flash */ | |
6d0f6bcf JCPV |
452 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
453 | #define CONFIG_SYS_CS0_MASK 0x01FF0001 | |
454 | #define CONFIG_SYS_CS0_CTRL 0x00000D60 | |
8ae158cd | 455 | /* Atmel Flash */ |
6d0f6bcf JCPV |
456 | #define CONFIG_SYS_CS1_BASE 0x04000000 |
457 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
458 | #define CONFIG_SYS_CS1_CTRL 0x00001140 | |
8ae158cd | 459 | |
6d0f6bcf | 460 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE |
8ae158cd TL |
461 | #endif |
462 | ||
463 | /* CPLD */ | |
6d0f6bcf JCPV |
464 | #define CONFIG_SYS_CS2_BASE 0x08000000 |
465 | #define CONFIG_SYS_CS2_MASK 0x00070001 | |
466 | #define CONFIG_SYS_CS2_CTRL 0x003f1140 | |
8ae158cd TL |
467 | |
468 | /* FPGA */ | |
6d0f6bcf JCPV |
469 | #define CONFIG_SYS_CS3_BASE 0x09000000 |
470 | #define CONFIG_SYS_CS3_MASK 0x00070001 | |
471 | #define CONFIG_SYS_CS3_CTRL 0x00000020 | |
8ae158cd | 472 | |
e8ee8f3a | 473 | #endif /* _M54455EVB_H */ |