[people/ms/u-boot.git] / include / configs / M54455EVB.h

/*
 * Configuation settings for the Freescale MCF54455 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54455EVB_H
#define _M54455EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF5445x		/* define processor family */
#define CONFIG_M54455		/* define processor type */
#define CONFIG_M54455EVB	/* M54455EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#undef CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF

#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS

/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC1_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP 50000
#	define CONFIG_HAS_ETH1

#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
#	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
#	define CONFIG_ETH1ADDR		00:e0:0c:bc:e5:61
#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		M54455EVB
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010013
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 1000000 3;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 0x30000;"	\
	"save\0"				\
	""
#else
/* Atmel and Intel */
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_UBOOT_END	0x0403FFFF
#elif defined(CONFIG_SYS_INTEL_BOOT)
#	define CONFIG_SYS_UBOOT_END	0x3FFFF
#endif
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${uboot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	""
#endif

/* ATA configuration */
#define CONFIG_ISO_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT	1
#define CONFIG_ATAPI
#undef CONFIG_LBA48

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_BASE_ADDR	0x90000000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0

#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O                            */
#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers           */
#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers                 */

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x13
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SPI_FLASH
#	define CONFIG_SPI_FLASH_STMICRO

#	define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	4

#define CONFIG_SYS_PCI_MEM_BUS		0xA0000000
#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#define CONFIG_SYS_PCI_IO_BUS		0xB1000000
#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE		0x01000000

#define CONFIG_SYS_PCI_CFG_BUS		0xB0000000
#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
#endif

/* FPGA - Spartan 2 */
/* experiment
#define CONFIG_FPGA
#define CONFIG_FPGA_COUNT	1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
*/

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_HZ			1000

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_BASE1		0x48000000
#define CONFIG_SYS_SDRAM_SIZE		256	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x65311610
#define CONFIG_SYS_SDRAM_CFG2		0x59670000
#define CONFIG_SYS_SDRAM_CTRL		0xEA0B2000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x00010033
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0xAA

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SERIAL_BOOT
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*
 * Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_IS_IN_SPI_FLASH
#	define CONFIG_ENV_SPI_CS		1
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif
#undef CONFIG_ENV_OVERWRITE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_OFFSET		0x30000
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x20000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#	define CONFIG_FLASH_CFI_LEGACY

#ifdef CONFIG_FLASH_CFI_LEGACY
#	define CONFIG_SYS_ATMEL_REGION		4
#	define CONFIG_SYS_ATMEL_TOTALSECT	11
#	define CONFIG_SYS_ATMEL_SECT		{1, 2, 1, 7}
#	define CONFIG_SYS_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
#endif
#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#ifdef CF_STMICRO_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH2_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH1_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x500000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE		16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - CompactFlash and registers
 * CS2 - CPLD
 * CS3 - FPGA
 * CS4 - Available
 * CS5 - Available
 */

#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 /* Atmel Flash */
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00070001
#define CONFIG_SYS_CS0_CTRL		0x00001140
/* Intel Flash */
#define CONFIG_SYS_CS1_BASE		0x00000000
#define CONFIG_SYS_CS1_MASK		0x01FF0001
#define CONFIG_SYS_CS1_CTRL		0x00000D60

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS0_BASE
#else
/* Intel Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x01FF0001
#define CONFIG_SYS_CS0_CTRL		0x00000D60
 /* Atmel Flash */
#define CONFIG_SYS_CS1_BASE		0x04000000
#define CONFIG_SYS_CS1_MASK		0x00070001
#define CONFIG_SYS_CS1_CTRL		0x00001140

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS1_BASE
#endif

/* CPLD */
#define CONFIG_SYS_CS2_BASE		0x08000000
#define CONFIG_SYS_CS2_MASK		0x00070001
#define CONFIG_SYS_CS2_CTRL		0x003f1140

/* FPGA */
#define CONFIG_SYS_CS3_BASE		0x09000000
#define CONFIG_SYS_CS3_MASK		0x00070001
#define CONFIG_SYS_CS3_CTRL		0x00000020

#endif				/* _M54455EVB_H */
Commit	Line	Data
8ae158cd TL	1	/*
	2	* Configuation settings for the Freescale MCF54455 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
8ae158cd TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
e8ee8f3a TL	14	#ifndef _M54455EVB_H
e8ee8f3a TL	15	#define _M54455EVB_H
8ae158cd TL	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21	#define CONFIG_MCF5445x /* define processor family */
	22	#define CONFIG_M54455 /* define processor type */
	23	#define CONFIG_M54455EVB /* M54455EVB board */
	24
8ae158cd	25	#define CONFIG_MCFUART
6d0f6bcf	26	#define CONFIG_SYS_UART_PORT (0)
8ae158cd	27	#define CONFIG_BAUDRATE 115200
8ae158cd TL	28
	29	#undef CONFIG_WATCHDOG
	30
	31	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	32
	33	/*
	34	* BOOTP options
	35	*/
	36	#define CONFIG_BOOTP_BOOTFILESIZE
	37	#define CONFIG_BOOTP_BOOTPATH
	38	#define CONFIG_BOOTP_GATEWAY
	39	#define CONFIG_BOOTP_HOSTNAME
	40
	41	/* Command line configuration */
	42	#include <config_cmd_default.h>
	43
	44	#define CONFIG_CMD_BOOTD
	45	#define CONFIG_CMD_CACHE
	46	#define CONFIG_CMD_DATE
	47	#define CONFIG_CMD_DHCP
	48	#define CONFIG_CMD_ELF
	49	#define CONFIG_CMD_EXT2
	50	#define CONFIG_CMD_FAT
	51	#define CONFIG_CMD_FLASH
	52	#define CONFIG_CMD_I2C
	53	#define CONFIG_CMD_IDE
	54	#define CONFIG_CMD_JFFS2
	55	#define CONFIG_CMD_MEMORY
	56	#define CONFIG_CMD_MISC
	57	#define CONFIG_CMD_MII
	58	#define CONFIG_CMD_NET
e8ee8f3a	59	#undef CONFIG_CMD_PCI
8ae158cd TL	60	#define CONFIG_CMD_PING
8ae158cd TL	61	#define CONFIG_CMD_REGINFO
a7323bba	62	#define CONFIG_CMD_SPI
922cd751	63	#define CONFIG_CMD_SF
8ae158cd TL	64
	65	#undef CONFIG_CMD_LOADB
	66	#undef CONFIG_CMD_LOADS
	67
	68	/* Network configuration */
	69	#define CONFIG_MCFFEC
	70	#ifdef CONFIG_MCFFEC
8ae158cd	71	# define CONFIG_MII 1
0f3ba7e9	72	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	73	# define CONFIG_SYS_DISCOVER_PHY
	74	# define CONFIG_SYS_RX_ETH_BUFFER 8
	75	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	76
	77	# define CONFIG_SYS_FEC0_PINMUX 0
	78	# define CONFIG_SYS_FEC1_PINMUX 0
	79	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	80	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
8ae158cd TL	81	# define MCFFEC_TOUT_LOOP 50000
	82	# define CONFIG_HAS_ETH1
	83
	84	# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	85	# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
	86	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	87	# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
	88	# define CONFIG_ETHPRIME "FEC0"
	89	# define CONFIG_IPADDR 192.162.1.2
	90	# define CONFIG_NETMASK 255.255.255.0
	91	# define CONFIG_SERVERIP 192.162.1.1
	92	# define CONFIG_GATEWAYIP 192.162.1.1
	93	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	94
6d0f6bcf JCPV	95	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	96	# ifndef CONFIG_SYS_DISCOVER_PHY
8ae158cd TL	97	# define FECDUPLEX FULL
	98	# define FECSPEED _100BASET
	99	# else
6d0f6bcf JCPV	100	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	101	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
8ae158cd	102	# endif
6d0f6bcf	103	# endif /* CONFIG_SYS_DISCOVER_PHY */
8ae158cd TL	104	#endif
	105
	106	#define CONFIG_HOSTNAME M54455EVB
6d0f6bcf	107	#ifdef CONFIG_SYS_STMICRO_BOOT
9f751551	108	/* ST Micro serial flash */
6d0f6bcf	109	#define CONFIG_SYS_LOAD_ADDR2 0x40010013
8ae158cd TL	110	#define CONFIG_EXTRA_ENV_SETTINGS \
8ae158cd TL	111	"netdev=eth0\0" \
5368c55d	112	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	113	"loadaddr=0x40010000\0" \
	114	"sbfhdr=sbfhdr.bin\0" \
	115	"uboot=u-boot.bin\0" \
	116	"load=tftp ${loadaddr} ${sbfhdr};" \
5368c55d	117	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
8ae158cd	118	"upd=run load; run prog\0" \
09933fb0	119	"prog=sf probe 0:1 1000000 3;" \
9f751551 TL	120	"sf erase 0 30000;" \
9f751551 TL	121	"sf write ${loadaddr} 0 0x30000;" \
8ae158cd TL	122	"save\0" \
8ae158cd TL	123	""
9f751551 TL	124	#else
9f751551 TL	125	/* Atmel and Intel */
6d0f6bcf JCPV	126	#ifdef CONFIG_SYS_ATMEL_BOOT
	127	# define CONFIG_SYS_UBOOT_END 0x0403FFFF
	128	#elif defined(CONFIG_SYS_INTEL_BOOT)
	129	# define CONFIG_SYS_UBOOT_END 0x3FFFF
9f751551 TL	130	#endif
	131	#define CONFIG_EXTRA_ENV_SETTINGS \
	132	"netdev=eth0\0" \
5368c55d	133	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	134	"loadaddr=0x40010000\0" \
	135	"uboot=u-boot.bin\0" \
	136	"load=tftp ${loadaddr} ${uboot}\0" \
	137	"upd=run load; run prog\0" \
5368c55d MV	138	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
	139	" " __stringify(CONFIG_SYS_UBOOT_END) ";" \
	140	"era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
	141	__stringify(CONFIG_SYS_UBOOT_END) ";" \
	142	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
9f751551 TL	143	" ${filesize}; save\0" \
	144	""
	145	#endif
8ae158cd TL	146
	147	/* ATA configuration */
	148	#define CONFIG_ISO_PARTITION
	149	#define CONFIG_DOS_PARTITION
	150	#define CONFIG_IDE_RESET 1
	151	#define CONFIG_IDE_PREINIT 1
	152	#define CONFIG_ATAPI
	153	#undef CONFIG_LBA48
	154
6d0f6bcf JCPV	155	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	156	#define CONFIG_SYS_IDE_MAXDEVICE 2
8ae158cd	157
6d0f6bcf JCPV	158	#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
6d0f6bcf JCPV	159	#define CONFIG_SYS_ATA_IDE0_OFFSET 0
8ae158cd	160
6d0f6bcf JCPV	161	#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	162	#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	163	#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	164	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
8ae158cd TL	165
	166	/* Realtime clock */
	167	#define CONFIG_MCFRTC
	168	#undef RTC_DEBUG
6d0f6bcf	169	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
8ae158cd TL	170
	171	/* Timer */
	172	#define CONFIG_MCFTMR
	173	#undef CONFIG_MCFPIT
	174
	175	/* I2c */
	176	#define CONFIG_FSL_I2C
	177	#define CONFIG_HARD_I2C /* I2C with hardware support */
	178	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	179	#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
	180	#define CONFIG_SYS_I2C_SLAVE 0x7F
	181	#define CONFIG_SYS_I2C_OFFSET 0x58000
	182	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
8ae158cd	183
bae61eef	184	/* DSPI and Serial Flash */
ee0a8462	185	#define CONFIG_CF_SPI
bae61eef	186	#define CONFIG_CF_DSPI
a7323bba	187	#define CONFIG_HARD_SPI
6d0f6bcf	188	#define CONFIG_SYS_SBFHDR_SIZE 0x13
a7323bba	189	#ifdef CONFIG_CMD_SPI
922cd751 TL	190	# define CONFIG_SPI_FLASH
	191	# define CONFIG_SPI_FLASH_STMICRO
	192
ee0a8462 TL	193	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	194	DSPI_CTAR_PCSSCK_1CLK \| \
	195	DSPI_CTAR_PASC(0) \| \
	196	DSPI_CTAR_PDT(0) \| \
	197	DSPI_CTAR_CSSCK(0) \| \
	198	DSPI_CTAR_ASC(0) \| \
	199	DSPI_CTAR_DT(1))
a7323bba	200	#endif
bae61eef	201
8ae158cd	202	/* PCI */
e8ee8f3a	203	#ifdef CONFIG_CMD_PCI
8ae158cd	204	#define CONFIG_PCI 1
2e72ad06	205	#define CONFIG_PCI_PNP 1
f33fca22	206	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
2e72ad06	207
6d0f6bcf	208	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
8ae158cd	209
6d0f6bcf JCPV	210	#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
	211	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
	212	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
8ae158cd	213
6d0f6bcf JCPV	214	#define CONFIG_SYS_PCI_IO_BUS 0xB1000000
	215	#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
	216	#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
8ae158cd	217
6d0f6bcf JCPV	218	#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
	219	#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
	220	#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
e8ee8f3a	221	#endif
8ae158cd TL	222
	223	/* FPGA - Spartan 2 */
	224	/* experiment
b03b25ca	225	#define CONFIG_FPGA
8ae158cd	226	#define CONFIG_FPGA_COUNT 1
6d0f6bcf JCPV	227	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
6d0f6bcf JCPV	228	#define CONFIG_SYS_FPGA_CHECK_CTRLC
8ae158cd TL	229	*/
	230
	231	/* Input, PCI, Flexbus, and VCO */
	232	#define CONFIG_EXTRA_CLOCK
	233
9f751551	234	#define CONFIG_PRAM 2048 /* 2048 KB */
8ae158cd	235
6d0f6bcf JCPV	236	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	237	#define CONFIG_SYS_LONGHELP /* undef to save memory */
8ae158cd TL	238
8ae158cd TL	239	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	240	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
8ae158cd	241	#else
6d0f6bcf	242	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
8ae158cd	243	#endif
6d0f6bcf JCPV	244	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	245	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	246	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
8ae158cd	247
6d0f6bcf	248	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
8ae158cd	249
6d0f6bcf	250	#define CONFIG_SYS_HZ 1000
8ae158cd	251
6d0f6bcf	252	#define CONFIG_SYS_MBAR 0xFC000000
8ae158cd TL	253
	254	/*
	255	* Low Level Configuration Settings
	256	* (address mappings, register initial values, etc.)
	257	* You should know what you are doing if you make changes here.
	258	*/
	259
	260	/*-----------------------------------------------------------------------
	261	* Definitions for initial stack pointer and data area (in DPRAM)
	262	*/
6d0f6bcf	263	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	264	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	265	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	266	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
6d0f6bcf	267	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
553f0982	268	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
8ae158cd TL	269
	270	/*-----------------------------------------------------------------------
	271	* Start addresses for the final memory configuration
	272	* (Set up by the startup code)
6d0f6bcf	273	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
8ae158cd	274	*/
6d0f6bcf JCPV	275	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	276	#define CONFIG_SYS_SDRAM_BASE1 0x48000000
	277	#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
	278	#define CONFIG_SYS_SDRAM_CFG1 0x65311610
	279	#define CONFIG_SYS_SDRAM_CFG2 0x59670000
	280	#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
	281	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	282	#define CONFIG_SYS_SDRAM_MODE 0x00010033
	283	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
	284
	285	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	286	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
8ae158cd	287
9f751551	288	#ifdef CONFIG_CF_SBF
09933fb0	289	# define CONFIG_SERIAL_BOOT
14d0a02a	290	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
9f751551	291	#else
6d0f6bcf	292	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
9f751551	293	#endif
6d0f6bcf JCPV	294	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	295	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
09933fb0 JJ	296
	297	/* Reserve 256 kB for malloc() */
	298	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
8ae158cd TL	299
	300	/*
	301	* For booting Linux, the board info and command line data
	302	* have to be in the first 8 MB of memory, since this is
	303	* the maximum mapped by the Linux kernel during initialization ??
	304	*/
	305	/* Initial Memory map for Linux */
6d0f6bcf	306	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
8ae158cd	307
9f751551 TL	308	/*
9f751551 TL	309	* Configuration for environment
09933fb0 JJ	310	* Environment is not embedded in u-boot. First time runing may have env
09933fb0 JJ	311	* crc error warning if there is no correct environment on the flash.
8ae158cd	312	*/
9f751551	313	#ifdef CONFIG_CF_SBF
0b5099a8	314	# define CONFIG_ENV_IS_IN_SPI_FLASH
0e8d1586	315	# define CONFIG_ENV_SPI_CS 1
9f751551	316	#else
5a1aceb0	317	# define CONFIG_ENV_IS_IN_FLASH 1
9f751551 TL	318	#endif
9f751551 TL	319	#undef CONFIG_ENV_OVERWRITE
8ae158cd TL	320
	321	/*-----------------------------------------------------------------------
	322	* FLASH organization
	323	*/
6d0f6bcf	324	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462 TL	325	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
ee0a8462 TL	326	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
0e8d1586 JCPV	327	# define CONFIG_ENV_OFFSET 0x30000
	328	# define CONFIG_ENV_SIZE 0x2000
	329	# define CONFIG_ENV_SECT_SIZE 0x10000
9f751551	330	#endif
6d0f6bcf JCPV	331	#ifdef CONFIG_SYS_ATMEL_BOOT
	332	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	333	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	334	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
09933fb0 JJ	335	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
	336	# define CONFIG_ENV_SIZE 0x2000
	337	# define CONFIG_ENV_SECT_SIZE 0x10000
9f751551	338	#endif
6d0f6bcf JCPV	339	#ifdef CONFIG_SYS_INTEL_BOOT
	340	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	341	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	342	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
	343	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
0e8d1586 JCPV	344	# define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	345	# define CONFIG_ENV_SECT_SIZE 0x20000
8ae158cd TL	346	#endif
8ae158cd TL	347
6d0f6bcf JCPV	348	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	349	#ifdef CONFIG_SYS_FLASH_CFI
8ae158cd	350
00b1883a	351	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff	352	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
6d0f6bcf JCPV	353	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	354	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
	355	# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	356	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	357	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	358	# define CONFIG_SYS_FLASH_CHECKSUM
	359	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
b2d022d1	360	# define CONFIG_FLASH_CFI_LEGACY
8ae158cd	361
b2d022d1	362	#ifdef CONFIG_FLASH_CFI_LEGACY
6d0f6bcf JCPV	363	# define CONFIG_SYS_ATMEL_REGION 4
	364	# define CONFIG_SYS_ATMEL_TOTALSECT 11
	365	# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
	366	# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
bae61eef	367	#endif
8ae158cd TL	368	#endif
	369
	370	/*
	371	* This is setting for JFFS2 support in u-boot.
	372	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	373	*/
9f751551 TL	374	#ifdef CONFIG_CMD_JFFS2
	375	#ifdef CF_STMICRO_BOOT
	376	# define CONFIG_JFFS2_DEV "nor1"
	377	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	378	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
9f751551	379	#endif
6d0f6bcf	380	#ifdef CONFIG_SYS_ATMEL_BOOT
e8ee8f3a	381	# define CONFIG_JFFS2_DEV "nor1"
8ae158cd	382	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	383	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
9f751551	384	#endif
6d0f6bcf	385	#ifdef CONFIG_SYS_INTEL_BOOT
8ae158cd TL	386	# define CONFIG_JFFS2_DEV "nor0"
8ae158cd TL	387	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
6d0f6bcf	388	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
8ae158cd	389	#endif
9f751551	390	#endif
8ae158cd TL	391
	392	/*-----------------------------------------------------------------------
	393	* Cache Configuration
	394	*/
6d0f6bcf	395	#define CONFIG_SYS_CACHELINE_SIZE 16
8ae158cd	396
dd9f054e	397	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	398	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	399	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	400	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	401	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	402	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	403	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	404	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	405	CF_ACR_EN \| CF_ACR_SM_ALL)
	406	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	407	CF_CACR_ICINVA \| CF_CACR_EUSP)
	408	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	409	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	410	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	411
8ae158cd TL	412	/*-----------------------------------------------------------------------
	413	* Memory bank definitions
	414	*/
	415	/*
	416	* CS0 - NOR Flash 1, 2, 4, or 8MB
	417	* CS1 - CompactFlash and registers
	418	* CS2 - CPLD
	419	* CS3 - FPGA
	420	* CS4 - Available
	421	* CS5 - Available
	422	*/
	423
6d0f6bcf	424	#if defined(CONFIG_SYS_ATMEL_BOOT) \|\| defined(CONFIG_SYS_STMICRO_BOOT)
8ae158cd	425	/* Atmel Flash */
6d0f6bcf JCPV	426	#define CONFIG_SYS_CS0_BASE 0x04000000
	427	#define CONFIG_SYS_CS0_MASK 0x00070001
	428	#define CONFIG_SYS_CS0_CTRL 0x00001140
8ae158cd	429	/* Intel Flash */
6d0f6bcf JCPV	430	#define CONFIG_SYS_CS1_BASE 0x00000000
	431	#define CONFIG_SYS_CS1_MASK 0x01FF0001
	432	#define CONFIG_SYS_CS1_CTRL 0x00000D60
8ae158cd	433
6d0f6bcf	434	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
8ae158cd TL	435	#else
8ae158cd TL	436	/* Intel Flash */
6d0f6bcf JCPV	437	#define CONFIG_SYS_CS0_BASE 0x00000000
	438	#define CONFIG_SYS_CS0_MASK 0x01FF0001
	439	#define CONFIG_SYS_CS0_CTRL 0x00000D60
8ae158cd	440	/* Atmel Flash */
6d0f6bcf JCPV	441	#define CONFIG_SYS_CS1_BASE 0x04000000
	442	#define CONFIG_SYS_CS1_MASK 0x00070001
	443	#define CONFIG_SYS_CS1_CTRL 0x00001140
8ae158cd	444
6d0f6bcf	445	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
8ae158cd TL	446	#endif
	447
	448	/* CPLD */
6d0f6bcf JCPV	449	#define CONFIG_SYS_CS2_BASE 0x08000000
	450	#define CONFIG_SYS_CS2_MASK 0x00070001
	451	#define CONFIG_SYS_CS2_CTRL 0x003f1140
8ae158cd TL	452
8ae158cd TL	453	/* FPGA */
6d0f6bcf JCPV	454	#define CONFIG_SYS_CS3_BASE 0x09000000
	455	#define CONFIG_SYS_CS3_MASK 0x00070001
	456	#define CONFIG_SYS_CS3_CTRL 0x00000020
8ae158cd	457
e8ee8f3a	458	#endif /* _M54455EVB_H */