[people/ms/u-boot.git] / include / configs / M54455EVB.h

/*
 * Configuation settings for the Freescale MCF54455 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54455EVB_H
#define _M54455EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M54455EVB	/* M54455EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#define LDS_BOARD_TEXT                  board/freescale/m54455evb/sbf_dram_init.o (.text*)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC1_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP 50000
#	define CONFIG_HAS_ETH1

#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		M54455EVB
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010013
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 1000000 3;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 0x30000;"	\
	"save\0"				\
	""
#else
/* Atmel and Intel */
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_UBOOT_END	0x0403FFFF
#elif defined(CONFIG_SYS_INTEL_BOOT)
#	define CONFIG_SYS_UBOOT_END	0x3FFFF
#endif
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${uboot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	""
#endif

/* ATA configuration */
#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT	1
#define CONFIG_ATAPI
#undef CONFIG_LBA48

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_BASE_ADDR	0x90000000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0

#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O                            */
#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers           */
#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers                 */

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x13
#ifdef CONFIG_CMD_SPI

#	define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	4

#define CONFIG_SYS_PCI_MEM_BUS		0xA0000000
#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#define CONFIG_SYS_PCI_IO_BUS		0xB1000000
#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE		0x01000000

#define CONFIG_SYS_PCI_CFG_BUS		0xB0000000
#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
#endif

/* FPGA - Spartan 2 */
/* experiment
#define CONFIG_FPGA_COUNT	1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
*/

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_BASE1		0x48000000
#define CONFIG_SYS_SDRAM_SIZE		256	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x65311610
#define CONFIG_SYS_SDRAM_CFG2		0x59670000
#define CONFIG_SYS_SDRAM_CTRL		0xEA0B2000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x00010033
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0xAA

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SERIAL_BOOT
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*
 * Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_SPI_CS		1
#endif
#undef CONFIG_ENV_OVERWRITE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_OFFSET		0x30000
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x20000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#	define CONFIG_FLASH_CFI_LEGACY

#ifdef CONFIG_FLASH_CFI_LEGACY
#	define CONFIG_SYS_ATMEL_REGION		4
#	define CONFIG_SYS_ATMEL_TOTALSECT	11
#	define CONFIG_SYS_ATMEL_SECT		{1, 2, 1, 7}
#	define CONFIG_SYS_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
#endif
#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#ifdef CF_STMICRO_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH2_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH1_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x500000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE		16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - CompactFlash and registers
 * CS2 - CPLD
 * CS3 - FPGA
 * CS4 - Available
 * CS5 - Available
 */

#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 /* Atmel Flash */
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00070001
#define CONFIG_SYS_CS0_CTRL		0x00001140
/* Intel Flash */
#define CONFIG_SYS_CS1_BASE		0x00000000
#define CONFIG_SYS_CS1_MASK		0x01FF0001
#define CONFIG_SYS_CS1_CTRL		0x00000D60

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS0_BASE
#else
/* Intel Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x01FF0001
#define CONFIG_SYS_CS0_CTRL		0x00000D60
 /* Atmel Flash */
#define CONFIG_SYS_CS1_BASE		0x04000000
#define CONFIG_SYS_CS1_MASK		0x00070001
#define CONFIG_SYS_CS1_CTRL		0x00001140

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS1_BASE
#endif

/* CPLD */
#define CONFIG_SYS_CS2_BASE		0x08000000
#define CONFIG_SYS_CS2_MASK		0x00070001
#define CONFIG_SYS_CS2_CTRL		0x003f1140

/* FPGA */
#define CONFIG_SYS_CS3_BASE		0x09000000
#define CONFIG_SYS_CS3_MASK		0x00070001
#define CONFIG_SYS_CS3_CTRL		0x00000020

#endif				/* _M54455EVB_H */
Commit	Line	Data
8ae158cd TL	1	/*
	2	* Configuation settings for the Freescale MCF54455 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
8ae158cd TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
e8ee8f3a TL	14	#ifndef _M54455EVB_H
e8ee8f3a TL	15	#define _M54455EVB_H
8ae158cd TL	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
8ae158cd TL	21	#define CONFIG_M54455EVB /* M54455EVB board */
8ae158cd TL	22
8ae158cd	23	#define CONFIG_MCFUART
6d0f6bcf	24	#define CONFIG_SYS_UART_PORT (0)
8ae158cd	25
c74dda8b AD	26	#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
c74dda8b AD	27
8ae158cd TL	28	#undef CONFIG_WATCHDOG
	29
	30	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	31
	32	/*
	33	* BOOTP options
	34	*/
	35	#define CONFIG_BOOTP_BOOTFILESIZE
	36	#define CONFIG_BOOTP_BOOTPATH
	37	#define CONFIG_BOOTP_GATEWAY
	38	#define CONFIG_BOOTP_HOSTNAME
	39
8ae158cd TL	40	/* Network configuration */
	41	#define CONFIG_MCFFEC
	42	#ifdef CONFIG_MCFFEC
8ae158cd	43	# define CONFIG_MII 1
0f3ba7e9	44	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	45	# define CONFIG_SYS_DISCOVER_PHY
	46	# define CONFIG_SYS_RX_ETH_BUFFER 8
	47	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	48
	49	# define CONFIG_SYS_FEC0_PINMUX 0
	50	# define CONFIG_SYS_FEC1_PINMUX 0
	51	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	52	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
8ae158cd TL	53	# define MCFFEC_TOUT_LOOP 50000
	54	# define CONFIG_HAS_ETH1
	55
8ae158cd TL	56	# define CONFIG_ETHPRIME "FEC0"
	57	# define CONFIG_IPADDR 192.162.1.2
	58	# define CONFIG_NETMASK 255.255.255.0
	59	# define CONFIG_SERVERIP 192.162.1.1
	60	# define CONFIG_GATEWAYIP 192.162.1.1
8ae158cd	61
6d0f6bcf JCPV	62	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	63	# ifndef CONFIG_SYS_DISCOVER_PHY
8ae158cd TL	64	# define FECDUPLEX FULL
	65	# define FECSPEED _100BASET
	66	# else
6d0f6bcf JCPV	67	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	68	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
8ae158cd	69	# endif
6d0f6bcf	70	# endif /* CONFIG_SYS_DISCOVER_PHY */
8ae158cd TL	71	#endif
	72
	73	#define CONFIG_HOSTNAME M54455EVB
6d0f6bcf	74	#ifdef CONFIG_SYS_STMICRO_BOOT
9f751551	75	/* ST Micro serial flash */
6d0f6bcf	76	#define CONFIG_SYS_LOAD_ADDR2 0x40010013
8ae158cd TL	77	#define CONFIG_EXTRA_ENV_SETTINGS \
8ae158cd TL	78	"netdev=eth0\0" \
5368c55d	79	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	80	"loadaddr=0x40010000\0" \
	81	"sbfhdr=sbfhdr.bin\0" \
	82	"uboot=u-boot.bin\0" \
	83	"load=tftp ${loadaddr} ${sbfhdr};" \
5368c55d	84	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
8ae158cd	85	"upd=run load; run prog\0" \
09933fb0	86	"prog=sf probe 0:1 1000000 3;" \
9f751551 TL	87	"sf erase 0 30000;" \
9f751551 TL	88	"sf write ${loadaddr} 0 0x30000;" \
8ae158cd TL	89	"save\0" \
8ae158cd TL	90	""
9f751551 TL	91	#else
9f751551 TL	92	/* Atmel and Intel */
6d0f6bcf JCPV	93	#ifdef CONFIG_SYS_ATMEL_BOOT
	94	# define CONFIG_SYS_UBOOT_END 0x0403FFFF
	95	#elif defined(CONFIG_SYS_INTEL_BOOT)
	96	# define CONFIG_SYS_UBOOT_END 0x3FFFF
9f751551 TL	97	#endif
	98	#define CONFIG_EXTRA_ENV_SETTINGS \
	99	"netdev=eth0\0" \
5368c55d	100	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	101	"loadaddr=0x40010000\0" \
	102	"uboot=u-boot.bin\0" \
	103	"load=tftp ${loadaddr} ${uboot}\0" \
	104	"upd=run load; run prog\0" \
5368c55d MV	105	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
	106	" " __stringify(CONFIG_SYS_UBOOT_END) ";" \
	107	"era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
	108	__stringify(CONFIG_SYS_UBOOT_END) ";" \
	109	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
9f751551 TL	110	" ${filesize}; save\0" \
	111	""
	112	#endif
8ae158cd TL	113
8ae158cd TL	114	/* ATA configuration */
8ae158cd TL	115	#define CONFIG_IDE_RESET 1
	116	#define CONFIG_IDE_PREINIT 1
	117	#define CONFIG_ATAPI
	118	#undef CONFIG_LBA48
	119
6d0f6bcf JCPV	120	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	121	#define CONFIG_SYS_IDE_MAXDEVICE 2
8ae158cd	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
6d0f6bcf JCPV	124	#define CONFIG_SYS_ATA_IDE0_OFFSET 0
8ae158cd	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	127	#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	128	#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	129	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
8ae158cd TL	130
	131	/* Realtime clock */
	132	#define CONFIG_MCFRTC
	133	#undef RTC_DEBUG
6d0f6bcf	134	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
8ae158cd TL	135
	136	/* Timer */
	137	#define CONFIG_MCFTMR
	138	#undef CONFIG_MCFPIT
	139
	140	/* I2c */
00f792e0 HS	141	#define CONFIG_SYS_I2C
	142	#define CONFIG_SYS_I2C_FSL
	143	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	144	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
6af3a0ea	145	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
6d0f6bcf	146	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
8ae158cd	147
bae61eef	148	/* DSPI and Serial Flash */
ee0a8462	149	#define CONFIG_CF_SPI
bae61eef	150	#define CONFIG_CF_DSPI
a7323bba	151	#define CONFIG_HARD_SPI
6d0f6bcf	152	#define CONFIG_SYS_SBFHDR_SIZE 0x13
a7323bba	153	#ifdef CONFIG_CMD_SPI
922cd751	154
ee0a8462 TL	155	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	156	DSPI_CTAR_PCSSCK_1CLK \| \
	157	DSPI_CTAR_PASC(0) \| \
	158	DSPI_CTAR_PDT(0) \| \
	159	DSPI_CTAR_CSSCK(0) \| \
	160	DSPI_CTAR_ASC(0) \| \
	161	DSPI_CTAR_DT(1))
a7323bba	162	#endif
bae61eef	163
8ae158cd	164	/* PCI */
e8ee8f3a	165	#ifdef CONFIG_CMD_PCI
f33fca22	166	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
2e72ad06	167
6d0f6bcf	168	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
8ae158cd	169
6d0f6bcf JCPV	170	#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
	171	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
	172	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
8ae158cd	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_PCI_IO_BUS 0xB1000000
	175	#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
	176	#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
8ae158cd	177
6d0f6bcf JCPV	178	#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
	179	#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
	180	#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
e8ee8f3a	181	#endif
8ae158cd TL	182
	183	/* FPGA - Spartan 2 */
	184	/* experiment
8ae158cd	185	#define CONFIG_FPGA_COUNT 1
6d0f6bcf JCPV	186	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
6d0f6bcf JCPV	187	#define CONFIG_SYS_FPGA_CHECK_CTRLC
8ae158cd TL	188	*/
	189
	190	/* Input, PCI, Flexbus, and VCO */
	191	#define CONFIG_EXTRA_CLOCK
	192
9f751551	193	#define CONFIG_PRAM 2048 /* 2048 KB */
8ae158cd	194
6d0f6bcf	195	#define CONFIG_SYS_LONGHELP /* undef to save memory */
8ae158cd	196
6d0f6bcf	197	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
8ae158cd	198
6d0f6bcf	199	#define CONFIG_SYS_MBAR 0xFC000000
8ae158cd TL	200
	201	/*
	202	* Low Level Configuration Settings
	203	* (address mappings, register initial values, etc.)
	204	* You should know what you are doing if you make changes here.
	205	*/
	206
	207	/*-----------------------------------------------------------------------
	208	* Definitions for initial stack pointer and data area (in DPRAM)
	209	*/
6d0f6bcf	210	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	211	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	212	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	213	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
6d0f6bcf	214	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
553f0982	215	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
8ae158cd TL	216
	217	/*-----------------------------------------------------------------------
	218	* Start addresses for the final memory configuration
	219	* (Set up by the startup code)
6d0f6bcf	220	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
8ae158cd	221	*/
6d0f6bcf JCPV	222	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	223	#define CONFIG_SYS_SDRAM_BASE1 0x48000000
	224	#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
	225	#define CONFIG_SYS_SDRAM_CFG1 0x65311610
	226	#define CONFIG_SYS_SDRAM_CFG2 0x59670000
	227	#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
	228	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	229	#define CONFIG_SYS_SDRAM_MODE 0x00010033
	230	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
	231
	232	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	233	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
8ae158cd	234
9f751551	235	#ifdef CONFIG_CF_SBF
09933fb0	236	# define CONFIG_SERIAL_BOOT
14d0a02a	237	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
9f751551	238	#else
6d0f6bcf	239	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
9f751551	240	#endif
6d0f6bcf JCPV	241	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	242	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
09933fb0 JJ	243
	244	/* Reserve 256 kB for malloc() */
	245	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
8ae158cd TL	246
	247	/*
	248	* For booting Linux, the board info and command line data
	249	* have to be in the first 8 MB of memory, since this is
	250	* the maximum mapped by the Linux kernel during initialization ??
	251	*/
	252	/* Initial Memory map for Linux */
6d0f6bcf	253	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
8ae158cd	254
9f751551 TL	255	/*
9f751551 TL	256	* Configuration for environment
09933fb0 JJ	257	* Environment is not embedded in u-boot. First time runing may have env
09933fb0 JJ	258	* crc error warning if there is no correct environment on the flash.
8ae158cd	259	*/
9f751551	260	#ifdef CONFIG_CF_SBF
0e8d1586	261	# define CONFIG_ENV_SPI_CS 1
9f751551 TL	262	#endif
9f751551 TL	263	#undef CONFIG_ENV_OVERWRITE
8ae158cd TL	264
	265	/*-----------------------------------------------------------------------
	266	* FLASH organization
	267	*/
6d0f6bcf	268	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462 TL	269	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
ee0a8462 TL	270	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
0e8d1586 JCPV	271	# define CONFIG_ENV_OFFSET 0x30000
	272	# define CONFIG_ENV_SIZE 0x2000
	273	# define CONFIG_ENV_SECT_SIZE 0x10000
9f751551	274	#endif
6d0f6bcf JCPV	275	#ifdef CONFIG_SYS_ATMEL_BOOT
	276	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	277	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	278	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
09933fb0 JJ	279	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
	280	# define CONFIG_ENV_SIZE 0x2000
	281	# define CONFIG_ENV_SECT_SIZE 0x10000
9f751551	282	#endif
6d0f6bcf JCPV	283	#ifdef CONFIG_SYS_INTEL_BOOT
	284	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	285	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	286	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
	287	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
0e8d1586 JCPV	288	# define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	289	# define CONFIG_ENV_SECT_SIZE 0x20000
8ae158cd TL	290	#endif
8ae158cd TL	291
6d0f6bcf JCPV	292	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	293	#ifdef CONFIG_SYS_FLASH_CFI
8ae158cd	294
00b1883a	295	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff	296	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
6d0f6bcf JCPV	297	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	298	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
	299	# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	300	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	301	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	302	# define CONFIG_SYS_FLASH_CHECKSUM
	303	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
b2d022d1	304	# define CONFIG_FLASH_CFI_LEGACY
8ae158cd	305
b2d022d1	306	#ifdef CONFIG_FLASH_CFI_LEGACY
6d0f6bcf JCPV	307	# define CONFIG_SYS_ATMEL_REGION 4
	308	# define CONFIG_SYS_ATMEL_TOTALSECT 11
	309	# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
	310	# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
bae61eef	311	#endif
8ae158cd TL	312	#endif
	313
	314	/*
	315	* This is setting for JFFS2 support in u-boot.
	316	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	317	*/
9f751551 TL	318	#ifdef CONFIG_CMD_JFFS2
	319	#ifdef CF_STMICRO_BOOT
	320	# define CONFIG_JFFS2_DEV "nor1"
	321	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	322	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
9f751551	323	#endif
6d0f6bcf	324	#ifdef CONFIG_SYS_ATMEL_BOOT
e8ee8f3a	325	# define CONFIG_JFFS2_DEV "nor1"
8ae158cd	326	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	327	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
9f751551	328	#endif
6d0f6bcf	329	#ifdef CONFIG_SYS_INTEL_BOOT
8ae158cd TL	330	# define CONFIG_JFFS2_DEV "nor0"
8ae158cd TL	331	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
6d0f6bcf	332	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
8ae158cd	333	#endif
9f751551	334	#endif
8ae158cd TL	335
	336	/*-----------------------------------------------------------------------
	337	* Cache Configuration
	338	*/
6d0f6bcf	339	#define CONFIG_SYS_CACHELINE_SIZE 16
8ae158cd	340
dd9f054e	341	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	342	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	343	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	344	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	345	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	346	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	347	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	348	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	349	CF_ACR_EN \| CF_ACR_SM_ALL)
	350	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	351	CF_CACR_ICINVA \| CF_CACR_EUSP)
	352	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	353	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	354	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	355
8ae158cd TL	356	/*-----------------------------------------------------------------------
	357	* Memory bank definitions
	358	*/
	359	/*
	360	* CS0 - NOR Flash 1, 2, 4, or 8MB
	361	* CS1 - CompactFlash and registers
	362	* CS2 - CPLD
	363	* CS3 - FPGA
	364	* CS4 - Available
	365	* CS5 - Available
	366	*/
	367
6d0f6bcf	368	#if defined(CONFIG_SYS_ATMEL_BOOT) \|\| defined(CONFIG_SYS_STMICRO_BOOT)
8ae158cd	369	/* Atmel Flash */
6d0f6bcf JCPV	370	#define CONFIG_SYS_CS0_BASE 0x04000000
	371	#define CONFIG_SYS_CS0_MASK 0x00070001
	372	#define CONFIG_SYS_CS0_CTRL 0x00001140
8ae158cd	373	/* Intel Flash */
6d0f6bcf JCPV	374	#define CONFIG_SYS_CS1_BASE 0x00000000
	375	#define CONFIG_SYS_CS1_MASK 0x01FF0001
	376	#define CONFIG_SYS_CS1_CTRL 0x00000D60
8ae158cd	377
6d0f6bcf	378	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
8ae158cd TL	379	#else
8ae158cd TL	380	/* Intel Flash */
6d0f6bcf JCPV	381	#define CONFIG_SYS_CS0_BASE 0x00000000
	382	#define CONFIG_SYS_CS0_MASK 0x01FF0001
	383	#define CONFIG_SYS_CS0_CTRL 0x00000D60
8ae158cd	384	/* Atmel Flash */
6d0f6bcf JCPV	385	#define CONFIG_SYS_CS1_BASE 0x04000000
	386	#define CONFIG_SYS_CS1_MASK 0x00070001
	387	#define CONFIG_SYS_CS1_CTRL 0x00001140
8ae158cd	388
6d0f6bcf	389	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
8ae158cd TL	390	#endif
	391
	392	/* CPLD */
6d0f6bcf JCPV	393	#define CONFIG_SYS_CS2_BASE 0x08000000
	394	#define CONFIG_SYS_CS2_MASK 0x00070001
	395	#define CONFIG_SYS_CS2_CTRL 0x003f1140
8ae158cd TL	396
8ae158cd TL	397	/* FPGA */
6d0f6bcf JCPV	398	#define CONFIG_SYS_CS3_BASE 0x09000000
	399	#define CONFIG_SYS_CS3_MASK 0x00070001
	400	#define CONFIG_SYS_CS3_CTRL 0x00000020
8ae158cd	401
e8ee8f3a	402	#endif /* _M54455EVB_H */