[people/ms/u-boot.git] / include / configs / M54455EVB.h

/*
 * Configuation settings for the Freescale MCF54455 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54455EVB_H
#define _M54455EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M54455EVB	/* M54455EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#undef CONFIG_CMD_PCI
#define CONFIG_CMD_REGINFO

/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC1_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP 50000
#	define CONFIG_HAS_ETH1

#	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		M54455EVB
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010013
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 1000000 3;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 0x30000;"	\
	"save\0"				\
	""
#else
/* Atmel and Intel */
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_UBOOT_END	0x0403FFFF
#elif defined(CONFIG_SYS_INTEL_BOOT)
#	define CONFIG_SYS_UBOOT_END	0x3FFFF
#endif
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${uboot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	""
#endif

/* ATA configuration */
#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT	1
#define CONFIG_ATAPI
#undef CONFIG_LBA48

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_BASE_ADDR	0x90000000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0

#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O                            */
#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers           */
#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers                 */

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x13
#ifdef CONFIG_CMD_SPI

#	define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	4

#define CONFIG_SYS_PCI_MEM_BUS		0xA0000000
#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#define CONFIG_SYS_PCI_IO_BUS		0xB1000000
#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE		0x01000000

#define CONFIG_SYS_PCI_CFG_BUS		0xB0000000
#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
#endif

/* FPGA - Spartan 2 */
/* experiment
#define CONFIG_FPGA
#define CONFIG_FPGA_COUNT	1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
*/

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_BASE1		0x48000000
#define CONFIG_SYS_SDRAM_SIZE		256	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x65311610
#define CONFIG_SYS_SDRAM_CFG2		0x59670000
#define CONFIG_SYS_SDRAM_CTRL		0xEA0B2000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x00010033
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0xAA

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SERIAL_BOOT
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*
 * Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_IS_IN_SPI_FLASH
#	define CONFIG_ENV_SPI_CS		1
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif
#undef CONFIG_ENV_OVERWRITE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_OFFSET		0x30000
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x20000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#	define CONFIG_FLASH_CFI_LEGACY

#ifdef CONFIG_FLASH_CFI_LEGACY
#	define CONFIG_SYS_ATMEL_REGION		4
#	define CONFIG_SYS_ATMEL_TOTALSECT	11
#	define CONFIG_SYS_ATMEL_SECT		{1, 2, 1, 7}
#	define CONFIG_SYS_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
#endif
#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#ifdef CF_STMICRO_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH2_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH1_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x500000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE		16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - CompactFlash and registers
 * CS2 - CPLD
 * CS3 - FPGA
 * CS4 - Available
 * CS5 - Available
 */

#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 /* Atmel Flash */
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00070001
#define CONFIG_SYS_CS0_CTRL		0x00001140
/* Intel Flash */
#define CONFIG_SYS_CS1_BASE		0x00000000
#define CONFIG_SYS_CS1_MASK		0x01FF0001
#define CONFIG_SYS_CS1_CTRL		0x00000D60

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS0_BASE
#else
/* Intel Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x01FF0001
#define CONFIG_SYS_CS0_CTRL		0x00000D60
 /* Atmel Flash */
#define CONFIG_SYS_CS1_BASE		0x04000000
#define CONFIG_SYS_CS1_MASK		0x00070001
#define CONFIG_SYS_CS1_CTRL		0x00001140

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS1_BASE
#endif

/* CPLD */
#define CONFIG_SYS_CS2_BASE		0x08000000
#define CONFIG_SYS_CS2_MASK		0x00070001
#define CONFIG_SYS_CS2_CTRL		0x003f1140

/* FPGA */
#define CONFIG_SYS_CS3_BASE		0x09000000
#define CONFIG_SYS_CS3_MASK		0x00070001
#define CONFIG_SYS_CS3_CTRL		0x00000020

#endif				/* _M54455EVB_H */
Commit	Line	Data
8ae158cd TL	1	/*
	2	* Configuation settings for the Freescale MCF54455 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
8ae158cd TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
e8ee8f3a TL	14	#ifndef _M54455EVB_H
e8ee8f3a TL	15	#define _M54455EVB_H
8ae158cd TL	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
8ae158cd TL	21	#define CONFIG_M54455EVB /* M54455EVB board */
8ae158cd TL	22
8ae158cd	23	#define CONFIG_MCFUART
6d0f6bcf	24	#define CONFIG_SYS_UART_PORT (0)
8ae158cd TL	25
	26	#undef CONFIG_WATCHDOG
	27
	28	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	29
	30	/*
	31	* BOOTP options
	32	*/
	33	#define CONFIG_BOOTP_BOOTFILESIZE
	34	#define CONFIG_BOOTP_BOOTPATH
	35	#define CONFIG_BOOTP_GATEWAY
	36	#define CONFIG_BOOTP_HOSTNAME
	37
	38	/* Command line configuration */
e8ee8f3a	39	#undef CONFIG_CMD_PCI
8ae158cd	40	#define CONFIG_CMD_REGINFO
8ae158cd TL	41
	42	/* Network configuration */
	43	#define CONFIG_MCFFEC
	44	#ifdef CONFIG_MCFFEC
8ae158cd	45	# define CONFIG_MII 1
0f3ba7e9	46	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	47	# define CONFIG_SYS_DISCOVER_PHY
	48	# define CONFIG_SYS_RX_ETH_BUFFER 8
	49	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	50
	51	# define CONFIG_SYS_FEC0_PINMUX 0
	52	# define CONFIG_SYS_FEC1_PINMUX 0
	53	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	54	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
8ae158cd TL	55	# define MCFFEC_TOUT_LOOP 50000
	56	# define CONFIG_HAS_ETH1
	57
8ae158cd	58	# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
8ae158cd TL	59	# define CONFIG_ETHPRIME "FEC0"
	60	# define CONFIG_IPADDR 192.162.1.2
	61	# define CONFIG_NETMASK 255.255.255.0
	62	# define CONFIG_SERVERIP 192.162.1.1
	63	# define CONFIG_GATEWAYIP 192.162.1.1
8ae158cd	64
6d0f6bcf JCPV	65	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	66	# ifndef CONFIG_SYS_DISCOVER_PHY
8ae158cd TL	67	# define FECDUPLEX FULL
	68	# define FECSPEED _100BASET
	69	# else
6d0f6bcf JCPV	70	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	71	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
8ae158cd	72	# endif
6d0f6bcf	73	# endif /* CONFIG_SYS_DISCOVER_PHY */
8ae158cd TL	74	#endif
	75
	76	#define CONFIG_HOSTNAME M54455EVB
6d0f6bcf	77	#ifdef CONFIG_SYS_STMICRO_BOOT
9f751551	78	/* ST Micro serial flash */
6d0f6bcf	79	#define CONFIG_SYS_LOAD_ADDR2 0x40010013
8ae158cd TL	80	#define CONFIG_EXTRA_ENV_SETTINGS \
8ae158cd TL	81	"netdev=eth0\0" \
5368c55d	82	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	83	"loadaddr=0x40010000\0" \
	84	"sbfhdr=sbfhdr.bin\0" \
	85	"uboot=u-boot.bin\0" \
	86	"load=tftp ${loadaddr} ${sbfhdr};" \
5368c55d	87	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
8ae158cd	88	"upd=run load; run prog\0" \
09933fb0	89	"prog=sf probe 0:1 1000000 3;" \
9f751551 TL	90	"sf erase 0 30000;" \
9f751551 TL	91	"sf write ${loadaddr} 0 0x30000;" \
8ae158cd TL	92	"save\0" \
8ae158cd TL	93	""
9f751551 TL	94	#else
9f751551 TL	95	/* Atmel and Intel */
6d0f6bcf JCPV	96	#ifdef CONFIG_SYS_ATMEL_BOOT
	97	# define CONFIG_SYS_UBOOT_END 0x0403FFFF
	98	#elif defined(CONFIG_SYS_INTEL_BOOT)
	99	# define CONFIG_SYS_UBOOT_END 0x3FFFF
9f751551 TL	100	#endif
	101	#define CONFIG_EXTRA_ENV_SETTINGS \
	102	"netdev=eth0\0" \
5368c55d	103	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	104	"loadaddr=0x40010000\0" \
	105	"uboot=u-boot.bin\0" \
	106	"load=tftp ${loadaddr} ${uboot}\0" \
	107	"upd=run load; run prog\0" \
5368c55d MV	108	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
	109	" " __stringify(CONFIG_SYS_UBOOT_END) ";" \
	110	"era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
	111	__stringify(CONFIG_SYS_UBOOT_END) ";" \
	112	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
9f751551 TL	113	" ${filesize}; save\0" \
	114	""
	115	#endif
8ae158cd TL	116
8ae158cd TL	117	/* ATA configuration */
8ae158cd TL	118	#define CONFIG_IDE_RESET 1
	119	#define CONFIG_IDE_PREINIT 1
	120	#define CONFIG_ATAPI
	121	#undef CONFIG_LBA48
	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	124	#define CONFIG_SYS_IDE_MAXDEVICE 2
8ae158cd	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
6d0f6bcf JCPV	127	#define CONFIG_SYS_ATA_IDE0_OFFSET 0
8ae158cd	128
6d0f6bcf JCPV	129	#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	130	#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	131	#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	132	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
8ae158cd TL	133
	134	/* Realtime clock */
	135	#define CONFIG_MCFRTC
	136	#undef RTC_DEBUG
6d0f6bcf	137	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
8ae158cd TL	138
	139	/* Timer */
	140	#define CONFIG_MCFTMR
	141	#undef CONFIG_MCFPIT
	142
	143	/* I2c */
00f792e0 HS	144	#define CONFIG_SYS_I2C
	145	#define CONFIG_SYS_I2C_FSL
	146	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	147	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
6af3a0ea	148	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
6d0f6bcf	149	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
8ae158cd	150
bae61eef	151	/* DSPI and Serial Flash */
ee0a8462	152	#define CONFIG_CF_SPI
bae61eef	153	#define CONFIG_CF_DSPI
a7323bba	154	#define CONFIG_HARD_SPI
6d0f6bcf	155	#define CONFIG_SYS_SBFHDR_SIZE 0x13
a7323bba	156	#ifdef CONFIG_CMD_SPI
922cd751	157
ee0a8462 TL	158	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	159	DSPI_CTAR_PCSSCK_1CLK \| \
	160	DSPI_CTAR_PASC(0) \| \
	161	DSPI_CTAR_PDT(0) \| \
	162	DSPI_CTAR_CSSCK(0) \| \
	163	DSPI_CTAR_ASC(0) \| \
	164	DSPI_CTAR_DT(1))
a7323bba	165	#endif
bae61eef	166
8ae158cd	167	/* PCI */
e8ee8f3a	168	#ifdef CONFIG_CMD_PCI
f33fca22	169	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
2e72ad06	170
6d0f6bcf	171	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
8ae158cd	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
	174	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
	175	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
8ae158cd	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_PCI_IO_BUS 0xB1000000
	178	#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
	179	#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
8ae158cd	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
	182	#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
	183	#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
e8ee8f3a	184	#endif
8ae158cd TL	185
	186	/* FPGA - Spartan 2 */
	187	/* experiment
b03b25ca	188	#define CONFIG_FPGA
8ae158cd	189	#define CONFIG_FPGA_COUNT 1
6d0f6bcf JCPV	190	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
6d0f6bcf JCPV	191	#define CONFIG_SYS_FPGA_CHECK_CTRLC
8ae158cd TL	192	*/
	193
	194	/* Input, PCI, Flexbus, and VCO */
	195	#define CONFIG_EXTRA_CLOCK
	196
9f751551	197	#define CONFIG_PRAM 2048 /* 2048 KB */
8ae158cd	198
6d0f6bcf	199	#define CONFIG_SYS_LONGHELP /* undef to save memory */
8ae158cd TL	200
8ae158cd TL	201	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	202	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
8ae158cd	203	#else
6d0f6bcf	204	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
8ae158cd	205	#endif
6d0f6bcf JCPV	206	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	207	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	208	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
8ae158cd	209
6d0f6bcf	210	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
8ae158cd	211
6d0f6bcf	212	#define CONFIG_SYS_MBAR 0xFC000000
8ae158cd TL	213
	214	/*
	215	* Low Level Configuration Settings
	216	* (address mappings, register initial values, etc.)
	217	* You should know what you are doing if you make changes here.
	218	*/
	219
	220	/*-----------------------------------------------------------------------
	221	* Definitions for initial stack pointer and data area (in DPRAM)
	222	*/
6d0f6bcf	223	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	224	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	225	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	226	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
6d0f6bcf	227	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
553f0982	228	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
8ae158cd TL	229
	230	/*-----------------------------------------------------------------------
	231	* Start addresses for the final memory configuration
	232	* (Set up by the startup code)
6d0f6bcf	233	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
8ae158cd	234	*/
6d0f6bcf JCPV	235	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	236	#define CONFIG_SYS_SDRAM_BASE1 0x48000000
	237	#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
	238	#define CONFIG_SYS_SDRAM_CFG1 0x65311610
	239	#define CONFIG_SYS_SDRAM_CFG2 0x59670000
	240	#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
	241	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	242	#define CONFIG_SYS_SDRAM_MODE 0x00010033
	243	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
	244
	245	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	246	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
8ae158cd	247
9f751551	248	#ifdef CONFIG_CF_SBF
09933fb0	249	# define CONFIG_SERIAL_BOOT
14d0a02a	250	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
9f751551	251	#else
6d0f6bcf	252	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
9f751551	253	#endif
6d0f6bcf JCPV	254	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	255	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
09933fb0 JJ	256
	257	/* Reserve 256 kB for malloc() */
	258	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
8ae158cd TL	259
	260	/*
	261	* For booting Linux, the board info and command line data
	262	* have to be in the first 8 MB of memory, since this is
	263	* the maximum mapped by the Linux kernel during initialization ??
	264	*/
	265	/* Initial Memory map for Linux */
6d0f6bcf	266	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
8ae158cd	267
9f751551 TL	268	/*
9f751551 TL	269	* Configuration for environment
09933fb0 JJ	270	* Environment is not embedded in u-boot. First time runing may have env
09933fb0 JJ	271	* crc error warning if there is no correct environment on the flash.
8ae158cd	272	*/
9f751551	273	#ifdef CONFIG_CF_SBF
0b5099a8	274	# define CONFIG_ENV_IS_IN_SPI_FLASH
0e8d1586	275	# define CONFIG_ENV_SPI_CS 1
9f751551	276	#else
5a1aceb0	277	# define CONFIG_ENV_IS_IN_FLASH 1
9f751551 TL	278	#endif
9f751551 TL	279	#undef CONFIG_ENV_OVERWRITE
8ae158cd TL	280
	281	/*-----------------------------------------------------------------------
	282	* FLASH organization
	283	*/
6d0f6bcf	284	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462 TL	285	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
ee0a8462 TL	286	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
0e8d1586 JCPV	287	# define CONFIG_ENV_OFFSET 0x30000
	288	# define CONFIG_ENV_SIZE 0x2000
	289	# define CONFIG_ENV_SECT_SIZE 0x10000
9f751551	290	#endif
6d0f6bcf JCPV	291	#ifdef CONFIG_SYS_ATMEL_BOOT
	292	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	293	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	294	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
09933fb0 JJ	295	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
	296	# define CONFIG_ENV_SIZE 0x2000
	297	# define CONFIG_ENV_SECT_SIZE 0x10000
9f751551	298	#endif
6d0f6bcf JCPV	299	#ifdef CONFIG_SYS_INTEL_BOOT
	300	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	301	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	302	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
	303	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
0e8d1586 JCPV	304	# define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	305	# define CONFIG_ENV_SECT_SIZE 0x20000
8ae158cd TL	306	#endif
8ae158cd TL	307
6d0f6bcf JCPV	308	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	309	#ifdef CONFIG_SYS_FLASH_CFI
8ae158cd	310
00b1883a	311	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff	312	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
6d0f6bcf JCPV	313	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	314	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
	315	# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	316	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	317	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	318	# define CONFIG_SYS_FLASH_CHECKSUM
	319	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
b2d022d1	320	# define CONFIG_FLASH_CFI_LEGACY
8ae158cd	321
b2d022d1	322	#ifdef CONFIG_FLASH_CFI_LEGACY
6d0f6bcf JCPV	323	# define CONFIG_SYS_ATMEL_REGION 4
	324	# define CONFIG_SYS_ATMEL_TOTALSECT 11
	325	# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
	326	# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
bae61eef	327	#endif
8ae158cd TL	328	#endif
	329
	330	/*
	331	* This is setting for JFFS2 support in u-boot.
	332	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	333	*/
9f751551 TL	334	#ifdef CONFIG_CMD_JFFS2
	335	#ifdef CF_STMICRO_BOOT
	336	# define CONFIG_JFFS2_DEV "nor1"
	337	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	338	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
9f751551	339	#endif
6d0f6bcf	340	#ifdef CONFIG_SYS_ATMEL_BOOT
e8ee8f3a	341	# define CONFIG_JFFS2_DEV "nor1"
8ae158cd	342	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	343	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
9f751551	344	#endif
6d0f6bcf	345	#ifdef CONFIG_SYS_INTEL_BOOT
8ae158cd TL	346	# define CONFIG_JFFS2_DEV "nor0"
8ae158cd TL	347	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
6d0f6bcf	348	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
8ae158cd	349	#endif
9f751551	350	#endif
8ae158cd TL	351
	352	/*-----------------------------------------------------------------------
	353	* Cache Configuration
	354	*/
6d0f6bcf	355	#define CONFIG_SYS_CACHELINE_SIZE 16
8ae158cd	356
dd9f054e	357	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	358	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	359	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	360	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	361	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	362	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	363	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	364	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	365	CF_ACR_EN \| CF_ACR_SM_ALL)
	366	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	367	CF_CACR_ICINVA \| CF_CACR_EUSP)
	368	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	369	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	370	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	371
8ae158cd TL	372	/*-----------------------------------------------------------------------
	373	* Memory bank definitions
	374	*/
	375	/*
	376	* CS0 - NOR Flash 1, 2, 4, or 8MB
	377	* CS1 - CompactFlash and registers
	378	* CS2 - CPLD
	379	* CS3 - FPGA
	380	* CS4 - Available
	381	* CS5 - Available
	382	*/
	383
6d0f6bcf	384	#if defined(CONFIG_SYS_ATMEL_BOOT) \|\| defined(CONFIG_SYS_STMICRO_BOOT)
8ae158cd	385	/* Atmel Flash */
6d0f6bcf JCPV	386	#define CONFIG_SYS_CS0_BASE 0x04000000
	387	#define CONFIG_SYS_CS0_MASK 0x00070001
	388	#define CONFIG_SYS_CS0_CTRL 0x00001140
8ae158cd	389	/* Intel Flash */
6d0f6bcf JCPV	390	#define CONFIG_SYS_CS1_BASE 0x00000000
	391	#define CONFIG_SYS_CS1_MASK 0x01FF0001
	392	#define CONFIG_SYS_CS1_CTRL 0x00000D60
8ae158cd	393
6d0f6bcf	394	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
8ae158cd TL	395	#else
8ae158cd TL	396	/* Intel Flash */
6d0f6bcf JCPV	397	#define CONFIG_SYS_CS0_BASE 0x00000000
	398	#define CONFIG_SYS_CS0_MASK 0x01FF0001
	399	#define CONFIG_SYS_CS0_CTRL 0x00000D60
8ae158cd	400	/* Atmel Flash */
6d0f6bcf JCPV	401	#define CONFIG_SYS_CS1_BASE 0x04000000
	402	#define CONFIG_SYS_CS1_MASK 0x00070001
	403	#define CONFIG_SYS_CS1_CTRL 0x00001140
8ae158cd	404
6d0f6bcf	405	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
8ae158cd TL	406	#endif
	407
	408	/* CPLD */
6d0f6bcf JCPV	409	#define CONFIG_SYS_CS2_BASE 0x08000000
	410	#define CONFIG_SYS_CS2_MASK 0x00070001
	411	#define CONFIG_SYS_CS2_CTRL 0x003f1140
8ae158cd TL	412
8ae158cd TL	413	/* FPGA */
6d0f6bcf JCPV	414	#define CONFIG_SYS_CS3_BASE 0x09000000
	415	#define CONFIG_SYS_CS3_MASK 0x00070001
	416	#define CONFIG_SYS_CS3_CTRL 0x00000020
8ae158cd	417
e8ee8f3a	418	#endif /* _M54455EVB_H */