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8ae158cd TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF54455 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
8ae158cd TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
e8ee8f3a TL |
14 | #ifndef _M54455EVB_H |
15 | #define _M54455EVB_H | |
8ae158cd TL |
16 | |
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
8ae158cd TL |
21 | #define CONFIG_M54455EVB /* M54455EVB board */ |
22 | ||
8ae158cd | 23 | #define CONFIG_MCFUART |
6d0f6bcf | 24 | #define CONFIG_SYS_UART_PORT (0) |
8ae158cd | 25 | #define CONFIG_BAUDRATE 115200 |
8ae158cd TL |
26 | |
27 | #undef CONFIG_WATCHDOG | |
28 | ||
29 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
30 | ||
31 | /* | |
32 | * BOOTP options | |
33 | */ | |
34 | #define CONFIG_BOOTP_BOOTFILESIZE | |
35 | #define CONFIG_BOOTP_BOOTPATH | |
36 | #define CONFIG_BOOTP_GATEWAY | |
37 | #define CONFIG_BOOTP_HOSTNAME | |
38 | ||
39 | /* Command line configuration */ | |
8ae158cd | 40 | #define CONFIG_CMD_DATE |
8ae158cd TL |
41 | #define CONFIG_CMD_IDE |
42 | #define CONFIG_CMD_JFFS2 | |
e8ee8f3a | 43 | #undef CONFIG_CMD_PCI |
8ae158cd | 44 | #define CONFIG_CMD_REGINFO |
8ae158cd TL |
45 | |
46 | /* Network configuration */ | |
47 | #define CONFIG_MCFFEC | |
48 | #ifdef CONFIG_MCFFEC | |
8ae158cd | 49 | # define CONFIG_MII 1 |
0f3ba7e9 | 50 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
51 | # define CONFIG_SYS_DISCOVER_PHY |
52 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
53 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
54 | ||
55 | # define CONFIG_SYS_FEC0_PINMUX 0 | |
56 | # define CONFIG_SYS_FEC1_PINMUX 0 | |
57 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
58 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
8ae158cd TL |
59 | # define MCFFEC_TOUT_LOOP 50000 |
60 | # define CONFIG_HAS_ETH1 | |
61 | ||
8ae158cd | 62 | # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" |
8ae158cd TL |
63 | # define CONFIG_ETHPRIME "FEC0" |
64 | # define CONFIG_IPADDR 192.162.1.2 | |
65 | # define CONFIG_NETMASK 255.255.255.0 | |
66 | # define CONFIG_SERVERIP 192.162.1.1 | |
67 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
8ae158cd | 68 | |
6d0f6bcf JCPV |
69 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
70 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
8ae158cd TL |
71 | # define FECDUPLEX FULL |
72 | # define FECSPEED _100BASET | |
73 | # else | |
6d0f6bcf JCPV |
74 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
75 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8ae158cd | 76 | # endif |
6d0f6bcf | 77 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
8ae158cd TL |
78 | #endif |
79 | ||
80 | #define CONFIG_HOSTNAME M54455EVB | |
6d0f6bcf | 81 | #ifdef CONFIG_SYS_STMICRO_BOOT |
9f751551 | 82 | /* ST Micro serial flash */ |
6d0f6bcf | 83 | #define CONFIG_SYS_LOAD_ADDR2 0x40010013 |
8ae158cd TL |
84 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
85 | "netdev=eth0\0" \ | |
5368c55d | 86 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
87 | "loadaddr=0x40010000\0" \ |
88 | "sbfhdr=sbfhdr.bin\0" \ | |
89 | "uboot=u-boot.bin\0" \ | |
90 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
5368c55d | 91 | "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ |
8ae158cd | 92 | "upd=run load; run prog\0" \ |
09933fb0 | 93 | "prog=sf probe 0:1 1000000 3;" \ |
9f751551 TL |
94 | "sf erase 0 30000;" \ |
95 | "sf write ${loadaddr} 0 0x30000;" \ | |
8ae158cd TL |
96 | "save\0" \ |
97 | "" | |
9f751551 TL |
98 | #else |
99 | /* Atmel and Intel */ | |
6d0f6bcf JCPV |
100 | #ifdef CONFIG_SYS_ATMEL_BOOT |
101 | # define CONFIG_SYS_UBOOT_END 0x0403FFFF | |
102 | #elif defined(CONFIG_SYS_INTEL_BOOT) | |
103 | # define CONFIG_SYS_UBOOT_END 0x3FFFF | |
9f751551 TL |
104 | #endif |
105 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
106 | "netdev=eth0\0" \ | |
5368c55d | 107 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
108 | "loadaddr=0x40010000\0" \ |
109 | "uboot=u-boot.bin\0" \ | |
110 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
111 | "upd=run load; run prog\0" \ | |
5368c55d MV |
112 | "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
113 | " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
114 | "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ | |
115 | __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
116 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
9f751551 TL |
117 | " ${filesize}; save\0" \ |
118 | "" | |
119 | #endif | |
8ae158cd TL |
120 | |
121 | /* ATA configuration */ | |
122 | #define CONFIG_ISO_PARTITION | |
123 | #define CONFIG_DOS_PARTITION | |
124 | #define CONFIG_IDE_RESET 1 | |
125 | #define CONFIG_IDE_PREINIT 1 | |
126 | #define CONFIG_ATAPI | |
127 | #undef CONFIG_LBA48 | |
128 | ||
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_IDE_MAXBUS 1 |
130 | #define CONFIG_SYS_IDE_MAXDEVICE 2 | |
8ae158cd | 131 | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 |
133 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
8ae158cd | 134 | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
136 | #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
137 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
138 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
8ae158cd TL |
139 | |
140 | /* Realtime clock */ | |
141 | #define CONFIG_MCFRTC | |
142 | #undef RTC_DEBUG | |
6d0f6bcf | 143 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
8ae158cd TL |
144 | |
145 | /* Timer */ | |
146 | #define CONFIG_MCFTMR | |
147 | #undef CONFIG_MCFPIT | |
148 | ||
149 | /* I2c */ | |
00f792e0 HS |
150 | #define CONFIG_SYS_I2C |
151 | #define CONFIG_SYS_I2C_FSL | |
152 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
153 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
6af3a0ea | 154 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 |
6d0f6bcf | 155 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
8ae158cd | 156 | |
bae61eef | 157 | /* DSPI and Serial Flash */ |
ee0a8462 | 158 | #define CONFIG_CF_SPI |
bae61eef | 159 | #define CONFIG_CF_DSPI |
a7323bba | 160 | #define CONFIG_HARD_SPI |
6d0f6bcf | 161 | #define CONFIG_SYS_SBFHDR_SIZE 0x13 |
a7323bba | 162 | #ifdef CONFIG_CMD_SPI |
922cd751 | 163 | |
ee0a8462 TL |
164 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
165 | DSPI_CTAR_PCSSCK_1CLK | \ | |
166 | DSPI_CTAR_PASC(0) | \ | |
167 | DSPI_CTAR_PDT(0) | \ | |
168 | DSPI_CTAR_CSSCK(0) | \ | |
169 | DSPI_CTAR_ASC(0) | \ | |
170 | DSPI_CTAR_DT(1)) | |
a7323bba | 171 | #endif |
bae61eef | 172 | |
8ae158cd | 173 | /* PCI */ |
e8ee8f3a | 174 | #ifdef CONFIG_CMD_PCI |
8ae158cd | 175 | #define CONFIG_PCI 1 |
2e72ad06 | 176 | #define CONFIG_PCI_PNP 1 |
f33fca22 | 177 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2e72ad06 | 178 | |
6d0f6bcf | 179 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 |
8ae158cd | 180 | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 |
182 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS | |
183 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 | |
8ae158cd | 184 | |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 |
186 | #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS | |
187 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 | |
8ae158cd | 188 | |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 |
190 | #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS | |
191 | #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 | |
e8ee8f3a | 192 | #endif |
8ae158cd TL |
193 | |
194 | /* FPGA - Spartan 2 */ | |
195 | /* experiment | |
b03b25ca | 196 | #define CONFIG_FPGA |
8ae158cd | 197 | #define CONFIG_FPGA_COUNT 1 |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_FPGA_PROG_FEEDBACK |
199 | #define CONFIG_SYS_FPGA_CHECK_CTRLC | |
8ae158cd TL |
200 | */ |
201 | ||
202 | /* Input, PCI, Flexbus, and VCO */ | |
203 | #define CONFIG_EXTRA_CLOCK | |
204 | ||
9f751551 | 205 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
8ae158cd | 206 | |
6d0f6bcf | 207 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
8ae158cd TL |
208 | |
209 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 210 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8ae158cd | 211 | #else |
6d0f6bcf | 212 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8ae158cd | 213 | #endif |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
215 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
216 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8ae158cd | 217 | |
6d0f6bcf | 218 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
8ae158cd | 219 | |
6d0f6bcf | 220 | #define CONFIG_SYS_MBAR 0xFC000000 |
8ae158cd TL |
221 | |
222 | /* | |
223 | * Low Level Configuration Settings | |
224 | * (address mappings, register initial values, etc.) | |
225 | * You should know what you are doing if you make changes here. | |
226 | */ | |
227 | ||
228 | /*----------------------------------------------------------------------- | |
229 | * Definitions for initial stack pointer and data area (in DPRAM) | |
230 | */ | |
6d0f6bcf | 231 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 232 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 233 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 234 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
6d0f6bcf | 235 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
553f0982 | 236 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
8ae158cd TL |
237 | |
238 | /*----------------------------------------------------------------------- | |
239 | * Start addresses for the final memory configuration | |
240 | * (Set up by the startup code) | |
6d0f6bcf | 241 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
8ae158cd | 242 | */ |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
244 | #define CONFIG_SYS_SDRAM_BASE1 0x48000000 | |
245 | #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ | |
246 | #define CONFIG_SYS_SDRAM_CFG1 0x65311610 | |
247 | #define CONFIG_SYS_SDRAM_CFG2 0x59670000 | |
248 | #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 | |
249 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
250 | #define CONFIG_SYS_SDRAM_MODE 0x00010033 | |
251 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA | |
252 | ||
253 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
254 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
8ae158cd | 255 | |
9f751551 | 256 | #ifdef CONFIG_CF_SBF |
09933fb0 | 257 | # define CONFIG_SERIAL_BOOT |
14d0a02a | 258 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
9f751551 | 259 | #else |
6d0f6bcf | 260 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
9f751551 | 261 | #endif |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
263 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
09933fb0 JJ |
264 | |
265 | /* Reserve 256 kB for malloc() */ | |
266 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
8ae158cd TL |
267 | |
268 | /* | |
269 | * For booting Linux, the board info and command line data | |
270 | * have to be in the first 8 MB of memory, since this is | |
271 | * the maximum mapped by the Linux kernel during initialization ?? | |
272 | */ | |
273 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 274 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
8ae158cd | 275 | |
9f751551 TL |
276 | /* |
277 | * Configuration for environment | |
09933fb0 JJ |
278 | * Environment is not embedded in u-boot. First time runing may have env |
279 | * crc error warning if there is no correct environment on the flash. | |
8ae158cd | 280 | */ |
9f751551 | 281 | #ifdef CONFIG_CF_SBF |
0b5099a8 | 282 | # define CONFIG_ENV_IS_IN_SPI_FLASH |
0e8d1586 | 283 | # define CONFIG_ENV_SPI_CS 1 |
9f751551 | 284 | #else |
5a1aceb0 | 285 | # define CONFIG_ENV_IS_IN_FLASH 1 |
9f751551 TL |
286 | #endif |
287 | #undef CONFIG_ENV_OVERWRITE | |
8ae158cd TL |
288 | |
289 | /*----------------------------------------------------------------------- | |
290 | * FLASH organization | |
291 | */ | |
6d0f6bcf | 292 | #ifdef CONFIG_SYS_STMICRO_BOOT |
ee0a8462 TL |
293 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
294 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE | |
0e8d1586 JCPV |
295 | # define CONFIG_ENV_OFFSET 0x30000 |
296 | # define CONFIG_ENV_SIZE 0x2000 | |
297 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 298 | #endif |
6d0f6bcf JCPV |
299 | #ifdef CONFIG_SYS_ATMEL_BOOT |
300 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
301 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
302 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
09933fb0 JJ |
303 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
304 | # define CONFIG_ENV_SIZE 0x2000 | |
305 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 306 | #endif |
6d0f6bcf JCPV |
307 | #ifdef CONFIG_SYS_INTEL_BOOT |
308 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
309 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
310 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
311 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) | |
0e8d1586 JCPV |
312 | # define CONFIG_ENV_SIZE 0x2000 |
313 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
8ae158cd TL |
314 | #endif |
315 | ||
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_FLASH_CFI |
317 | #ifdef CONFIG_SYS_FLASH_CFI | |
8ae158cd | 318 | |
00b1883a | 319 | # define CONFIG_FLASH_CFI_DRIVER 1 |
bbf6bbff | 320 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
6d0f6bcf JCPV |
321 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
322 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
323 | # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
324 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
325 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
326 | # define CONFIG_SYS_FLASH_CHECKSUM | |
327 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } | |
b2d022d1 | 328 | # define CONFIG_FLASH_CFI_LEGACY |
8ae158cd | 329 | |
b2d022d1 | 330 | #ifdef CONFIG_FLASH_CFI_LEGACY |
6d0f6bcf JCPV |
331 | # define CONFIG_SYS_ATMEL_REGION 4 |
332 | # define CONFIG_SYS_ATMEL_TOTALSECT 11 | |
333 | # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} | |
334 | # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} | |
bae61eef | 335 | #endif |
8ae158cd TL |
336 | #endif |
337 | ||
338 | /* | |
339 | * This is setting for JFFS2 support in u-boot. | |
340 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
341 | */ | |
9f751551 TL |
342 | #ifdef CONFIG_CMD_JFFS2 |
343 | #ifdef CF_STMICRO_BOOT | |
344 | # define CONFIG_JFFS2_DEV "nor1" | |
345 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
6d0f6bcf | 346 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) |
9f751551 | 347 | #endif |
6d0f6bcf | 348 | #ifdef CONFIG_SYS_ATMEL_BOOT |
e8ee8f3a | 349 | # define CONFIG_JFFS2_DEV "nor1" |
8ae158cd | 350 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 |
6d0f6bcf | 351 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) |
9f751551 | 352 | #endif |
6d0f6bcf | 353 | #ifdef CONFIG_SYS_INTEL_BOOT |
8ae158cd TL |
354 | # define CONFIG_JFFS2_DEV "nor0" |
355 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) | |
6d0f6bcf | 356 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) |
8ae158cd | 357 | #endif |
9f751551 | 358 | #endif |
8ae158cd TL |
359 | |
360 | /*----------------------------------------------------------------------- | |
361 | * Cache Configuration | |
362 | */ | |
6d0f6bcf | 363 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
8ae158cd | 364 | |
dd9f054e | 365 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 366 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 367 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 368 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
369 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
370 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
371 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
372 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
373 | CF_ACR_EN | CF_ACR_SM_ALL) | |
374 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ | |
375 | CF_CACR_ICINVA | CF_CACR_EUSP) | |
376 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
377 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
378 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
379 | ||
8ae158cd TL |
380 | /*----------------------------------------------------------------------- |
381 | * Memory bank definitions | |
382 | */ | |
383 | /* | |
384 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
385 | * CS1 - CompactFlash and registers | |
386 | * CS2 - CPLD | |
387 | * CS3 - FPGA | |
388 | * CS4 - Available | |
389 | * CS5 - Available | |
390 | */ | |
391 | ||
6d0f6bcf | 392 | #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) |
8ae158cd | 393 | /* Atmel Flash */ |
6d0f6bcf JCPV |
394 | #define CONFIG_SYS_CS0_BASE 0x04000000 |
395 | #define CONFIG_SYS_CS0_MASK 0x00070001 | |
396 | #define CONFIG_SYS_CS0_CTRL 0x00001140 | |
8ae158cd | 397 | /* Intel Flash */ |
6d0f6bcf JCPV |
398 | #define CONFIG_SYS_CS1_BASE 0x00000000 |
399 | #define CONFIG_SYS_CS1_MASK 0x01FF0001 | |
400 | #define CONFIG_SYS_CS1_CTRL 0x00000D60 | |
8ae158cd | 401 | |
6d0f6bcf | 402 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE |
8ae158cd TL |
403 | #else |
404 | /* Intel Flash */ | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
406 | #define CONFIG_SYS_CS0_MASK 0x01FF0001 | |
407 | #define CONFIG_SYS_CS0_CTRL 0x00000D60 | |
8ae158cd | 408 | /* Atmel Flash */ |
6d0f6bcf JCPV |
409 | #define CONFIG_SYS_CS1_BASE 0x04000000 |
410 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
411 | #define CONFIG_SYS_CS1_CTRL 0x00001140 | |
8ae158cd | 412 | |
6d0f6bcf | 413 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE |
8ae158cd TL |
414 | #endif |
415 | ||
416 | /* CPLD */ | |
6d0f6bcf JCPV |
417 | #define CONFIG_SYS_CS2_BASE 0x08000000 |
418 | #define CONFIG_SYS_CS2_MASK 0x00070001 | |
419 | #define CONFIG_SYS_CS2_CTRL 0x003f1140 | |
8ae158cd TL |
420 | |
421 | /* FPGA */ | |
6d0f6bcf JCPV |
422 | #define CONFIG_SYS_CS3_BASE 0x09000000 |
423 | #define CONFIG_SYS_CS3_MASK 0x00070001 | |
424 | #define CONFIG_SYS_CS3_CTRL 0x00000020 | |
8ae158cd | 425 | |
e8ee8f3a | 426 | #endif /* _M54455EVB_H */ |