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7d393aed WD |
1 | /* |
2 | * (C) Copyright 2001, 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /*********************************************************** | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | ***********************************************************/ | |
35 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
36 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
37 | #define CONFIG_MIP405 1 /* ...on a MIP405 board */ | |
2ae18241 WD |
38 | |
39 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 | |
40 | ||
f3e0de60 WD |
41 | /*********************************************************** |
42 | * Note that it may also be a MIP405T board which is a subset of the | |
43 | * MIP405 | |
44 | ***********************************************************/ | |
45 | /*********************************************************** | |
46 | * WARNING: | |
47 | * CONFIG_BOOT_PCI is only used for first boot-up and should | |
48 | * NOT be enabled for production bootloader | |
49 | ***********************************************************/ | |
8bde7f77 | 50 | /*#define CONFIG_BOOT_PCI 1*/ |
7d393aed WD |
51 | /*********************************************************** |
52 | * Clock | |
53 | ***********************************************************/ | |
54 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ | |
55 | ||
7d393aed | 56 | |
659e2f67 JL |
57 | /* |
58 | * BOOTP options | |
59 | */ | |
60 | #define CONFIG_BOOTP_BOOTFILESIZE | |
61 | #define CONFIG_BOOTP_BOOTPATH | |
62 | #define CONFIG_BOOTP_GATEWAY | |
63 | #define CONFIG_BOOTP_HOSTNAME | |
64 | ||
65 | ||
8353e139 JL |
66 | /* |
67 | * Command line configuration. | |
68 | */ | |
69 | #include <config_cmd_default.h> | |
70 | ||
71 | #define CONFIG_CMD_CACHE | |
72 | #define CONFIG_CMD_DATE | |
73 | #define CONFIG_CMD_DHCP | |
74 | #define CONFIG_CMD_EEPROM | |
75 | #define CONFIG_CMD_ELF | |
76 | #define CONFIG_CMD_FAT | |
77 | #define CONFIG_CMD_I2C | |
78 | #define CONFIG_CMD_IDE | |
79 | #define CONFIG_CMD_IRQ | |
80 | #define CONFIG_CMD_JFFS2 | |
81 | #define CONFIG_CMD_MII | |
82 | #define CONFIG_CMD_PCI | |
83 | #define CONFIG_CMD_PING | |
84 | #define CONFIG_CMD_REGINFO | |
85 | #define CONFIG_CMD_SAVES | |
86 | #define CONFIG_CMD_BSP | |
f3e0de60 | 87 | |
8353e139 JL |
88 | #if !defined(CONFIG_MIP405T) |
89 | #define CONFIG_CMD_USB | |
f3e0de60 WD |
90 | #endif |
91 | ||
7d393aed | 92 | |
6d0f6bcf | 93 | #define CONFIG_SYS_HUSH_PARSER |
7d393aed WD |
94 | /************************************************************** |
95 | * I2C Stuff: | |
96 | * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address | |
97 | * 0x53. | |
98 | * The Atmel EEPROM uses 16Bit addressing. | |
99 | ***************************************************************/ | |
100 | ||
101 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
d0b0dcaa | 102 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ |
104 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
7d393aed | 105 | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ |
107 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
7d393aed | 108 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
109 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
110 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ | |
7d393aed WD |
111 | /* 64 byte page write mode using*/ |
112 | /* last 6 bits of the address */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
7d393aed WD |
114 | |
115 | ||
bb1f8b4f | 116 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
117 | #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ |
118 | #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ | |
7d393aed WD |
119 | |
120 | /*************************************************************** | |
121 | * Definitions for Serial Presence Detect EEPROM address | |
122 | * (to get SDRAM settings) | |
123 | ***************************************************************/ | |
f3e0de60 | 124 | /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 |
53677ef1 | 125 | #define SDRAM_EEPROM_READ_ADDRESS 0xA1 |
f3e0de60 | 126 | */ |
7d393aed WD |
127 | /************************************************************** |
128 | * Environment definitions | |
129 | **************************************************************/ | |
130 | #define CONFIG_BAUDRATE 9600 /* STD Baudrate */ | |
131 | #define CONFIG_BOOTDELAY 5 | |
132 | /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ | |
2afbe4ed | 133 | /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ |
53677ef1 | 134 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ |
7d393aed | 135 | |
3e38691e | 136 | #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ |
7d393aed WD |
137 | #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ |
138 | ||
139 | #define CONFIG_IPADDR 10.0.0.100 | |
140 | #define CONFIG_SERVERIP 10.0.0.1 | |
141 | #define CONFIG_PREBOOT | |
142 | /*************************************************************** | |
143 | * defines if the console is stored in the environment | |
144 | ***************************************************************/ | |
6d0f6bcf | 145 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ |
7d393aed WD |
146 | /*************************************************************** |
147 | * defines if an overwrite_console function exists | |
148 | *************************************************************/ | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
150 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
7d393aed WD |
151 | /*************************************************************** |
152 | * defines if the overwrite_console should be stored in the | |
153 | * environment | |
154 | **************************************************************/ | |
6d0f6bcf | 155 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
7d393aed WD |
156 | |
157 | /************************************************************** | |
158 | * loads config | |
159 | *************************************************************/ | |
160 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 161 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
7d393aed WD |
162 | |
163 | #define CONFIG_MISC_INIT_R | |
164 | /*********************************************************** | |
165 | * Miscellaneous configurable options | |
166 | **********************************************************/ | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
168 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
8353e139 | 169 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 170 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
7d393aed | 171 | #else |
6d0f6bcf | 172 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
7d393aed | 173 | #endif |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
175 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
176 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
7d393aed | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
179 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ | |
7d393aed | 180 | |
550650dd SR |
181 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
182 | #define CONFIG_SYS_NS16550 | |
183 | #define CONFIG_SYS_NS16550_SERIAL | |
184 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
185 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
186 | ||
6d0f6bcf JCPV |
187 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
188 | #define CONFIG_SYS_BASE_BAUD 916667 | |
7d393aed WD |
189 | |
190 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 191 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
7d393aed WD |
192 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
193 | 57600, 115200, 230400, 460800, 921600 } | |
194 | ||
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
196 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
7d393aed | 197 | |
6d0f6bcf | 198 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
7d393aed WD |
199 | |
200 | /*----------------------------------------------------------------------- | |
201 | * PCI stuff | |
202 | *----------------------------------------------------------------------- | |
203 | */ | |
204 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
205 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
206 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
207 | ||
208 | #define CONFIG_PCI /* include pci support */ | |
209 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ | |
210 | #define CONFIG_PCI_PNP /* pci plug-and-play */ | |
211 | /* resource configuration */ | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
213 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ | |
214 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
215 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
216 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
217 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
218 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
219 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
7d393aed WD |
220 | |
221 | /*----------------------------------------------------------------------- | |
222 | * Start addresses for the final memory configuration | |
223 | * (Set up by the startup code) | |
6d0f6bcf | 224 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
7d393aed | 225 | */ |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
227 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
228 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
229 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
230 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ | |
7d393aed WD |
231 | |
232 | /* | |
233 | * For booting Linux, the board info and command line data | |
234 | * have to be in the first 8 MB of memory, since this is | |
235 | * the maximum mapped by the Linux kernel during initialization. | |
236 | */ | |
6d0f6bcf | 237 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
7d393aed WD |
238 | /*----------------------------------------------------------------------- |
239 | * FLASH organization | |
240 | */ | |
39441b35 DM |
241 | #define CONFIG_SYS_UPDATE_FLASH_SIZE |
242 | #define CONFIG_SYS_FLASH_PROTECTION | |
243 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
7d393aed | 244 | |
39441b35 DM |
245 | #define CONFIG_SYS_FLASH_CFI |
246 | #define CONFIG_FLASH_CFI_DRIVER | |
247 | ||
248 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
249 | ||
250 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
251 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
7d393aed | 252 | |
700a0c64 WD |
253 | /* |
254 | * JFFS2 partitions | |
255 | * | |
256 | */ | |
257 | /* No command line, one static partition, whole device */ | |
68d7d651 | 258 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
259 | #define CONFIG_JFFS2_DEV "nor0" |
260 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
261 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
262 | ||
263 | /* mtdparts command line support */ | |
264 | /* Note: fake mtd_id used, no linux mtd map file */ | |
265 | /* | |
68d7d651 | 266 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
267 | #define MTDIDS_DEFAULT "nor0=mip405-0" |
268 | #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" | |
269 | */ | |
7d393aed | 270 | |
63e73c9a WD |
271 | /*----------------------------------------------------------------------- |
272 | * Logbuffer Configuration | |
273 | */ | |
53677ef1 | 274 | #undef CONFIG_LOGBUFFER /* supported but not enabled */ |
63e73c9a WD |
275 | /*----------------------------------------------------------------------- |
276 | * Bootcountlimit Configuration | |
277 | */ | |
278 | #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ | |
279 | ||
280 | /*----------------------------------------------------------------------- | |
281 | * POST Configuration | |
282 | */ | |
283 | #if 0 /* enable this if POST is desired (is supported but not enabled) */ | |
6d0f6bcf JCPV |
284 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
285 | CONFIG_SYS_POST_CPU | \ | |
286 | CONFIG_SYS_POST_RTC | \ | |
287 | CONFIG_SYS_POST_I2C) | |
63e73c9a WD |
288 | |
289 | #endif | |
7d393aed WD |
290 | /* |
291 | * Init Memory Controller: | |
292 | */ | |
7205e407 WD |
293 | #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ |
294 | #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ | |
295 | /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ | |
296 | #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ | |
7d393aed | 297 | |
c837dcb1 | 298 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
39441b35 | 299 | #define CONFIG_BOARD_EARLY_INIT_R |
7d393aed WD |
300 | |
301 | /* Peripheral Bus Mapping */ | |
302 | #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ | |
303 | #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ | |
304 | #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ | |
305 | ||
306 | #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 | |
53677ef1 | 307 | #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 |
7d393aed WD |
308 | |
309 | ||
7d393aed WD |
310 | /*----------------------------------------------------------------------- |
311 | * Definitions for initial stack pointer and data area (in On Chip SRAM) | |
312 | */ | |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
314 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 | |
315 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
316 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ | |
553f0982 | 317 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ |
25ddd1fb | 318 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
63e73c9a | 319 | /* reserve some memory for POST and BOOT limit info */ |
6d0f6bcf | 320 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) |
63e73c9a | 321 | |
63e73c9a | 322 | #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ |
6d0f6bcf | 323 | #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12) |
63e73c9a | 324 | #endif |
7d393aed | 325 | |
7d393aed WD |
326 | /*********************************************************************** |
327 | * External peripheral base address | |
328 | ***********************************************************************/ | |
6d0f6bcf | 329 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 |
7d393aed WD |
330 | |
331 | /*********************************************************************** | |
332 | * Last Stage Init | |
333 | ***********************************************************************/ | |
334 | #define CONFIG_LAST_STAGE_INIT | |
335 | /************************************************************ | |
336 | * Ethernet Stuff | |
337 | ***********************************************************/ | |
96e21f86 | 338 | #define CONFIG_PPC4xx_EMAC |
7d393aed WD |
339 | #define CONFIG_MII 1 /* MII PHY management */ |
340 | #define CONFIG_PHY_ADDR 1 /* PHY address */ | |
63e73c9a WD |
341 | #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ |
342 | #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ | |
7d393aed WD |
343 | /************************************************************ |
344 | * RTC | |
345 | ***********************************************************/ | |
346 | #define CONFIG_RTC_MC146818 | |
347 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
348 | ||
349 | /************************************************************ | |
350 | * IDE/ATA stuff | |
351 | ************************************************************/ | |
f3e0de60 | 352 | #if defined(CONFIG_MIP405T) |
6d0f6bcf | 353 | #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ |
f3e0de60 | 354 | #else |
6d0f6bcf | 355 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
f3e0de60 WD |
356 | #endif |
357 | ||
6d0f6bcf | 358 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
7d393aed | 359 | |
6d0f6bcf JCPV |
360 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */ |
361 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ | |
362 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ | |
363 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ | |
364 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ | |
365 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ | |
7d393aed WD |
366 | |
367 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
368 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
369 | #define CONFIG_IDE_RESET /* reset for ide supported... */ | |
370 | #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ | |
7205e407 | 371 | #define CONFIG_SUPPORT_VFAT |
7d393aed WD |
372 | /************************************************************ |
373 | * ATAPI support (experimental) | |
374 | ************************************************************/ | |
375 | #define CONFIG_ATAPI /* enable ATAPI Support */ | |
376 | ||
7d393aed WD |
377 | /************************************************************ |
378 | * DISK Partition support | |
379 | ************************************************************/ | |
380 | #define CONFIG_DOS_PARTITION | |
381 | #define CONFIG_MAC_PARTITION | |
382 | #define CONFIG_ISO_PARTITION /* Experimental */ | |
383 | ||
7d393aed WD |
384 | /************************************************************ |
385 | * Keyboard support | |
386 | ************************************************************/ | |
387 | #undef CONFIG_ISA_KEYBOARD | |
388 | ||
389 | /************************************************************ | |
390 | * Video support | |
391 | ************************************************************/ | |
392 | #define CONFIG_VIDEO /*To enable video controller support */ | |
393 | #define CONFIG_VIDEO_CT69000 | |
394 | #define CONFIG_CFB_CONSOLE | |
395 | #define CONFIG_VIDEO_LOGO | |
396 | #define CONFIG_CONSOLE_EXTRA_INFO | |
397 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
398 | #define CONFIG_VIDEO_SW_CURSOR | |
399 | #undef CONFIG_VIDEO_ONBOARD | |
400 | /************************************************************ | |
401 | * USB support EXPERIMENTAL | |
402 | ************************************************************/ | |
f3e0de60 | 403 | #if !defined(CONFIG_MIP405T) |
7d393aed WD |
404 | #define CONFIG_USB_UHCI |
405 | #define CONFIG_USB_KEYBOARD | |
406 | #define CONFIG_USB_STORAGE | |
407 | ||
408 | /* Enable needed helper functions */ | |
52cb4d4f | 409 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
f3e0de60 | 410 | #endif |
7d393aed WD |
411 | /************************************************************ |
412 | * Debug support | |
413 | ************************************************************/ | |
8353e139 | 414 | #if defined(CONFIG_CMD_KGDB) |
7d393aed WD |
415 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
416 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
417 | #endif | |
418 | ||
a2663ea4 WD |
419 | /************************************************************ |
420 | * support BZIP2 compression | |
421 | ************************************************************/ | |
422 | #define CONFIG_BZIP2 1 | |
423 | ||
7d393aed WD |
424 | /************************************************************ |
425 | * Ident | |
426 | ************************************************************/ | |
f3e0de60 | 427 | |
7d393aed | 428 | #define VERSION_TAG "released" |
f3e0de60 WD |
429 | #if !defined(CONFIG_MIP405T) |
430 | #define CONFIG_ISO_STRING "MEV-10072-001" | |
431 | #else | |
432 | #define CONFIG_ISO_STRING "MEV-10082-001" | |
433 | #endif | |
434 | ||
435 | #if !defined(CONFIG_BOOT_PCI) | |
436 | #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG | |
437 | #else | |
438 | #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version" | |
439 | #endif | |
7d393aed WD |
440 | |
441 | ||
442 | #endif /* __CONFIG_H */ |