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96b8a054 SW |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
96b8a054 SW |
21 | */ |
22 | /* | |
23 | * mpc8313epb board configuration file | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | */ | |
32 | #define CONFIG_E300 1 | |
33 | #define CONFIG_MPC83XX 1 | |
34 | #define CONFIG_MPC831X 1 | |
35 | #define CONFIG_MPC8313 1 | |
36 | #define CONFIG_MPC8313ERDB 1 | |
37 | ||
38 | #define CONFIG_PCI | |
39 | #define CONFIG_83XX_GENERIC_PCI | |
40 | ||
41 | #ifdef CFG_66MHZ | |
5c5d3242 | 42 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ |
96b8a054 | 43 | #elif defined(CFG_33MHZ) |
5c5d3242 | 44 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
96b8a054 SW |
45 | #else |
46 | #error Unknown oscillator frequency. | |
47 | #endif | |
48 | ||
49 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
50 | ||
51 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
52 | ||
53 | #define CFG_IMMR 0xE0000000 | |
54 | ||
55 | #define CFG_MEMTEST_START 0x00001000 | |
56 | #define CFG_MEMTEST_END 0x07f00000 | |
57 | ||
58 | /* Early revs of this board will lock up hard when attempting | |
59 | * to access the PMC registers, unless a JTAG debugger is | |
60 | * connected, or some resistor modifications are made. | |
61 | */ | |
62 | #define CFG_8313ERDB_BROKEN_PMC 1 | |
63 | ||
64 | #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ | |
65 | #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
66 | ||
67 | /* | |
68 | * DDR Setup | |
69 | */ | |
70 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ | |
71 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
72 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
73 | ||
74 | /* | |
75 | * Manually set up DDR parameters, as this board does not | |
76 | * seem to have the SPD connected to I2C. | |
77 | */ | |
78 | #define CFG_DDR_SIZE 128 /* MB */ | |
79 | #define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ | |
80 | | 0x00040000 /* TODO */ \ | |
81 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) | |
82 | /* 0x80840102 */ | |
83 | ||
84 | #define CFG_DDR_TIMING_3 0x00000000 | |
85 | #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | |
86 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | |
87 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
88 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
89 | | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
90 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
91 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
92 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
93 | /* 0x00220802 */ | |
94 | #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ | |
95 | | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | |
96 | | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | |
97 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | |
98 | | (13 << TIMING_CFG1_REFREC_SHIFT ) \ | |
99 | | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ | |
100 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | |
101 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
102 | /* 0x3935d322 */ | |
103 | #define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ | |
104 | | (31 << TIMING_CFG2_CPO_SHIFT ) \ | |
105 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | |
106 | | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
107 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
108 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
109 | | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) | |
110 | /* 0x0f9048ca */ /* P9-45,may need tuning */ | |
111 | #define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | |
112 | | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) | |
113 | /* 0x03200064 */ | |
114 | #if defined(CONFIG_DDR_2T_TIMING) | |
115 | #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ | |
bbea46f7 | 116 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
96b8a054 SW |
117 | | SDRAM_CFG_2T_EN \ |
118 | | SDRAM_CFG_DBW_32 ) | |
119 | #else | |
120 | #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ | |
bbea46f7 | 121 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
96b8a054 SW |
122 | | SDRAM_CFG_32_BE ) |
123 | /* 0x43080000 */ | |
124 | #endif | |
125 | #define CFG_SDRAM_CFG2 0x00401000; | |
126 | /* set burst length to 8 for 32-bit data path */ | |
127 | #define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ | |
128 | | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) | |
129 | /* 0x44400232 */ | |
130 | #define CFG_DDR_MODE_2 0x8000C000; | |
131 | ||
132 | #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
133 | /*0x02000000*/ | |
134 | #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ | |
135 | | DDRCDR_PZ_NOMZ \ | |
136 | | DDRCDR_NZ_NOMZ \ | |
137 | | DDRCDR_M_ODR ) | |
138 | ||
139 | /* | |
140 | * FLASH on the Local Bus | |
141 | */ | |
142 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
143 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
144 | #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ | |
145 | #define CFG_FLASH_SIZE 8 /* flash size in MB */ | |
146 | #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ | |
147 | #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
148 | ||
a7676ea7 WD |
149 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ |
150 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ | |
151 | BR_V) /* valid */ | |
152 | #define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ | |
96b8a054 SW |
153 | | OR_GPCM_XACS \ |
154 | | OR_GPCM_SCY_9 \ | |
155 | | OR_GPCM_EHTR \ | |
156 | | OR_GPCM_EAD ) | |
157 | /* 0xFF006FF7 TODO SLOW 16 MB flash size */ | |
158 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ | |
159 | #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ | |
160 | ||
161 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
162 | #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ | |
163 | ||
164 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
165 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
166 | ||
167 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
168 | ||
169 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
170 | #define CFG_RAMBOOT | |
171 | #endif | |
172 | ||
173 | #define CFG_INIT_RAM_LOCK 1 | |
174 | #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
175 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
176 | ||
177 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
178 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
179 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
180 | ||
b2893e1f | 181 | /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ |
96b8a054 SW |
182 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
183 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
184 | ||
185 | /* | |
186 | * Local Bus LCRR and LBCR regs | |
187 | */ | |
188 | #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ | |
189 | #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ | |
190 | | (0xFF << LBCR_BMT_SHIFT) \ | |
191 | | 0xF ) /* 0x0004ff0f */ | |
192 | ||
a7676ea7 | 193 | #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ |
96b8a054 SW |
194 | |
195 | /* drivers/nand/nand.c */ | |
a7676ea7 | 196 | #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ |
96b8a054 SW |
197 | #define CFG_MAX_NAND_DEVICE 1 |
198 | #define NAND_MAX_CHIPS 1 | |
199 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
200 | ||
201 | #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ | |
a7676ea7 WD |
202 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
203 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
204 | | BR_MS_FCM /* MSEL = FCM */ \ | |
205 | | BR_V ) /* valid */ | |
206 | #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ | |
96b8a054 SW |
207 | | OR_FCM_CSCT \ |
208 | | OR_FCM_CST \ | |
209 | | OR_FCM_CHT \ | |
210 | | OR_FCM_SCY_1 \ | |
211 | | OR_FCM_TRLX \ | |
212 | | OR_FCM_EHTR ) | |
213 | /* 0xFFFF8396 */ | |
214 | #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE | |
215 | #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ | |
216 | ||
217 | #define CFG_VSC7385_BASE 0xF0000000 | |
218 | ||
219 | #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ | |
220 | #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ | |
221 | #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ | |
222 | #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ | |
223 | #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ | |
224 | ||
225 | /* local bus read write buffer mapping */ | |
226 | #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ | |
227 | #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ | |
228 | #define CFG_LBLAWBAR3_PRELIM 0xFA000000 | |
229 | #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ | |
230 | ||
231 | /* pass open firmware flat tree */ | |
35cc4e48 | 232 | #define CONFIG_OF_LIBFDT 1 |
96b8a054 | 233 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 234 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
96b8a054 SW |
235 | |
236 | /* | |
237 | * Serial Port | |
238 | */ | |
239 | #define CONFIG_CONS_INDEX 1 | |
240 | #define CFG_NS16550 | |
241 | #define CFG_NS16550_SERIAL | |
242 | #define CFG_NS16550_REG_SIZE 1 | |
243 | #define CFG_NS16550_CLK get_bus_freq(0) | |
244 | ||
245 | #define CFG_BAUDRATE_TABLE \ | |
246 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
247 | ||
248 | #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) | |
249 | #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) | |
250 | ||
251 | /* Use the HUSH parser */ | |
252 | #define CFG_HUSH_PARSER | |
253 | #define CFG_PROMPT_HUSH_PS2 "> " | |
254 | ||
255 | /* I2C */ | |
256 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
257 | #define CONFIG_FSL_I2C | |
258 | #define CONFIG_I2C_MULTI_BUS | |
259 | #define CONFIG_I2C_CMD_TREE | |
260 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
261 | #define CFG_I2C_SLAVE 0x7F | |
cdd917a4 | 262 | #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
96b8a054 SW |
263 | #define CFG_I2C_OFFSET 0x3000 |
264 | #define CFG_I2C2_OFFSET 0x3100 | |
265 | ||
266 | /* TSEC */ | |
267 | #define CFG_TSEC1_OFFSET 0x24000 | |
268 | #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) | |
269 | #define CFG_TSEC2_OFFSET 0x25000 | |
270 | #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) | |
271 | #define CONFIG_NET_MULTI | |
272 | ||
273 | /* | |
274 | * General PCI | |
275 | * Addresses are mapped 1-1. | |
276 | */ | |
277 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
278 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
279 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
280 | #define CFG_PCI1_MMIO_BASE 0x90000000 | |
281 | #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE | |
282 | #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
283 | #define CFG_PCI1_IO_BASE 0x00000000 | |
284 | #define CFG_PCI1_IO_PHYS 0xE2000000 | |
285 | #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
286 | ||
287 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
288 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
289 | ||
290 | /* | |
291 | * TSEC configuration | |
292 | */ | |
293 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
294 | ||
295 | #ifndef CONFIG_NET_MULTI | |
296 | #define CONFIG_NET_MULTI 1 | |
297 | #endif | |
298 | ||
299 | #define CONFIG_GMII 1 /* MII PHY management */ | |
255a3577 | 300 | #define CONFIG_TSEC1 1 |
96b8a054 | 301 | |
255a3577 KP |
302 | #define CONFIG_TSEC1_NAME "TSEC0" |
303 | #define CONFIG_TSEC2 1 | |
304 | #define CONFIG_TSEC2_NAME "TSEC1" | |
96b8a054 SW |
305 | #define TSEC1_PHY_ADDR 0x1c |
306 | #define TSEC2_PHY_ADDR 4 | |
3a79013e AF |
307 | #define TSEC1_FLAGS TSEC_GIGABIT |
308 | #define TSEC2_FLAGS TSEC_GIGABIT | |
96b8a054 SW |
309 | #define TSEC1_PHYIDX 0 |
310 | #define TSEC2_PHYIDX 0 | |
311 | ||
312 | /* Options are: TSEC[0-1] */ | |
313 | #define CONFIG_ETHPRIME "TSEC1" | |
314 | ||
315 | /* | |
316 | * Configure on-board RTC | |
317 | */ | |
318 | #define CONFIG_RTC_DS1337 | |
319 | #define CFG_I2C_RTC_ADDR 0x68 | |
320 | ||
321 | /* | |
322 | * Environment | |
323 | */ | |
324 | #ifndef CFG_RAMBOOT | |
325 | #define CFG_ENV_IS_IN_FLASH 1 | |
b2893e1f | 326 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
96b8a054 SW |
327 | #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
328 | #define CFG_ENV_SIZE 0x2000 | |
329 | ||
330 | /* Address and size of Redundant Environment Sector */ | |
331 | #else | |
332 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
333 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
334 | #define CFG_ENV_SIZE 0x2000 | |
335 | #endif | |
336 | ||
337 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
338 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
339 | ||
079a136c JL |
340 | /* |
341 | * BOOTP options | |
342 | */ | |
343 | #define CONFIG_BOOTP_BOOTFILESIZE | |
344 | #define CONFIG_BOOTP_BOOTPATH | |
345 | #define CONFIG_BOOTP_GATEWAY | |
346 | #define CONFIG_BOOTP_HOSTNAME | |
347 | ||
348 | ||
8ea5499a JL |
349 | /* |
350 | * Command line configuration. | |
351 | */ | |
352 | #include <config_cmd_default.h> | |
96b8a054 | 353 | |
8ea5499a JL |
354 | #define CONFIG_CMD_PING |
355 | #define CONFIG_CMD_DHCP | |
356 | #define CONFIG_CMD_I2C | |
357 | #define CONFIG_CMD_MII | |
358 | #define CONFIG_CMD_DATE | |
359 | #define CONFIG_CMD_PCI | |
96b8a054 SW |
360 | |
361 | #if defined(CFG_RAMBOOT) | |
8ea5499a JL |
362 | #undef CONFIG_CMD_ENV |
363 | #undef CONFIG_CMD_LOADS | |
96b8a054 SW |
364 | #endif |
365 | ||
8ea5499a JL |
366 | #define CONFIG_CMDLINE_EDITING 1 |
367 | ||
96b8a054 SW |
368 | |
369 | /* | |
370 | * Miscellaneous configurable options | |
371 | */ | |
372 | #define CFG_LONGHELP /* undef to save memory */ | |
373 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
374 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
375 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
376 | ||
a7676ea7 | 377 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
96b8a054 SW |
378 | #define CFG_MAXARGS 16 /* max number of command args */ |
379 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
380 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
381 | ||
382 | /* | |
383 | * For booting Linux, the board info and command line data | |
384 | * have to be in the first 8 MB of memory, since this is | |
385 | * the maximum mapped by the Linux kernel during initialization. | |
386 | */ | |
387 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
388 | ||
389 | /* Cache Configuration */ | |
390 | #define CFG_DCACHE_SIZE 16384 | |
391 | #define CFG_CACHELINE_SIZE 32 | |
392 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ | |
393 | ||
a7676ea7 | 394 | #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
96b8a054 SW |
395 | |
396 | #ifdef CFG_66MHZ | |
397 | ||
398 | /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ | |
399 | /* 0x62040000 */ | |
400 | #define CFG_HRCW_LOW (\ | |
401 | 0x20000000 /* reserved, must be set */ |\ | |
402 | HRCWL_DDRCM |\ | |
403 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
404 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
405 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
406 | HRCWL_CORE_TO_CSB_2X1) | |
407 | ||
408 | #elif defined(CFG_33MHZ) | |
409 | ||
410 | /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ | |
411 | /* 0x65040000 */ | |
412 | #define CFG_HRCW_LOW (\ | |
413 | 0x20000000 /* reserved, must be set */ |\ | |
414 | HRCWL_DDRCM |\ | |
415 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
416 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
417 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
418 | HRCWL_CORE_TO_CSB_2X1) | |
419 | ||
420 | #endif | |
421 | ||
422 | /* 0xa0606c00 */ | |
423 | #define CFG_HRCW_HIGH (\ | |
424 | HRCWH_PCI_HOST |\ | |
425 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
426 | HRCWH_CORE_ENABLE |\ | |
427 | HRCWH_FROM_0X00000100 |\ | |
428 | HRCWH_BOOTSEQ_DISABLE |\ | |
429 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
430 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
431 | HRCWH_RL_EXT_LEGACY |\ | |
432 | HRCWH_TSEC1M_IN_RGMII |\ | |
433 | HRCWH_TSEC2M_IN_RGMII |\ | |
434 | HRCWH_BIG_ENDIAN |\ | |
435 | HRCWH_LALE_NORMAL) | |
436 | ||
437 | /* System IO Config */ | |
a7676ea7 WD |
438 | #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ |
439 | #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ | |
96b8a054 SW |
440 | |
441 | #define CFG_HID0_INIT 0x000000000 | |
442 | #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
a7676ea7 | 443 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
96b8a054 SW |
444 | |
445 | #define CFG_HID2 HID2_HBE | |
446 | ||
447 | /* DDR @ 0x00000000 */ | |
448 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) | |
449 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
450 | ||
451 | /* PCI @ 0x80000000 */ | |
452 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) | |
453 | #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
454 | #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
455 | #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
456 | ||
457 | /* PCI2 not supported on 8313 */ | |
458 | #define CFG_IBAT3L (0) | |
459 | #define CFG_IBAT3U (0) | |
460 | #define CFG_IBAT4L (0) | |
461 | #define CFG_IBAT4U (0) | |
462 | ||
463 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
464 | #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
465 | #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
466 | ||
467 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
468 | #define CFG_IBAT6L (0xF0000000 | BATL_PP_10) | |
469 | #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
470 | ||
471 | #define CFG_IBAT7L (0) | |
472 | #define CFG_IBAT7U (0) | |
473 | ||
474 | #define CFG_DBAT0L CFG_IBAT0L | |
475 | #define CFG_DBAT0U CFG_IBAT0U | |
476 | #define CFG_DBAT1L CFG_IBAT1L | |
477 | #define CFG_DBAT1U CFG_IBAT1U | |
478 | #define CFG_DBAT2L CFG_IBAT2L | |
479 | #define CFG_DBAT2U CFG_IBAT2U | |
480 | #define CFG_DBAT3L CFG_IBAT3L | |
481 | #define CFG_DBAT3U CFG_IBAT3U | |
482 | #define CFG_DBAT4L CFG_IBAT4L | |
483 | #define CFG_DBAT4U CFG_IBAT4U | |
484 | #define CFG_DBAT5L CFG_IBAT5L | |
485 | #define CFG_DBAT5U CFG_IBAT5U | |
486 | #define CFG_DBAT6L CFG_IBAT6L | |
487 | #define CFG_DBAT6U CFG_IBAT6U | |
488 | #define CFG_DBAT7L CFG_IBAT7L | |
489 | #define CFG_DBAT7U CFG_IBAT7U | |
490 | ||
491 | /* | |
492 | * Internal Definitions | |
493 | * | |
494 | * Boot Flags | |
495 | */ | |
496 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
497 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
498 | ||
499 | /* | |
500 | * Environment Configuration | |
501 | */ | |
502 | #define CONFIG_ENV_OVERWRITE | |
503 | ||
504 | #define CONFIG_ETHADDR 00:E0:0C:00:95:01 | |
505 | #define CONFIG_HAS_ETH1 | |
10327dc5 | 506 | #define CONFIG_HAS_ETH0 |
96b8a054 SW |
507 | #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 |
508 | ||
509 | #define CONFIG_IPADDR 10.0.0.2 | |
510 | #define CONFIG_SERVERIP 10.0.0.1 | |
511 | #define CONFIG_GATEWAYIP 10.0.0.1 | |
512 | #define CONFIG_NETMASK 255.0.0.0 | |
513 | #define CONFIG_NETDEV eth1 | |
514 | ||
515 | #define CONFIG_HOSTNAME mpc8313erdb | |
516 | #define CONFIG_ROOTPATH /nfs/root/path | |
517 | #define CONFIG_BOOTFILE uImage | |
518 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
519 | #define CONFIG_FDTFILE mpc8313erdb.dtb | |
520 | ||
521 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
522 | #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ | |
523 | #define CONFIG_BAUDRATE 115200 | |
524 | ||
525 | #define XMK_STR(x) #x | |
526 | #define MK_STR(x) XMK_STR(x) | |
527 | ||
528 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
529 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ | |
530 | "ethprime=TSEC1\0" \ | |
531 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
532 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
533 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
534 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
535 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
536 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
537 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
538 | "fdtaddr=400000\0" \ | |
539 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ | |
540 | "console=ttyS0\0" \ | |
541 | "setbootargs=setenv bootargs " \ | |
542 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
543 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
544 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
545 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" | |
546 | ||
547 | #define CONFIG_NFSBOOTCOMMAND \ | |
548 | "setenv rootdev /dev/nfs;" \ | |
549 | "run setbootargs;" \ | |
550 | "run setipargs;" \ | |
551 | "tftp $loadaddr $bootfile;" \ | |
552 | "tftp $fdtaddr $fdtfile;" \ | |
553 | "bootm $loadaddr - $fdtaddr" | |
554 | ||
555 | #define CONFIG_RAMBOOTCOMMAND \ | |
556 | "setenv rootdev /dev/ram;" \ | |
557 | "run setbootargs;" \ | |
558 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
559 | "tftp $loadaddr $bootfile;" \ | |
560 | "tftp $fdtaddr $fdtfile;" \ | |
561 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
562 | ||
563 | #undef MK_STR | |
564 | #undef XMK_STR | |
565 | ||
566 | #endif /* __CONFIG_H */ |