projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 991425fe MB |
1 | /* |
| 2 | * (C) Copyright 2006 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * mpc8349emds board configuration file | |
| 26 | * | |
| 27 | */ | |
| 28 | ||
| 29 | #ifndef __CONFIG_H | |
| 30 | #define __CONFIG_H | |
| 31 | ||
| 991425fe MB |
32 | /* |
| 33 | * High Level Configuration Options | |
| 34 | */ | |
| 35 | #define CONFIG_E300 1 /* E300 Family */ | |
| bf0b542d | 36 | #define CONFIG_MPC83XX 1 /* MPC83XX family */ |
| b24f119d | 37 | #define CONFIG_MPC834X 1 /* MPC834X family */ |
| 991425fe MB |
38 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
| 39 | #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ | |
| 40 | ||
| 977b50f8 | 41 | #undef CONFIG_PCI |
| 53677ef1 | 42 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ |
| 991425fe MB |
43 | |
| 44 | #define PCI_66M | |
| 45 | #ifdef PCI_66M | |
| 46 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
| 47 | #else | |
| 48 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
| 49 | #endif | |
| 50 | ||
| 447ad576 IS |
51 | #ifdef CONFIG_PCISLAVE |
| 52 | #define CONFIG_PCI | |
| 53 | #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ | |
| 54 | #endif /* CONFIG_PCISLAVE */ | |
| 55 | ||
| 991425fe MB |
56 | #ifndef CONFIG_SYS_CLK_FREQ |
| 57 | #ifdef PCI_66M | |
| 58 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
| 8fe9bf61 | 59 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
| 991425fe MB |
60 | #else |
| 61 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
| 8fe9bf61 | 62 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
| 991425fe MB |
63 | #endif |
| 64 | #endif | |
| 65 | ||
| 66 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
| 67 | ||
| 6d0f6bcf | 68 | #define CONFIG_SYS_IMMR 0xE0000000 |
| 991425fe | 69 | |
| 6d0f6bcf JCPV |
70 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 71 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
| 72 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
| 991425fe MB |
73 | |
| 74 | /* | |
| 75 | * DDR Setup | |
| 76 | */ | |
| 8d172c0f | 77 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
| d326f4a2 | 78 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
| 991425fe MB |
79 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
| 80 | ||
| dc9e499c RJ |
81 | /* |
| 82 | * 32-bit data path mode. | |
| cf48eb9a | 83 | * |
| dc9e499c RJ |
84 | * Please note that using this mode for devices with the real density of 64-bit |
| 85 | * effectively reduces the amount of available memory due to the effect of | |
| 86 | * wrapping around while translating address to row/columns, for example in the | |
| 87 | * 256MB module the upper 128MB get aliased with contents of the lower | |
| 88 | * 128MB); normally this define should be used for devices with real 32-bit | |
| cf48eb9a | 89 | * data path. |
| dc9e499c RJ |
90 | */ |
| 91 | #undef CONFIG_DDR_32BIT | |
| 92 | ||
| 6d0f6bcf JCPV |
93 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 94 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 95 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 96 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ | |
| 8d172c0f | 97 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
| 991425fe MB |
98 | #undef CONFIG_DDR_2T_TIMING |
| 99 | ||
| 8d172c0f XX |
100 | /* |
| 101 | * DDRCDR - DDR Control Driver Register | |
| 102 | */ | |
| 6d0f6bcf | 103 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
| 8d172c0f | 104 | |
| 991425fe | 105 | #if defined(CONFIG_SPD_EEPROM) |
| dc9e499c RJ |
106 | /* |
| 107 | * Determine DDR configuration from I2C interface. | |
| 108 | */ | |
| 109 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
| 991425fe | 110 | #else |
| dc9e499c RJ |
111 | /* |
| 112 | * Manually set up DDR parameters | |
| 113 | */ | |
| 6d0f6bcf | 114 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
| 8d172c0f | 115 | #if defined(CONFIG_DDR_II) |
| 6d0f6bcf JCPV |
116 | #define CONFIG_SYS_DDRCDR 0x80080001 |
| 117 | #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f | |
| 118 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 | |
| 119 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 | |
| 120 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
| 121 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
| 122 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
| 123 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
| 124 | #define CONFIG_SYS_DDR_MODE 0x47d00432 | |
| 125 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
| 126 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 | |
| 127 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 | |
| 128 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
| 8d172c0f | 129 | #else |
| 6d0f6bcf JCPV |
130 | #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
| 131 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 | |
| 132 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
| 133 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
| 134 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ | |
| dc9e499c RJ |
135 | |
| 136 | #if defined(CONFIG_DDR_32BIT) | |
| 137 | /* set burst length to 8 for 32-bit data path */ | |
| 6d0f6bcf | 138 | #define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ |
| dc9e499c RJ |
139 | #else |
| 140 | /* the default burst length is 4 - for 64-bit data path */ | |
| 6d0f6bcf | 141 | #define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ |
| dc9e499c | 142 | #endif |
| 991425fe | 143 | #endif |
| 8d172c0f | 144 | #endif |
| 991425fe MB |
145 | |
| 146 | /* | |
| 147 | * SDRAM on the Local Bus | |
| 148 | */ | |
| 6d0f6bcf JCPV |
149 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
| 150 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
| 991425fe MB |
151 | |
| 152 | /* | |
| 153 | * FLASH on the Local Bus | |
| 154 | */ | |
| 6d0f6bcf | 155 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| 00b1883a | 156 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
| 6d0f6bcf JCPV |
157 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
| 158 | #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ | |
| 159 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
| 160 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ | |
| 991425fe | 161 | |
| 6d0f6bcf | 162 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ |
| 8d172c0f | 163 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ |
| 991425fe | 164 | BR_V) /* valid */ |
| 6d0f6bcf | 165 | #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ |
| f9023afb | 166 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ |
| 8d172c0f | 167 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
| 6d0f6bcf JCPV |
168 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ |
| 169 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ | |
| 991425fe | 170 | |
| 6d0f6bcf JCPV |
171 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 172 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
| 991425fe | 173 | |
| 6d0f6bcf JCPV |
174 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 175 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 176 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 991425fe | 177 | |
| 6d0f6bcf JCPV |
178 | #define CONFIG_SYS_MID_FLASH_JUMP 0x7F000000 |
| 179 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 991425fe | 180 | |
| 6d0f6bcf JCPV |
181 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 182 | #define CONFIG_SYS_RAMBOOT | |
| 991425fe | 183 | #else |
| 6d0f6bcf | 184 | #undef CONFIG_SYS_RAMBOOT |
| 991425fe MB |
185 | #endif |
| 186 | ||
| 187 | /* | |
| 188 | * BCSR register on local bus 32KB, 8-bit wide for MDS config reg | |
| 189 | */ | |
| 6d0f6bcf JCPV |
190 | #define CONFIG_SYS_BCSR 0xE2400000 |
| 191 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ | |
| 192 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ | |
| 193 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ | |
| 194 | #define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ | |
| 991425fe | 195 | |
| 6d0f6bcf JCPV |
196 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 197 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
| 198 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
| 991425fe | 199 | |
| 6d0f6bcf JCPV |
200 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
| 201 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 202 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 991425fe | 203 | |
| 6d0f6bcf JCPV |
204 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 205 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 991425fe MB |
206 | |
| 207 | /* | |
| 208 | * Local Bus LCRR and LBCR regs | |
| 209 | * LCRR: DLL bypass, Clock divider is 4 | |
| 210 | * External Local Bus rate is | |
| 211 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
| 212 | */ | |
| 6d0f6bcf JCPV |
213 | #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
| 214 | #define CONFIG_SYS_LBC_LBCR 0x00000000 | |
| 991425fe | 215 | |
| 8d172c0f XX |
216 | /* |
| 217 | * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. | |
| 6d0f6bcf | 218 | * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM |
| 8d172c0f | 219 | */ |
| 6d0f6bcf | 220 | #undef CONFIG_SYS_LB_SDRAM |
| 991425fe | 221 | |
| 6d0f6bcf | 222 | #ifdef CONFIG_SYS_LB_SDRAM |
| 991425fe MB |
223 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ |
| 224 | /* | |
| 225 | * Base Register 2 and Option Register 2 configure SDRAM. | |
| 6d0f6bcf | 226 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
| 991425fe MB |
227 | * |
| 228 | * For BR2, need: | |
| 229 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
| 230 | * port-size = 32-bits = BR2[19:20] = 11 | |
| 231 | * no parity checking = BR2[21:22] = 00 | |
| 232 | * SDRAM for MSEL = BR2[24:26] = 011 | |
| 233 | * Valid = BR[31] = 1 | |
| 234 | * | |
| 235 | * 0 4 8 12 16 20 24 28 | |
| 236 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
| 237 | * | |
| 6d0f6bcf | 238 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
| 991425fe MB |
239 | * FIXME: the top 17 bits of BR2. |
| 240 | */ | |
| 241 | ||
| 6d0f6bcf JCPV |
242 | #define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ |
| 243 | #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 | |
| 244 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ | |
| 991425fe MB |
245 | |
| 246 | /* | |
| 6d0f6bcf | 247 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
| 991425fe MB |
248 | * |
| 249 | * For OR2, need: | |
| 250 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
| 251 | * XAM, OR2[17:18] = 11 | |
| 252 | * 9 columns OR2[19-21] = 010 | |
| 253 | * 13 rows OR2[23-25] = 100 | |
| 254 | * EAD set for extra time OR[31] = 1 | |
| 255 | * | |
| 256 | * 0 4 8 12 16 20 24 28 | |
| 257 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
| 258 | */ | |
| 259 | ||
| 6d0f6bcf | 260 | #define CONFIG_SYS_OR2_PRELIM 0xFC006901 |
| 991425fe | 261 | |
| 6d0f6bcf JCPV |
262 | #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
| 263 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
| 991425fe | 264 | |
| 540dcf1c KG |
265 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ |
| 266 | | LSDMR_BSMA1516 \ | |
| 267 | | LSDMR_RFCR8 \ | |
| 268 | | LSDMR_PRETOACT6 \ | |
| 269 | | LSDMR_ACTTORW3 \ | |
| 270 | | LSDMR_BL8 \ | |
| 271 | | LSDMR_WRC3 \ | |
| 272 | | LSDMR_CL3 \ | |
| 991425fe MB |
273 | ) |
| 274 | ||
| 275 | /* | |
| 276 | * SDRAM Controller configuration sequence. | |
| 277 | */ | |
| 540dcf1c KG |
278 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
| 279 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 280 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 281 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
| 282 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
| 991425fe MB |
283 | #endif |
| 284 | ||
| 285 | /* | |
| 286 | * Serial Port | |
| 287 | */ | |
| 288 | #define CONFIG_CONS_INDEX 1 | |
| 289 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 6d0f6bcf JCPV |
290 | #define CONFIG_SYS_NS16550 |
| 291 | #define CONFIG_SYS_NS16550_SERIAL | |
| 292 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 293 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 991425fe | 294 | |
| 6d0f6bcf | 295 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 991425fe MB |
296 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 297 | ||
| 6d0f6bcf JCPV |
298 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 299 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
| 991425fe | 300 | |
| 22d71a71 | 301 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 991425fe | 302 | /* Use the HUSH parser */ |
| 6d0f6bcf JCPV |
303 | #define CONFIG_SYS_HUSH_PARSER |
| 304 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 305 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 991425fe MB |
306 | #endif |
| 307 | ||
| bf0b542d | 308 | /* pass open firmware flat tree */ |
| 35cc4e48 | 309 | #define CONFIG_OF_LIBFDT 1 |
| bf0b542d | 310 | #define CONFIG_OF_BOARD_SETUP 1 |
| 5b8bc606 | 311 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| bf0b542d | 312 | |
| 991425fe MB |
313 | /* I2C */ |
| 314 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| 315 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| be5e6181 | 316 | #define CONFIG_FSL_I2C |
| b24f119d BW |
317 | #define CONFIG_I2C_MULTI_BUS |
| 318 | #define CONFIG_I2C_CMD_TREE | |
| 6d0f6bcf JCPV |
319 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 320 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 321 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
| 322 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 323 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 991425fe | 324 | |
| 80ddd226 | 325 | /* SPI */ |
| 8931ab17 | 326 | #define CONFIG_MPC8XXX_SPI |
| 80ddd226 | 327 | #undef CONFIG_SOFT_SPI /* SPI bit-banged */ |
| 80ddd226 BW |
328 | |
| 329 | /* GPIOs. Used as SPI chip selects */ | |
| 6d0f6bcf JCPV |
330 | #define CONFIG_SYS_GPIO1_PRELIM |
| 331 | #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ | |
| 332 | #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ | |
| 80ddd226 | 333 | |
| 991425fe | 334 | /* TSEC */ |
| 6d0f6bcf JCPV |
335 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
| 336 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) | |
| 337 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
| 338 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) | |
| 991425fe | 339 | |
| 8fe9bf61 | 340 | /* USB */ |
| 6d0f6bcf | 341 | #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ |
| 991425fe MB |
342 | |
| 343 | /* | |
| 344 | * General PCI | |
| 345 | * Addresses are mapped 1-1. | |
| 346 | */ | |
| 6d0f6bcf JCPV |
347 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 348 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
| 349 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 350 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
| 351 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
| 352 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 353 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
| 354 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
| 355 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 356 | ||
| 357 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
| 358 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
| 359 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 360 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
| 361 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
| 362 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
| 363 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 | |
| 364 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
| 365 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
| 991425fe MB |
366 | |
| 367 | #if defined(CONFIG_PCI) | |
| 368 | ||
| 8fe9bf61 | 369 | #define PCI_ONE_PCI1 |
| 991425fe MB |
370 | #if defined(PCI_64BIT) |
| 371 | #undef PCI_ALL_PCI1 | |
| 372 | #undef PCI_TWO_PCI1 | |
| 373 | #undef PCI_ONE_PCI1 | |
| 374 | #endif | |
| 375 | ||
| 376 | #define CONFIG_NET_MULTI | |
| 377 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 162338e1 IS |
378 | #define CONFIG_83XX_GENERIC_PCI |
| 379 | #define CONFIG_83XX_PCI_STREAMING | |
| 991425fe MB |
380 | |
| 381 | #undef CONFIG_EEPRO100 | |
| 382 | #undef CONFIG_TULIP | |
| 383 | ||
| 384 | #if !defined(CONFIG_PCI_PNP) | |
| 385 | #define PCI_ENET0_IOADDR 0xFIXME | |
| 386 | #define PCI_ENET0_MEMADDR 0xFIXME | |
| 53677ef1 | 387 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
| 991425fe MB |
388 | #endif |
| 389 | ||
| 390 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 6d0f6bcf | 391 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
| 991425fe MB |
392 | |
| 393 | #endif /* CONFIG_PCI */ | |
| 394 | ||
| 395 | /* | |
| 396 | * TSEC configuration | |
| 397 | */ | |
| 398 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
| 399 | ||
| 400 | #if defined(CONFIG_TSEC_ENET) | |
| 401 | #ifndef CONFIG_NET_MULTI | |
| 402 | #define CONFIG_NET_MULTI 1 | |
| 403 | #endif | |
| 404 | ||
| 405 | #define CONFIG_GMII 1 /* MII PHY management */ | |
| 255a3577 KP |
406 | #define CONFIG_TSEC1 1 |
| 407 | #define CONFIG_TSEC1_NAME "TSEC0" | |
| 408 | #define CONFIG_TSEC2 1 | |
| 409 | #define CONFIG_TSEC2_NAME "TSEC1" | |
| 991425fe MB |
410 | #define TSEC1_PHY_ADDR 0 |
| 411 | #define TSEC2_PHY_ADDR 1 | |
| 412 | #define TSEC1_PHYIDX 0 | |
| 413 | #define TSEC2_PHYIDX 0 | |
| 3a79013e AF |
414 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 415 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 991425fe MB |
416 | |
| 417 | /* Options are: TSEC[0-1] */ | |
| 418 | #define CONFIG_ETHPRIME "TSEC0" | |
| 419 | ||
| 420 | #endif /* CONFIG_TSEC_ENET */ | |
| 421 | ||
| 422 | /* | |
| 423 | * Configure on-board RTC | |
| 424 | */ | |
| 425 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
| 6d0f6bcf | 426 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
| 991425fe MB |
427 | |
| 428 | /* | |
| 429 | * Environment | |
| 430 | */ | |
| 6d0f6bcf | 431 | #ifndef CONFIG_SYS_RAMBOOT |
| 5a1aceb0 | 432 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 433 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 0e8d1586 JCPV |
434 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 435 | #define CONFIG_ENV_SIZE 0x2000 | |
| 991425fe MB |
436 | |
| 437 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
438 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 439 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 991425fe MB |
440 | |
| 441 | #else | |
| 6d0f6bcf | 442 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
| 93f6d725 | 443 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 6d0f6bcf | 444 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 0e8d1586 | 445 | #define CONFIG_ENV_SIZE 0x2000 |
| 991425fe MB |
446 | #endif |
| 447 | ||
| 448 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 449 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 991425fe | 450 | |
| 8ea5499a | 451 | |
| 659e2f67 JL |
452 | /* |
| 453 | * BOOTP options | |
| 454 | */ | |
| 455 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 456 | #define CONFIG_BOOTP_BOOTPATH | |
| 457 | #define CONFIG_BOOTP_GATEWAY | |
| 458 | #define CONFIG_BOOTP_HOSTNAME | |
| 459 | ||
| 460 | ||
| 8ea5499a JL |
461 | /* |
| 462 | * Command line configuration. | |
| 463 | */ | |
| 464 | #include <config_cmd_default.h> | |
| 465 | ||
| 466 | #define CONFIG_CMD_PING | |
| 467 | #define CONFIG_CMD_I2C | |
| 468 | #define CONFIG_CMD_DATE | |
| 469 | #define CONFIG_CMD_MII | |
| 470 | ||
| 991425fe | 471 | #if defined(CONFIG_PCI) |
| 8ea5499a | 472 | #define CONFIG_CMD_PCI |
| 991425fe | 473 | #endif |
| 8ea5499a | 474 | |
| 6d0f6bcf | 475 | #if defined(CONFIG_SYS_RAMBOOT) |
| bdab39d3 | 476 | #undef CONFIG_CMD_SAVEENV |
| 8ea5499a | 477 | #undef CONFIG_CMD_LOADS |
| 991425fe MB |
478 | #endif |
| 479 | ||
| 991425fe MB |
480 | |
| 481 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 482 | ||
| 483 | /* | |
| 484 | * Miscellaneous configurable options | |
| 485 | */ | |
| 6d0f6bcf JCPV |
486 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 487 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 488 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 991425fe | 489 | |
| 8ea5499a | 490 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 491 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 991425fe | 492 | #else |
| 6d0f6bcf | 493 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 991425fe MB |
494 | #endif |
| 495 | ||
| 6d0f6bcf JCPV |
496 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 497 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 498 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 499 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 991425fe MB |
500 | |
| 501 | /* | |
| 502 | * For booting Linux, the board info and command line data | |
| 503 | * have to be in the first 8 MB of memory, since this is | |
| 504 | * the maximum mapped by the Linux kernel during initialization. | |
| 505 | */ | |
| 6d0f6bcf | 506 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| 991425fe | 507 | |
| 6d0f6bcf | 508 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
| 991425fe MB |
509 | |
| 510 | #if 1 /*528/264*/ | |
| 6d0f6bcf | 511 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
512 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 513 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 514 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
515 | HRCWL_VCO_1X2 |\ |
| 516 | HRCWL_CORE_TO_CSB_2X1) | |
| 517 | #elif 0 /*396/132*/ | |
| 6d0f6bcf | 518 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
519 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 520 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 521 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
522 | HRCWL_VCO_1X4 |\ |
| 523 | HRCWL_CORE_TO_CSB_3X1) | |
| 524 | #elif 0 /*264/132*/ | |
| 6d0f6bcf | 525 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
526 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 527 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 528 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
529 | HRCWL_VCO_1X4 |\ |
| 530 | HRCWL_CORE_TO_CSB_2X1) | |
| 531 | #elif 0 /*132/132*/ | |
| 6d0f6bcf | 532 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
533 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 534 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 535 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
536 | HRCWL_VCO_1X4 |\ |
| 537 | HRCWL_CORE_TO_CSB_1X1) | |
| 538 | #elif 0 /*264/264 */ | |
| 6d0f6bcf | 539 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
540 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 541 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 542 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
543 | HRCWL_VCO_1X4 |\ |
| 544 | HRCWL_CORE_TO_CSB_1X1) | |
| 545 | #endif | |
| 546 | ||
| 447ad576 | 547 | #ifdef CONFIG_PCISLAVE |
| 6d0f6bcf | 548 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 447ad576 IS |
549 | HRCWH_PCI_AGENT |\ |
| 550 | HRCWH_64_BIT_PCI |\ | |
| 551 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
| 552 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
| 553 | HRCWH_CORE_ENABLE |\ | |
| 554 | HRCWH_FROM_0X00000100 |\ | |
| 555 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 556 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 557 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 558 | HRCWH_TSEC1M_IN_GMII |\ | |
| 559 | HRCWH_TSEC2M_IN_GMII ) | |
| 560 | #else | |
| 991425fe | 561 | #if defined(PCI_64BIT) |
| 6d0f6bcf | 562 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 991425fe MB |
563 | HRCWH_PCI_HOST |\ |
| 564 | HRCWH_64_BIT_PCI |\ | |
| 565 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 566 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
| 567 | HRCWH_CORE_ENABLE |\ | |
| 568 | HRCWH_FROM_0X00000100 |\ | |
| 569 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 570 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 571 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 572 | HRCWH_TSEC1M_IN_GMII |\ | |
| 573 | HRCWH_TSEC2M_IN_GMII ) | |
| 574 | #else | |
| 6d0f6bcf | 575 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 991425fe MB |
576 | HRCWH_PCI_HOST |\ |
| 577 | HRCWH_32_BIT_PCI |\ | |
| 578 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 579 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
| 580 | HRCWH_CORE_ENABLE |\ | |
| 581 | HRCWH_FROM_0X00000100 |\ | |
| 582 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 583 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 584 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 585 | HRCWH_TSEC1M_IN_GMII |\ | |
| 586 | HRCWH_TSEC2M_IN_GMII ) | |
| 447ad576 IS |
587 | #endif /* PCI_64BIT */ |
| 588 | #endif /* CONFIG_PCISLAVE */ | |
| 991425fe | 589 | |
| a5fe514e LN |
590 | /* |
| 591 | * System performance | |
| 592 | */ | |
| 6d0f6bcf JCPV |
593 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
| 594 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
| 595 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ | |
| 596 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
| 597 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
| 598 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
| a5fe514e | 599 | |
| 991425fe | 600 | /* System IO Config */ |
| 6d0f6bcf JCPV |
601 | #define CONFIG_SYS_SICRH SICRH_TSOBI1 |
| 602 | #define CONFIG_SYS_SICRL SICRL_LDP_A | |
| 991425fe | 603 | |
| 6d0f6bcf JCPV |
604 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
| 605 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
| 991425fe | 606 | |
| 6d0f6bcf | 607 | /* #define CONFIG_SYS_HID0_FINAL (\ |
| 991425fe MB |
608 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
| 609 | HID0_ENABLE_M_BIT |\ | |
| 610 | HID0_ENABLE_ADDRESS_BROADCAST ) */ | |
| 611 | ||
| 612 | ||
| 6d0f6bcf | 613 | #define CONFIG_SYS_HID2 HID2_HBE |
| 31d82672 | 614 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 991425fe MB |
615 | |
| 616 | /* DDR @ 0x00000000 */ | |
| 6d0f6bcf JCPV |
617 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 618 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 991425fe MB |
619 | |
| 620 | /* PCI @ 0x80000000 */ | |
| 621 | #ifdef CONFIG_PCI | |
| 6d0f6bcf JCPV |
622 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 623 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 624 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 625 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 991425fe | 626 | #else |
| 6d0f6bcf JCPV |
627 | #define CONFIG_SYS_IBAT1L (0) |
| 628 | #define CONFIG_SYS_IBAT1U (0) | |
| 629 | #define CONFIG_SYS_IBAT2L (0) | |
| 630 | #define CONFIG_SYS_IBAT2U (0) | |
| 991425fe MB |
631 | #endif |
| 632 | ||
| 8fe9bf61 | 633 | #ifdef CONFIG_MPC83XX_PCI2 |
| 6d0f6bcf JCPV |
634 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 635 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 636 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 637 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 8fe9bf61 | 638 | #else |
| 6d0f6bcf JCPV |
639 | #define CONFIG_SYS_IBAT3L (0) |
| 640 | #define CONFIG_SYS_IBAT3U (0) | |
| 641 | #define CONFIG_SYS_IBAT4L (0) | |
| 642 | #define CONFIG_SYS_IBAT4U (0) | |
| 8fe9bf61 | 643 | #endif |
| 991425fe | 644 | |
| 8fe9bf61 | 645 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
| 6d0f6bcf JCPV |
646 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 647 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 991425fe | 648 | |
| 8fe9bf61 | 649 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
| c1230980 SW |
650 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ |
| 651 | BATL_GUARDEDSTORAGE) | |
| 6d0f6bcf JCPV |
652 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 653 | ||
| 654 | #define CONFIG_SYS_IBAT7L (0) | |
| 655 | #define CONFIG_SYS_IBAT7U (0) | |
| 656 | ||
| 657 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 658 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 659 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 660 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 661 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
| 662 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 663 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 664 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 665 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
| 666 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| 667 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 668 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 669 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 670 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 671 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
| 672 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| 991425fe MB |
673 | |
| 674 | /* | |
| 675 | * Internal Definitions | |
| 676 | * | |
| 677 | * Boot Flags | |
| 678 | */ | |
| 679 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 680 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 681 | ||
| 8ea5499a | 682 | #if defined(CONFIG_CMD_KGDB) |
| 991425fe MB |
683 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 684 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 685 | #endif | |
| 686 | ||
| 687 | /* | |
| 688 | * Environment Configuration | |
| 689 | */ | |
| 690 | #define CONFIG_ENV_OVERWRITE | |
| 691 | ||
| 692 | #if defined(CONFIG_TSEC_ENET) | |
| 693 | #define CONFIG_ETHADDR 00:04:9f:ef:23:33 | |
| 694 | #define CONFIG_HAS_ETH1 | |
| 10327dc5 | 695 | #define CONFIG_HAS_ETH0 |
| 991425fe MB |
696 | #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 |
| 697 | #endif | |
| 698 | ||
| bf0b542d | 699 | #define CONFIG_IPADDR 192.168.1.253 |
| 991425fe MB |
700 | |
| 701 | #define CONFIG_HOSTNAME mpc8349emds | |
| bf0b542d KP |
702 | #define CONFIG_ROOTPATH /nfsroot/rootfs |
| 703 | #define CONFIG_BOOTFILE uImage | |
| 991425fe MB |
704 | |
| 705 | #define CONFIG_SERVERIP 192.168.1.1 | |
| 706 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
| 707 | #define CONFIG_NETMASK 255.255.255.0 | |
| 708 | ||
| b2115757 | 709 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ |
| 991425fe MB |
710 | |
| 711 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
| 712 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 713 | ||
| 714 | #define CONFIG_BAUDRATE 115200 | |
| 715 | ||
| 716 | #define CONFIG_PREBOOT "echo;" \ | |
| 32bf3d14 | 717 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
| 991425fe MB |
718 | "echo" |
| 719 | ||
| 720 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 721 | "netdev=eth0\0" \ | |
| 722 | "hostname=mpc8349emds\0" \ | |
| 723 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 724 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 725 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 726 | "addip=setenv bootargs ${bootargs} " \ | |
| 727 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 728 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 729 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
| 730 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 731 | "bootm ${kernel_addr}\0" \ | |
| 732 | "flash_self=run ramargs addip addtty;" \ | |
| 733 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 734 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
| 735 | "bootm\0" \ | |
| 991425fe MB |
736 | "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ |
| 737 | "update=protect off fe000000 fe03ffff; " \ | |
| 738 | "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ | |
| d8ab58b2 | 739 | "upd=run load update\0" \ |
| bf0b542d KP |
740 | "fdtaddr=400000\0" \ |
| 741 | "fdtfile=mpc8349emds.dtb\0" \ | |
| 991425fe MB |
742 | "" |
| 743 | ||
| bf0b542d KP |
744 | #define CONFIG_NFSBOOTCOMMAND \ |
| 745 | "setenv bootargs root=/dev/nfs rw " \ | |
| 746 | "nfsroot=$serverip:$rootpath " \ | |
| 747 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 748 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 749 | "tftp $loadaddr $bootfile;" \ | |
| 750 | "tftp $fdtaddr $fdtfile;" \ | |
| 751 | "bootm $loadaddr - $fdtaddr" | |
| 752 | ||
| 753 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 754 | "setenv bootargs root=/dev/ram rw " \ | |
| 755 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 756 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 757 | "tftp $loadaddr $bootfile;" \ | |
| 758 | "tftp $fdtaddr $fdtfile;" \ | |
| 759 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 760 | ||
| 991425fe MB |
761 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 762 | ||
| 763 | #endif /* __CONFIG_H */ |