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19580e66 DL |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #ifndef __CONFIG_H | |
22 | #define __CONFIG_H | |
23 | ||
19580e66 DL |
24 | /* |
25 | * High Level Configuration Options | |
26 | */ | |
27 | #define CONFIG_E300 1 /* E300 family */ | |
28 | #define CONFIG_MPC83XX 1 /* MPC83XX family */ | |
29 | #define CONFIG_MPC837X 1 /* MPC837X CPU specific */ | |
30 | #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ | |
31 | ||
32 | /* | |
33 | * System Clock Setup | |
34 | */ | |
35 | #ifdef CONFIG_PCISLAVE | |
36 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
37 | #else | |
38 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
39 | #endif | |
40 | ||
41 | #ifndef CONFIG_SYS_CLK_FREQ | |
42 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
43 | #endif | |
44 | ||
45 | /* | |
46 | * Hardware Reset Configuration Word | |
47 | * if CLKIN is 66MHz, then | |
48 | * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz | |
49 | */ | |
50 | #define CFG_HRCW_LOW (\ | |
51 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
52 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
53 | HRCWL_SVCOD_DIV_2 |\ | |
54 | HRCWL_CSB_TO_CLKIN_6X1 |\ | |
55 | HRCWL_CORE_TO_CSB_1_5X1) | |
56 | ||
57 | #ifdef CONFIG_PCISLAVE | |
58 | #define CFG_HRCW_HIGH (\ | |
59 | HRCWH_PCI_AGENT |\ | |
60 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
61 | HRCWH_CORE_ENABLE |\ | |
62 | HRCWH_FROM_0XFFF00100 |\ | |
63 | HRCWH_BOOTSEQ_DISABLE |\ | |
64 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
65 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
66 | HRCWH_RL_EXT_LEGACY |\ | |
67 | HRCWH_TSEC1M_IN_RGMII |\ | |
68 | HRCWH_TSEC2M_IN_RGMII |\ | |
69 | HRCWH_BIG_ENDIAN |\ | |
70 | HRCWH_LDP_CLEAR) | |
71 | #else | |
72 | #define CFG_HRCW_HIGH (\ | |
73 | HRCWH_PCI_HOST |\ | |
74 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
75 | HRCWH_CORE_ENABLE |\ | |
76 | HRCWH_FROM_0X00000100 |\ | |
77 | HRCWH_BOOTSEQ_DISABLE |\ | |
78 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
79 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
80 | HRCWH_RL_EXT_LEGACY |\ | |
81 | HRCWH_TSEC1M_IN_RGMII |\ | |
82 | HRCWH_TSEC2M_IN_RGMII |\ | |
83 | HRCWH_BIG_ENDIAN |\ | |
84 | HRCWH_LDP_CLEAR) | |
85 | #endif | |
86 | ||
bd4458cb DL |
87 | /* Arbiter Configuration Register */ |
88 | #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ | |
89 | #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ | |
90 | ||
91 | /* System Priority Control Register */ | |
92 | #define CFG_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ | |
93 | ||
19580e66 | 94 | /* |
bd4458cb | 95 | * IP blocks clock configuration |
19580e66 DL |
96 | */ |
97 | #define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ | |
98 | #define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ | |
20007848 | 99 | #define CFG_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ |
19580e66 DL |
100 | |
101 | /* | |
102 | * System IO Config | |
103 | */ | |
104 | #define CFG_SICRH 0x00000000 | |
105 | #define CFG_SICRL 0x00000000 | |
106 | ||
107 | /* | |
108 | * Output Buffer Impedance | |
109 | */ | |
110 | #define CFG_OBIR 0x31100000 | |
111 | ||
112 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
113 | #define CONFIG_BOARD_EARLY_INIT_R | |
114 | ||
115 | /* | |
116 | * IMMR new address | |
117 | */ | |
118 | #define CFG_IMMR 0xE0000000 | |
119 | ||
120 | /* | |
121 | * DDR Setup | |
122 | */ | |
123 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ | |
124 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
125 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
126 | #define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
127 | #define CFG_83XX_DDR_USES_CS0 | |
128 | #define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ | |
129 | ||
130 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
131 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
132 | ||
133 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
134 | #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
135 | ||
136 | #if defined(CONFIG_SPD_EEPROM) | |
137 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ | |
138 | #else | |
139 | /* | |
140 | * Manually set up DDR parameters | |
7e74d63d | 141 | * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM |
19580e66 DL |
142 | * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 |
143 | */ | |
144 | #define CFG_DDR_SIZE 512 /* MB */ | |
145 | #define CFG_DDR_CS0_BNDS 0x0000001f | |
146 | #define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ | |
147 | | 0x00010000 /* ODT_WR to CSn */ \ | |
148 | | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) | |
149 | /* 0x80010202 */ | |
150 | #define CFG_DDR_TIMING_3 0x00000000 | |
151 | #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | |
152 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | |
153 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
154 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
155 | | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
156 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
157 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
158 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
159 | /* 0x00620802 */ | |
160 | #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ | |
161 | | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | |
162 | | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | |
163 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | |
164 | | (13 << TIMING_CFG1_REFREC_SHIFT ) \ | |
165 | | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ | |
166 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | |
167 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
168 | /* 0x3935d322 */ | |
7e74d63d | 169 | #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ |
19580e66 DL |
170 | | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ |
171 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | |
172 | | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
173 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
174 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
175 | | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) | |
7e74d63d | 176 | /* 0x131088c8 */ |
19580e66 DL |
177 | #define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ |
178 | | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) | |
179 | /* 0x03E00100 */ | |
180 | #define CFG_DDR_SDRAM_CFG 0x43000000 | |
181 | #define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ | |
7e74d63d | 182 | #define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ |
19580e66 | 183 | | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) |
7e74d63d | 184 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
19580e66 DL |
185 | #define CFG_DDR_MODE2 0x00000000 |
186 | #endif | |
187 | ||
188 | /* | |
189 | * Memory test | |
190 | */ | |
191 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
192 | #define CFG_MEMTEST_START 0x00040000 /* memtest region */ | |
193 | #define CFG_MEMTEST_END 0x00140000 | |
194 | ||
195 | /* | |
196 | * The reserved memory | |
197 | */ | |
198 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
199 | ||
200 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
201 | #define CFG_RAMBOOT | |
202 | #else | |
203 | #undef CFG_RAMBOOT | |
204 | #endif | |
205 | ||
921d4b19 | 206 | /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ |
19580e66 DL |
207 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
208 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
209 | ||
210 | /* | |
211 | * Initial RAM Base Address Setup | |
212 | */ | |
213 | #define CFG_INIT_RAM_LOCK 1 | |
214 | #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
215 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ | |
216 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
217 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
218 | ||
219 | /* | |
220 | * Local Bus Configuration & Clock Setup | |
221 | */ | |
222 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) | |
223 | #define CFG_LBC_LBCR 0x00000000 | |
224 | ||
225 | /* | |
226 | * FLASH on the Local Bus | |
227 | */ | |
228 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
229 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
230 | #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ | |
231 | #define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ | |
232 | ||
233 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ | |
234 | #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ | |
235 | ||
ded08317 DL |
236 | #define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \ |
237 | | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ | |
238 | | BR_V ) /* valid */ | |
239 | #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | |
240 | | OR_UPM_XAM \ | |
241 | | OR_GPCM_CSNT \ | |
242 | | OR_GPCM_ACS_0b11 \ | |
243 | | OR_GPCM_XACS \ | |
244 | | OR_GPCM_SCY_15 \ | |
245 | | OR_GPCM_TRLX \ | |
246 | | OR_GPCM_EHTR \ | |
247 | | OR_GPCM_EAD ) | |
248 | /* 0xFE000FF7 */ | |
19580e66 DL |
249 | |
250 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
251 | #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ | |
252 | ||
253 | #undef CFG_FLASH_CHECKSUM | |
254 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
255 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
256 | ||
257 | /* | |
258 | * BCSR on the Local Bus | |
259 | */ | |
260 | #define CFG_BCSR 0xF8000000 | |
261 | #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ | |
262 | #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ | |
263 | ||
264 | #define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ | |
265 | #define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ | |
266 | ||
267 | /* | |
268 | * NAND Flash on the Local Bus | |
269 | */ | |
270 | #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ | |
271 | #define CFG_BR3_PRELIM ( CFG_NAND_BASE \ | |
272 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
273 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
274 | | BR_MS_FCM /* MSEL = FCM */ \ | |
275 | | BR_V ) /* valid */ | |
276 | #define CFG_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ | |
277 | | OR_FCM_CSCT \ | |
278 | | OR_FCM_CST \ | |
279 | | OR_FCM_CHT \ | |
280 | | OR_FCM_SCY_1 \ | |
281 | | OR_FCM_TRLX \ | |
282 | | OR_FCM_EHTR ) | |
283 | /* 0xFFFF8396 */ | |
284 | ||
285 | #define CFG_LBLAWBAR3_PRELIM CFG_NAND_BASE | |
286 | #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ | |
287 | ||
288 | /* | |
289 | * Serial Port | |
290 | */ | |
291 | #define CONFIG_CONS_INDEX 1 | |
292 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
293 | #define CFG_NS16550 | |
294 | #define CFG_NS16550_SERIAL | |
295 | #define CFG_NS16550_REG_SIZE 1 | |
296 | #define CFG_NS16550_CLK get_bus_freq(0) | |
297 | ||
298 | #define CFG_BAUDRATE_TABLE \ | |
299 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
300 | ||
301 | #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) | |
302 | #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) | |
303 | ||
304 | /* Use the HUSH parser */ | |
305 | #define CFG_HUSH_PARSER | |
306 | #ifdef CFG_HUSH_PARSER | |
307 | #define CFG_PROMPT_HUSH_PS2 "> " | |
308 | #endif | |
309 | ||
310 | /* Pass open firmware flat tree */ | |
311 | #define CONFIG_OF_LIBFDT 1 | |
312 | #define CONFIG_OF_BOARD_SETUP 1 | |
5b8bc606 | 313 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
19580e66 DL |
314 | |
315 | /* I2C */ | |
316 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
317 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
318 | #define CONFIG_FSL_I2C | |
319 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
320 | #define CFG_I2C_SLAVE 0x7F | |
321 | #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
322 | #define CFG_I2C_OFFSET 0x3000 | |
323 | #define CFG_I2C2_OFFSET 0x3100 | |
324 | ||
325 | /* | |
326 | * Config on-board RTC | |
327 | */ | |
328 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
329 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
330 | ||
331 | /* | |
332 | * General PCI | |
333 | * Addresses are mapped 1-1. | |
334 | */ | |
335 | #define CFG_PCI_MEM_BASE 0x80000000 | |
336 | #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE | |
337 | #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
338 | #define CFG_PCI_MMIO_BASE 0x90000000 | |
339 | #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE | |
340 | #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
a7ba32d4 | 341 | #define CFG_PCI_IO_BASE 0x00000000 |
19580e66 DL |
342 | #define CFG_PCI_IO_PHYS 0xE0300000 |
343 | #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ | |
344 | ||
345 | #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE | |
346 | #define CFG_PCI_SLV_MEM_BUS 0x00000000 | |
347 | #define CFG_PCI_SLV_MEM_SIZE 0x80000000 | |
348 | ||
349 | #ifdef CONFIG_PCI | |
350 | #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ | |
351 | #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ | |
352 | ||
353 | #define CONFIG_NET_MULTI | |
354 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
355 | ||
356 | #undef CONFIG_EEPRO100 | |
357 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
358 | #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ | |
359 | #endif /* CONFIG_PCI */ | |
360 | ||
361 | #ifndef CONFIG_NET_MULTI | |
362 | #define CONFIG_NET_MULTI 1 | |
363 | #endif | |
364 | ||
365 | /* | |
366 | * TSEC | |
367 | */ | |
368 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
369 | #define CFG_TSEC1_OFFSET 0x24000 | |
370 | #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) | |
371 | #define CFG_TSEC2_OFFSET 0x25000 | |
372 | #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) | |
373 | ||
374 | /* | |
375 | * TSEC ethernet configuration | |
376 | */ | |
377 | #define CONFIG_MII 1 /* MII PHY management */ | |
378 | #define CONFIG_TSEC1 1 | |
379 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
380 | #define CONFIG_TSEC2 1 | |
381 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
382 | #define TSEC1_PHY_ADDR 2 | |
383 | #define TSEC2_PHY_ADDR 3 | |
384 | #define TSEC1_PHYIDX 0 | |
385 | #define TSEC2_PHYIDX 0 | |
386 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
387 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
388 | ||
389 | /* Options are: TSEC[0-1] */ | |
390 | #define CONFIG_ETHPRIME "eTSEC1" | |
391 | ||
6f8c85e8 DL |
392 | /* SERDES */ |
393 | #define CONFIG_FSL_SERDES | |
394 | #define CONFIG_FSL_SERDES1 0xe3000 | |
395 | #define CONFIG_FSL_SERDES2 0xe3100 | |
396 | ||
2eeb3e4f DL |
397 | /* |
398 | * SATA | |
399 | */ | |
400 | #define CONFIG_LIBATA | |
401 | #define CONFIG_FSL_SATA | |
402 | ||
403 | #define CFG_SATA_MAX_DEVICE 2 | |
404 | #define CONFIG_SATA1 | |
405 | #define CFG_SATA1_OFFSET 0x18000 | |
406 | #define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET) | |
407 | #define CFG_SATA1_FLAGS FLAGS_DMA | |
408 | #define CONFIG_SATA2 | |
409 | #define CFG_SATA2_OFFSET 0x19000 | |
410 | #define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET) | |
411 | #define CFG_SATA2_FLAGS FLAGS_DMA | |
412 | ||
413 | #ifdef CONFIG_FSL_SATA | |
414 | #define CONFIG_LBA48 | |
415 | #define CONFIG_CMD_SATA | |
416 | #define CONFIG_DOS_PARTITION | |
417 | #define CONFIG_CMD_EXT2 | |
418 | #endif | |
419 | ||
19580e66 DL |
420 | /* |
421 | * Environment | |
422 | */ | |
423 | #ifndef CFG_RAMBOOT | |
424 | #define CFG_ENV_IS_IN_FLASH 1 | |
921d4b19 | 425 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
19580e66 DL |
426 | #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
427 | #define CFG_ENV_SIZE 0x2000 | |
428 | #else | |
429 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ | |
430 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
431 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
432 | #define CFG_ENV_SIZE 0x2000 | |
433 | #endif | |
434 | ||
435 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
436 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
437 | ||
438 | /* | |
439 | * BOOTP options | |
440 | */ | |
441 | #define CONFIG_BOOTP_BOOTFILESIZE | |
442 | #define CONFIG_BOOTP_BOOTPATH | |
443 | #define CONFIG_BOOTP_GATEWAY | |
444 | #define CONFIG_BOOTP_HOSTNAME | |
445 | ||
446 | ||
447 | /* | |
448 | * Command line configuration. | |
449 | */ | |
450 | #include <config_cmd_default.h> | |
451 | ||
452 | #define CONFIG_CMD_PING | |
453 | #define CONFIG_CMD_I2C | |
454 | #define CONFIG_CMD_MII | |
455 | #define CONFIG_CMD_DATE | |
456 | ||
457 | #if defined(CONFIG_PCI) | |
458 | #define CONFIG_CMD_PCI | |
459 | #endif | |
460 | ||
461 | #if defined(CFG_RAMBOOT) | |
462 | #undef CONFIG_CMD_ENV | |
463 | #undef CONFIG_CMD_LOADS | |
464 | #endif | |
465 | ||
466 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
467 | ||
468 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
469 | ||
470 | /* | |
471 | * Miscellaneous configurable options | |
472 | */ | |
473 | #define CFG_LONGHELP /* undef to save memory */ | |
474 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
475 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
476 | ||
477 | #if defined(CONFIG_CMD_KGDB) | |
478 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
479 | #else | |
480 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
481 | #endif | |
482 | ||
483 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
484 | #define CFG_MAXARGS 16 /* max number of command args */ | |
485 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
486 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
487 | ||
488 | /* | |
489 | * For booting Linux, the board info and command line data | |
490 | * have to be in the first 8 MB of memory, since this is | |
491 | * the maximum mapped by the Linux kernel during initialization. | |
492 | */ | |
493 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
494 | ||
495 | /* | |
496 | * Core HID Setup | |
497 | */ | |
498 | #define CFG_HID0_INIT 0x000000000 | |
499 | #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
500 | #define CFG_HID2 HID2_HBE | |
501 | ||
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502 | /* |
503 | * MMU Setup | |
504 | */ | |
31d82672 | 505 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
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506 | |
507 | /* DDR: cache cacheable */ | |
508 | #define CFG_SDRAM_LOWER CFG_SDRAM_BASE | |
509 | #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) | |
510 | ||
511 | #define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) | |
512 | #define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) | |
513 | #define CFG_DBAT0L CFG_IBAT0L | |
514 | #define CFG_DBAT0U CFG_IBAT0U | |
515 | ||
516 | #define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) | |
517 | #define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) | |
518 | #define CFG_DBAT1L CFG_IBAT1L | |
519 | #define CFG_DBAT1U CFG_IBAT1U | |
520 | ||
521 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
522 | #define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ | |
523 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
524 | #define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) | |
525 | #define CFG_DBAT2L CFG_IBAT2L | |
526 | #define CFG_DBAT2U CFG_IBAT2U | |
527 | ||
528 | /* BCSR: cache-inhibit and guarded */ | |
529 | #define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \ | |
530 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
531 | #define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) | |
532 | #define CFG_DBAT3L CFG_IBAT3L | |
533 | #define CFG_DBAT3U CFG_IBAT3U | |
534 | ||
535 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
536 | #define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
537 | #define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
538 | #define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ | |
539 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
540 | #define CFG_DBAT4U CFG_IBAT4U | |
541 | ||
542 | /* Stack in dcache: cacheable, no memory coherence */ | |
543 | #define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) | |
544 | #define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
545 | #define CFG_DBAT5L CFG_IBAT5L | |
546 | #define CFG_DBAT5U CFG_IBAT5U | |
547 | ||
548 | #ifdef CONFIG_PCI | |
549 | /* PCI MEM space: cacheable */ | |
550 | #define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) | |
551 | #define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
552 | #define CFG_DBAT6L CFG_IBAT6L | |
553 | #define CFG_DBAT6U CFG_IBAT6U | |
554 | /* PCI MMIO space: cache-inhibit and guarded */ | |
555 | #define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ | |
556 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
557 | #define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
558 | #define CFG_DBAT7L CFG_IBAT7L | |
559 | #define CFG_DBAT7U CFG_IBAT7U | |
560 | #else | |
561 | #define CFG_IBAT6L (0) | |
562 | #define CFG_IBAT6U (0) | |
563 | #define CFG_IBAT7L (0) | |
564 | #define CFG_IBAT7U (0) | |
565 | #define CFG_DBAT6L CFG_IBAT6L | |
566 | #define CFG_DBAT6U CFG_IBAT6U | |
567 | #define CFG_DBAT7L CFG_IBAT7L | |
568 | #define CFG_DBAT7U CFG_IBAT7U | |
569 | #endif | |
570 | ||
571 | /* | |
572 | * Internal Definitions | |
573 | * | |
574 | * Boot Flags | |
575 | */ | |
576 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
577 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
578 | ||
579 | #if defined(CONFIG_CMD_KGDB) | |
580 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
581 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
582 | #endif | |
583 | ||
584 | /* | |
585 | * Environment Configuration | |
586 | */ | |
587 | ||
588 | #define CONFIG_ENV_OVERWRITE | |
589 | ||
590 | #if defined(CONFIG_TSEC_ENET) | |
591 | #define CONFIG_HAS_ETH0 | |
592 | #define CONFIG_ETHADDR 00:E0:0C:00:83:79 | |
593 | #define CONFIG_HAS_ETH1 | |
594 | #define CONFIG_ETH1ADDR 00:E0:0C:00:83:78 | |
595 | #endif | |
596 | ||
597 | #define CONFIG_BAUDRATE 115200 | |
598 | ||
b2115757 | 599 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ |
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600 | |
601 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
602 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
603 | ||
604 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
605 | "netdev=eth0\0" \ | |
606 | "consoledev=ttyS0\0" \ | |
607 | "ramdiskaddr=1000000\0" \ | |
608 | "ramdiskfile=ramfs.83xx\0" \ | |
609 | "fdtaddr=400000\0" \ | |
270fe261 | 610 | "fdtfile=mpc8379_mds.dtb\0" \ |
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611 | "" |
612 | ||
613 | #define CONFIG_NFSBOOTCOMMAND \ | |
614 | "setenv bootargs root=/dev/nfs rw " \ | |
615 | "nfsroot=$serverip:$rootpath " \ | |
616 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
617 | "console=$consoledev,$baudrate $othbootargs;" \ | |
618 | "tftp $loadaddr $bootfile;" \ | |
619 | "tftp $fdtaddr $fdtfile;" \ | |
620 | "bootm $loadaddr - $fdtaddr" | |
621 | ||
622 | #define CONFIG_RAMBOOTCOMMAND \ | |
623 | "setenv bootargs root=/dev/ram rw " \ | |
624 | "console=$consoledev,$baudrate $othbootargs;" \ | |
625 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
626 | "tftp $loadaddr $bootfile;" \ | |
627 | "tftp $fdtaddr $fdtfile;" \ | |
628 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
629 | ||
630 | ||
631 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
632 | ||
633 | #endif /* __CONFIG_H */ |