[people/ms/u-boot.git] / include / configs / MPC8544DS.h

/*
 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8544ds board configuration file
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xfff80000
#endif

#define CONFIG_PCI1		1	/* PCI controller 1 */
#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */

#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000
#define CONFIG_PANIC_HANG	/* do not reset board on panic */

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Memory map
 *
 * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
 *
 * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
 *
 * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
 *
 * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
 * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
 *
 * Localbus cacheable
 *
 * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
 * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
 *
 * Localbus non-cacheable
 *
 * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
 * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
 * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
 *
 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* boot TLB */

#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M */

#define CONFIG_SYS_BR0_PRELIM		0xff801001
#define CONFIG_SYS_BR1_PRELIM		0xfe801001

#define CONFIG_SYS_OR0_PRELIM		0xff806e65
#define CONFIG_SYS_OR1_PRELIM		0xff806e65

#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000

#define CONFIG_SYS_BR2_PRELIM		0xf8201001	/* port size 16bit */
#define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/

#define CONFIG_SYS_BR3_PRELIM		0xf8100801	/* port size 8bit */
#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/

#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
#define PIXIS_ID		0x0	/* Board ID at offset 0 */
#define PIXIS_VER		0x1	/* Board version at offset 1 */
#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
					 * register */
#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
#define PIXIS_VCTL		0x10	/* VELA Control Register */
#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
#define PIXIS_VSPEED2		0x1d	/* VELA VSpeed 2 */
#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
#define PIXIS_VSPEED2_TSEC1SER	0x2
#define PIXIS_VSPEED2_TSEC3SER	0x1
#define PIXIS_VCFGEN1_TSEC1SER	0x20
#define PIXIS_VCFGEN1_TSEC3SER	0x40
#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)

#define CONFIG_SYS_INIT_RAM_LOCK      1
#define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCIE_VIRT		0x80000000	/* 1G PCIE TLB */
#define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
#define CONFIG_SYS_PCI_VIRT		0xc0000000	/* 512M PCI TLB */
#define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */

#define CONFIG_SYS_PCI1_MEM_VIRT	0xc0000000
#define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0xc0000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */

/* controller 2, Slot 1, tgtid 1, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
#define CONFIG_SYS_PCIE2_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xe1010000
#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 1, Slot 2,tgtid 2, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xe1020000
#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

/* controller 3, direct to uli, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_NAME		"ULI"
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
#define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xb0000000
#define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
#define CONFIG_SYS_PCIE3_IO_VIRT	0xb0100000	/* reuse mem LAW */
#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
#define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
#define CONFIG_SYS_PCIE3_MEM_VIRT2	0xb0200000
#define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
#define CONFIG_SYS_PCIE3_MEM_PHYS2	0xb0200000
#define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */

#if defined(CONFIG_PCI)

/*PCIE video card used*/
#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT

/*PCI video card used*/
/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/

/* video */

#if defined(CONFIG_VIDEO)
#define CONFIG_BIOSEMU
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#ifndef CONFIG_PCI_PNP
	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SCSI_AHCI

#ifdef CONFIG_SCSI_AHCI
#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
#define CONFIG_SYS_SCSI_MAX_LUN	1
#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
#endif /* SCSCI */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC3"

#define CONFIG_PIXIS_SGMII_CMD
#define CONFIG_FSL_SGMII_RISER	1
#define SGMII_RISER_PHY_OFFSET	0x1c

#define TSEC1_PHY_ADDR		0
#define TSEC3_PHY_ADDR		1

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX		0
#define TSEC3_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC1"

#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) */
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR		0xfff80000
#else
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#endif
#define CONFIG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

/*
 * USB
 */

#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_PCI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_PCI_EHCI_DEVICE			0
#endif

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_IPADDR	192.168.1.251

#define CONFIG_HOSTNAME	8544ds_unknown
#define CONFIG_ROOTPATH	"/nfs/mpc85xx"
#define CONFIG_BOOTFILE	"8544ds/uImage.uboot"
#define CONFIG_UBOOTPATH	8544ds/u-boot.bin	/* TFTP server */

#define CONFIG_SERVERIP	192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK	255.255.0.0

#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/

#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/

#define	CONFIG_EXTRA_ENV_SETTINGS				\
"netdev=eth0\0"						\
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
"tftpflash=tftpboot $loadaddr $uboot; "			\
	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
		" +$filesize; "	\
	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
		" +$filesize; "	\
	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
		" $filesize; "	\
	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
		" +$filesize; "	\
	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
		" $filesize\0"	\
"consoledev=ttyS0\0"				\
"ramdiskaddr=2000000\0"			\
"ramdiskfile=8544ds/ramdisk.uboot\0"		\
"fdtaddr=1e00000\0"				\
"fdtfile=8544ds/mpc8544ds.dtb\0"		\
"bdev=sda3\0"

#define CONFIG_NFSBOOTCOMMAND		\
 "setenv bootargs root=/dev/nfs rw "	\
 "nfsroot=$serverip:$rootpath "		\
 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND		\
 "setenv bootargs root=/dev/ram rw "	\
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $ramdiskaddr $ramdiskfile;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND		\
 "setenv bootargs root=/dev/$bdev rw "	\
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr - $fdtaddr"

#endif	/* __CONFIG_H */
Commit	Line	Data
0cde4b00	1	/*
7c57f3e8	2	* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
0cde4b00	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
0cde4b00 JL	5	*/
	6
	7	/*
	8	* mpc8544ds board configuration file
	9	*
	10	*/
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
2ae18241 WD	14	#ifndef CONFIG_SYS_TEXT_BASE
	15	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	16	#endif
	17
837f1ba0	18	#define CONFIG_PCI1 1 /* PCI controller 1 */
b38eaec5 RD	19	#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
	20	#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
	21	#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
837f1ba0	22	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
842033e6	23	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
8ff3de61	24	#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
0151cbac	25	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
837f1ba0 ES	26
837f1ba0 ES	27	#define CONFIG_TSEC_ENET /* tsec ethernet support */
0cde4b00	28	#define CONFIG_ENV_OVERWRITE
837f1ba0	29	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
0cde4b00	30
0cde4b00 JL	31	#ifndef __ASSEMBLY__
	32	extern unsigned long get_board_sys_clk(unsigned long dummy);
	33	#endif
	34	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
	35
	36	/*
	37	* These can be toggled for performance analysis, otherwise use default.
	38	*/
837f1ba0	39	#define CONFIG_L2_CACHE /* toggle L2 cache */
0cde4b00	40	#define CONFIG_BTB /* toggle branch predition */
0cde4b00 JL	41
	42	/*
	43	* Only possible on E500 Version 2 or newer cores.
	44	*/
	45	#define CONFIG_ENABLE_36BIT_PHYS 1
	46
6d0f6bcf JCPV	47	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
6d0f6bcf JCPV	48	#define CONFIG_SYS_MEMTEST_END 0x00400000
837f1ba0	49	#define CONFIG_PANIC_HANG /* do not reset board on panic */
0cde4b00	50
e46fedfe TT	51	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	52	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
0cde4b00	53
1167a2fd	54	/* DDR Setup */
1167a2fd KG	55	#undef CONFIG_FSL_DDR_INTERACTIVE
	56	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	57	#define CONFIG_DDR_SPD
	58
9b0ad1b1	59	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
1167a2fd KG	60	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
1167a2fd KG	61
6d0f6bcf JCPV	62	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	63	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
1167a2fd KG	64	#define CONFIG_VERY_BIG_RAM
1167a2fd KG	65
1167a2fd KG	66	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
1167a2fd KG	67	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
0cde4b00	68
1167a2fd	69	/* I2C addresses of SPD EEPROMs */
0cde4b00 JL	70	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
0cde4b00 JL	71
1167a2fd	72	/* Make sure required options are set */
0cde4b00 JL	73	#ifndef CONFIG_SPD_EEPROM
	74	#error ("CONFIG_SPD_EEPROM is required")
	75	#endif
	76
	77	#undef CONFIG_CLOCKS_IN_MHZ
	78
	79	/*
	80	* Memory map
	81	*
	82	* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	83	*
	84	* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
	85	*
	86	* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
	87	*
	88	* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
	89	* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
	90	*
	91	* Localbus cacheable
	92	*
	93	* 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
	94	* 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
	95	*
	96	* Localbus non-cacheable
	97	*
	98	* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
	99	* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
	100	* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
	101	*
	102	*/
	103
	104	/*
	105	* Local Bus Definitions
	106	*/
6d0f6bcf	107	#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
0cde4b00	108
6d0f6bcf	109	#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
0cde4b00	110
6d0f6bcf JCPV	111	#define CONFIG_SYS_BR0_PRELIM 0xff801001
6d0f6bcf JCPV	112	#define CONFIG_SYS_BR1_PRELIM 0xfe801001
0cde4b00	113
6d0f6bcf JCPV	114	#define CONFIG_SYS_OR0_PRELIM 0xff806e65
6d0f6bcf JCPV	115	#define CONFIG_SYS_OR1_PRELIM 0xff806e65
0cde4b00	116
6d0f6bcf	117	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
0cde4b00	118
6d0f6bcf JCPV	119	#define CONFIG_SYS_FLASH_QUIET_TEST
	120	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	121	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
	122	#undef CONFIG_SYS_FLASH_CHECKSUM
	123	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	124	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
81e56e9a	125	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
0cde4b00	126
14d0a02a	127	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
0cde4b00	128
00b1883a	129	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	130	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	131	#define CONFIG_SYS_FLASH_EMPTY_INFO
0cde4b00	132
6d0f6bcf	133	#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
0cde4b00	134
6d0f6bcf JCPV	135	#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
6d0f6bcf JCPV	136	#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
0cde4b00	137
6d0f6bcf JCPV	138	#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
6d0f6bcf JCPV	139	#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
0cde4b00	140
7608d75f	141	#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
0cde4b00 JL	142	#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
	143	#define PIXIS_ID 0x0 /* Board ID at offset 0 */
	144	#define PIXIS_VER 0x1 /* Board version at offset 1 */
	145	#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
	146	#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
	147	#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
	148	* register */
	149	#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
	150	#define PIXIS_VCTL 0x10 /* VELA Control Register */
	151	#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
	152	#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
	153	#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
6bb5b412 KG	154	#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
6bb5b412 KG	155	#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
0cde4b00 JL	156	#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
	157	#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
	158	#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
	159	#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
5a8a163a	160	#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
6d0f6bcf	161	#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
5a8a163a AF	162	#define PIXIS_VSPEED2_TSEC1SER 0x2
	163	#define PIXIS_VSPEED2_TSEC3SER 0x1
	164	#define PIXIS_VCFGEN1_TSEC1SER 0x20
	165	#define PIXIS_VCFGEN1_TSEC3SER 0x40
bff188ba LY	166	#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER\|PIXIS_VSPEED2_TSEC3SER)
bff188ba LY	167	#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER\|PIXIS_VCFGEN1_TSEC3SER)
0cde4b00	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	170	#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
553f0982	171	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
1107014e	172
25ddd1fb	173	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	174	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0cde4b00	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	177	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
0cde4b00 JL	178
	179	/* Serial Port - controlled on board with jumper J8
	180	* open - index 2
	181	* shorted - index 1
	182	*/
	183	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	184	#define CONFIG_SYS_NS16550_SERIAL
	185	#define CONFIG_SYS_NS16550_REG_SIZE 1
	186	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
0cde4b00	187
6d0f6bcf	188	#define CONFIG_SYS_BAUDRATE_TABLE \
0cde4b00 JL	189	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
0cde4b00 JL	190
6d0f6bcf JCPV	191	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	192	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
0cde4b00	193
0cde4b00	194	/* I2C */
00f792e0 HS	195	#define CONFIG_SYS_I2C
	196	#define CONFIG_SYS_I2C_FSL
	197	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	198	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
7f25fdc7	199	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
00f792e0	200	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
6d0f6bcf	201	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
0cde4b00 JL	202
	203	/*
	204	* General PCI
	205	* Memory space is mapped 1-1, but I/O space must start from 0.
	206	*/
5af0fdd8	207	#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
6d0f6bcf	208	#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
5af0fdd8	209	#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
6d0f6bcf	210	#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
0cde4b00	211
5af0fdd8	212	#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
10795f42	213	#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
5af0fdd8	214	#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
6d0f6bcf	215	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	216	#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
5f91ef6a	217	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	218	#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
6d0f6bcf JCPV	219	#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
0cde4b00	220
0cde4b00	221	/* controller 2, Slot 1, tgtid 1, Base address 9000 */
64a1686a	222	#define CONFIG_SYS_PCIE2_NAME "Slot 1"
5af0fdd8	223	#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
10795f42	224	#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
5af0fdd8	225	#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
6d0f6bcf	226	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
aca5f018	227	#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
5f91ef6a	228	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
6d0f6bcf JCPV	229	#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
6d0f6bcf JCPV	230	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
0cde4b00 JL	231
0cde4b00 JL	232	/* controller 1, Slot 2,tgtid 2, Base address a000 */
64a1686a	233	#define CONFIG_SYS_PCIE1_NAME "Slot 2"
5af0fdd8	234	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
10795f42	235	#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
5af0fdd8	236	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
6d0f6bcf	237	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
aca5f018	238	#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
5f91ef6a	239	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
6d0f6bcf JCPV	240	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
6d0f6bcf JCPV	241	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
0cde4b00 JL	242
0cde4b00 JL	243	/* controller 3, direct to uli, tgtid 3, Base address b000 */
64a1686a	244	#define CONFIG_SYS_PCIE3_NAME "ULI"
5af0fdd8	245	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
10795f42	246	#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
5af0fdd8	247	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
6d0f6bcf	248	#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
aca5f018	249	#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
5f91ef6a	250	#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
6d0f6bcf JCPV	251	#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
6d0f6bcf JCPV	252	#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
5af0fdd8	253	#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
10795f42	254	#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
5af0fdd8	255	#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
6d0f6bcf	256	#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
0cde4b00 JL	257
	258	#if defined(CONFIG_PCI)
	259
630d9bfc	260	/PCIE video card used/
aca5f018	261	#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
630d9bfc KG	262
630d9bfc KG	263	/PCI video card used/
aca5f018	264	/#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT/
630d9bfc KG	265
630d9bfc KG	266	/* video */
630d9bfc KG	267
	268	#if defined(CONFIG_VIDEO)
	269	#define CONFIG_BIOSEMU
630d9bfc KG	270	#define CONFIG_ATI_RADEON_FB
630d9bfc KG	271	#define CONFIG_VIDEO_LOGO
6d0f6bcf	272	#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
630d9bfc KG	273	#endif
630d9bfc KG	274
0cde4b00 JL	275	#undef CONFIG_EEPRO100
0cde4b00 JL	276	#undef CONFIG_TULIP
0cde4b00	277
0cde4b00	278	#ifndef CONFIG_PCI_PNP
5f91ef6a KG	279	#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
5f91ef6a KG	280	#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
0cde4b00 JL	281	#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
	282	#endif
	283
	284	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
0cde4b00 JL	285	#define CONFIG_SCSI_AHCI
	286
	287	#ifdef CONFIG_SCSI_AHCI
344ca0b4	288	#define CONFIG_LIBATA
0cde4b00	289	#define CONFIG_SATA_ULI5288
6d0f6bcf JCPV	290	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
	291	#define CONFIG_SYS_SCSI_MAX_LUN 1
	292	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
	293	#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
0cde4b00 JL	294	#endif /* SCSCI */
	295
	296	#endif /* CONFIG_PCI */
	297
0cde4b00 JL	298	#if defined(CONFIG_TSEC_ENET)
0cde4b00 JL	299
0cde4b00 JL	300	#define CONFIG_MII 1 /* MII PHY management */
0cde4b00 JL	301	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
255a3577 KP	302	#define CONFIG_TSEC1 1
	303	#define CONFIG_TSEC1_NAME "eTSEC1"
	304	#define CONFIG_TSEC3 1
	305	#define CONFIG_TSEC3_NAME "eTSEC3"
837f1ba0	306
bff188ba	307	#define CONFIG_PIXIS_SGMII_CMD
652f7c2e AF	308	#define CONFIG_FSL_SGMII_RISER 1
	309	#define SGMII_RISER_PHY_OFFSET 0x1c
	310
0cde4b00 JL	311	#define TSEC1_PHY_ADDR 0
	312	#define TSEC3_PHY_ADDR 1
	313
3a79013e AF	314	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	315	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	316
0cde4b00 JL	317	#define TSEC1_PHYIDX 0
	318	#define TSEC3_PHYIDX 0
	319
	320	#define CONFIG_ETHPRIME "eTSEC1"
	321
	322	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
0cde4b00 JL	323	#endif /* CONFIG_TSEC_ENET */
	324
	325	/*
	326	* Environment
	327	*/
109f5a21	328	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
6d0f6bcf	329	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
0e8d1586	330	#define CONFIG_ENV_ADDR 0xfff80000
0cde4b00	331	#else
109f5a21	332	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
0cde4b00	333	#endif
0e8d1586	334	#define CONFIG_ENV_SIZE 0x2000
0cde4b00 JL	335
0cde4b00 JL	336	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	337	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
0cde4b00	338
659e2f67 JL	339	/*
	340	* BOOTP options
	341	*/
	342	#define CONFIG_BOOTP_BOOTFILESIZE
	343	#define CONFIG_BOOTP_BOOTPATH
	344	#define CONFIG_BOOTP_GATEWAY
	345	#define CONFIG_BOOTP_HOSTNAME
	346
2835e518 JL	347	/*
	348	* Command line configuration.
	349	*/
199e262e	350	#define CONFIG_CMD_REGINFO
2835e518	351
0cde4b00	352	#if defined(CONFIG_PCI)
2835e518	353	#define CONFIG_CMD_PCI
0cde4b00	354	#endif
2835e518	355
86a194b7 HJ	356	/*
	357	* USB
	358	*/
86a194b7	359
8850c5d5	360	#ifdef CONFIG_USB_EHCI_HCD
86a194b7 HJ	361	#define CONFIG_USB_EHCI_PCI
86a194b7 HJ	362	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
86a194b7 HJ	363	#define CONFIG_PCI_EHCI_DEVICE 0
86a194b7 HJ	364	#endif
0cde4b00 JL	365
	366	#undef CONFIG_WATCHDOG /* watchdog disabled */
	367
	368	/*
	369	* Miscellaneous configurable options
	370	*/
6d0f6bcf	371	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5be58f5f KP	372	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f KP	373	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf	374	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
2835e518	375	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	376	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0cde4b00	377	#else
6d0f6bcf	378	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0cde4b00	379	#endif
6d0f6bcf JCPV	380	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	381	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	382	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0cde4b00 JL	383
	384	/*
	385	* For booting Linux, the board info and command line data
a832ac41	386	* have to be in the first 64 MB of memory, since this is
0cde4b00 JL	387	* the maximum mapped by the Linux kernel during initialization.
0cde4b00 JL	388	*/
a832ac41 KG	389	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	390	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
0cde4b00	391
2835e518	392	#if defined(CONFIG_CMD_KGDB)
0cde4b00	393	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
0cde4b00 JL	394	#endif
	395
	396	/*
	397	* Environment Configuration
	398	*/
	399
	400	/* The mac addresses for all ethernet interface */
	401	#if defined(CONFIG_TSEC_ENET)
ea5877e3	402	#define CONFIG_HAS_ETH0
0cde4b00	403	#define CONFIG_HAS_ETH1
0cde4b00 JL	404	#endif
	405
	406	#define CONFIG_IPADDR 192.168.1.251
	407
	408	#define CONFIG_HOSTNAME 8544ds_unknown
8b3637c6	409	#define CONFIG_ROOTPATH "/nfs/mpc85xx"
b3f44c21	410	#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
837f1ba0	411	#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
0cde4b00	412
50c03c8c KG	413	#define CONFIG_SERVERIP 192.168.1.1
50c03c8c KG	414	#define CONFIG_GATEWAYIP 192.168.1.1
0cde4b00 JL	415	#define CONFIG_NETMASK 255.255.0.0
	416
	417	#define CONFIG_LOADADDR 1000000 /default location for tftp and bootm/
	418
837f1ba0	419	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
0cde4b00	420
837f1ba0	421	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d MV	422	"netdev=eth0\0" \
	423	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	424	"tftpflash=tftpboot $loadaddr $uboot; " \
	425	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	426	" +$filesize; " \
	427	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	428	" +$filesize; " \
	429	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	430	" $filesize; " \
	431	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	432	" +$filesize; " \
	433	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	434	" $filesize\0" \
	435	"consoledev=ttyS0\0" \
	436	"ramdiskaddr=2000000\0" \
	437	"ramdiskfile=8544ds/ramdisk.uboot\0" \
b24a4f62	438	"fdtaddr=1e00000\0" \
5368c55d MV	439	"fdtfile=8544ds/mpc8544ds.dtb\0" \
5368c55d MV	440	"bdev=sda3\0"
0cde4b00 JL	441
	442	#define CONFIG_NFSBOOTCOMMAND \
	443	"setenv bootargs root=/dev/nfs rw " \
	444	"nfsroot=$serverip:$rootpath " \
	445	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	446	"console=$consoledev,$baudrate $othbootargs;" \
	447	"tftp $loadaddr $bootfile;" \
50c03c8c KG	448	"tftp $fdtaddr $fdtfile;" \
50c03c8c KG	449	"bootm $loadaddr - $fdtaddr"
0cde4b00	450
837f1ba0	451	#define CONFIG_RAMBOOTCOMMAND \
0cde4b00 JL	452	"setenv bootargs root=/dev/ram rw " \
	453	"console=$consoledev,$baudrate $othbootargs;" \
	454	"tftp $ramdiskaddr $ramdiskfile;" \
	455	"tftp $loadaddr $bootfile;" \
50c03c8c KG	456	"tftp $fdtaddr $fdtfile;" \
50c03c8c KG	457	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0cde4b00	458
837f1ba0 ES	459	#define CONFIG_BOOTCOMMAND \
837f1ba0 ES	460	"setenv bootargs root=/dev/$bdev rw " \
0cde4b00 JL	461	"console=$consoledev,$baudrate $othbootargs;" \
0cde4b00 JL	462	"tftp $loadaddr $bootfile;" \
50c03c8c KG	463	"tftp $fdtaddr $fdtfile;" \
50c03c8c KG	464	"bootm $loadaddr - $fdtaddr"
0cde4b00 JL	465
0cde4b00 JL	466	#endif /* __CONFIG_H */