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| Commit | Line | Data |
|---|---|---|
| 129ba616 KG |
1 | /* |
| 2 | * Copyright 2007-2008 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | /* | |
| 24 | * mpc8572ds board configuration file | |
| 25 | * | |
| 26 | */ | |
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| f9edcc10 KG |
30 | #ifdef CONFIG_MK_36BIT |
| 31 | #define CONFIG_PHYS_64BIT | |
| 32 | #endif | |
| 33 | ||
| 129ba616 KG |
34 | /* High Level Configuration Options */ |
| 35 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
| 36 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 37 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
| 38 | #define CONFIG_MPC8572 1 | |
| 39 | #define CONFIG_MPC8572DS 1 | |
| 40 | #define CONFIG_MP 1 /* support multiple processors */ | |
| 129ba616 | 41 | |
| c51fc5d5 | 42 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
| 129ba616 KG |
43 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 44 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
| 45 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
| 46 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
| 47 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 48 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
| 0151cbac | 49 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 129ba616 KG |
50 | |
| 51 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
| 52 | ||
| 53 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 54 | #define CONFIG_ENV_OVERWRITE | |
| 55 | ||
| 129ba616 KG |
56 | #ifndef __ASSEMBLY__ |
| 57 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 58 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
| 59 | #endif | |
| 60 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
| 61 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ | |
| 4ca06607 | 62 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
| 129ba616 KG |
63 | #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq |
| 64 | from ICS307 instead of switches */ | |
| 65 | ||
| 66 | /* | |
| 67 | * These can be toggled for performance analysis, otherwise use default. | |
| 68 | */ | |
| 69 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 70 | #define CONFIG_BTB /* toggle branch predition */ | |
| 129ba616 KG |
71 | |
| 72 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 73 | ||
| 18af1c5f KG |
74 | #ifdef CONFIG_PHYS_64BIT |
| 75 | #define CONFIG_ADDR_MAP 1 | |
| 76 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 77 | #endif | |
| 78 | ||
| 6d0f6bcf JCPV |
79 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| 80 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
| 129ba616 KG |
81 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 82 | ||
| 83 | /* | |
| 84 | * Base addresses -- Note these are effective addresses where the | |
| 85 | * actual resources get mapped (not physical addresses) | |
| 86 | */ | |
| 6d0f6bcf JCPV |
87 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 88 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ | |
| 18af1c5f KG |
89 | #ifdef CONFIG_PHYS_64BIT |
| 90 | #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ | |
| 91 | #else | |
| 6d0f6bcf | 92 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
| 18af1c5f | 93 | #endif |
| 6d0f6bcf | 94 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
| 129ba616 | 95 | |
| 6d0f6bcf JCPV |
96 | #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
| 97 | #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) | |
| 98 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) | |
| 129ba616 KG |
99 | |
| 100 | /* DDR Setup */ | |
| b5f65dfa | 101 | #define CONFIG_SYS_DDR_TLB_START 9 |
| f8523cb0 | 102 | #define CONFIG_VERY_BIG_RAM |
| 129ba616 KG |
103 | #define CONFIG_FSL_DDR2 |
| 104 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 105 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 106 | #define CONFIG_DDR_SPD | |
| 107 | #undef CONFIG_DDR_DLL | |
| 108 | ||
| 9b0ad1b1 | 109 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 129ba616 KG |
110 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 111 | ||
| 6d0f6bcf JCPV |
112 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 113 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 129ba616 KG |
114 | |
| 115 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 116 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 117 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
| 118 | ||
| 119 | /* I2C addresses of SPD EEPROMs */ | |
| 6d0f6bcf | 120 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ |
| 129ba616 KG |
121 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
| 122 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ | |
| 123 | ||
| 124 | /* These are used when DDR doesn't use SPD. */ | |
| dc889e86 DL |
125 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
| 126 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F | |
| 127 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ | |
| 128 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
| 129 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
| 130 | #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 | |
| 131 | #define CONFIG_SYS_DDR_TIMING_2 0x062874cf | |
| 132 | #define CONFIG_SYS_DDR_MODE_1 0x00440462 | |
| 6d0f6bcf | 133 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| dc889e86 | 134 | #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 |
| 6d0f6bcf | 135 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| dc889e86 DL |
136 | #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 |
| 137 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 6d0f6bcf | 138 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| dc889e86 DL |
139 | #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ |
| 140 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
| 6d0f6bcf JCPV |
141 | |
| 142 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
| 143 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
| 144 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
| 129ba616 | 145 | |
| 129ba616 KG |
146 | /* |
| 147 | * Make sure required options are set | |
| 148 | */ | |
| 149 | #ifndef CONFIG_SPD_EEPROM | |
| 150 | #error ("CONFIG_SPD_EEPROM is required") | |
| 151 | #endif | |
| 152 | ||
| 153 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 154 | ||
| 155 | /* | |
| 156 | * Memory map | |
| 157 | * | |
| 158 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 159 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
| 160 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
| 161 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
| 162 | * | |
| 163 | * Localbus cacheable (TBD) | |
| 164 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
| 165 | * | |
| 166 | * Localbus non-cacheable | |
| 167 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
| 168 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
| 3cbd8231 | 169 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
| 129ba616 KG |
170 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 171 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 172 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 173 | */ | |
| 174 | ||
| 175 | /* | |
| 176 | * Local Bus Definitions | |
| 177 | */ | |
| 6d0f6bcf | 178 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
| 18af1c5f KG |
179 | #ifdef CONFIG_PHYS_64BIT |
| 180 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
| 181 | #else | |
| c953ddfd | 182 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 18af1c5f | 183 | #endif |
| 129ba616 | 184 | |
| c953ddfd KG |
185 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) |
| 186 | #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 | |
| 129ba616 | 187 | |
| c953ddfd KG |
188 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| 189 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
| 129ba616 | 190 | |
| 18af1c5f | 191 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
| 6d0f6bcf | 192 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 129ba616 KG |
193 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 194 | ||
| 6d0f6bcf JCPV |
195 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 196 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 197 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 198 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 199 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 129ba616 | 200 | |
| 6d0f6bcf | 201 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 129ba616 KG |
202 | |
| 203 | #define CONFIG_FLASH_CFI_DRIVER | |
| 6d0f6bcf JCPV |
204 | #define CONFIG_SYS_FLASH_CFI |
| 205 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 206 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
| 129ba616 KG |
207 | |
| 208 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 209 | ||
| 210 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ | |
| 211 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
| 18af1c5f KG |
212 | #ifdef CONFIG_PHYS_64BIT |
| 213 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
| 214 | #else | |
| 52b565f5 | 215 | #define PIXIS_BASE_PHYS PIXIS_BASE |
| 18af1c5f | 216 | #endif |
| 129ba616 | 217 | |
| 52b565f5 | 218 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| 6d0f6bcf | 219 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
| 129ba616 KG |
220 | |
| 221 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
| 222 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 223 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 224 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
| 225 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 226 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
| 227 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
| 228 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 229 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
| 230 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 231 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
| 232 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 233 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 234 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
| 235 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 6bb5b412 KG |
236 | #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ |
| 237 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ | |
| 238 | #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ | |
| 239 | #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ | |
| 240 | #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ | |
| 129ba616 KG |
241 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 242 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 243 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
| 244 | #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ | |
| 245 | #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ | |
| 246 | #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ | |
| 247 | #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ | |
| 248 | #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ | |
| 249 | #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ | |
| 250 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
| 251 | #define PIXIS_LED 0x25 /* LED Register */ | |
| 252 | ||
| 253 | /* old pixis referenced names */ | |
| 254 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 255 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 6d0f6bcf | 256 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
| 7e183cad LY |
257 | #define PIXIS_VSPEED2_TSEC1SER 0x8 |
| 258 | #define PIXIS_VSPEED2_TSEC2SER 0x4 | |
| 259 | #define PIXIS_VSPEED2_TSEC3SER 0x2 | |
| 260 | #define PIXIS_VSPEED2_TSEC4SER 0x1 | |
| 261 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
| 262 | #define PIXIS_VCFGEN1_TSEC2SER 0x20 | |
| 263 | #define PIXIS_VCFGEN1_TSEC3SER 0x20 | |
| 264 | #define PIXIS_VCFGEN1_TSEC4SER 0x20 | |
| 265 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ | |
| 266 | | PIXIS_VSPEED2_TSEC2SER \ | |
| 267 | | PIXIS_VSPEED2_TSEC3SER \ | |
| 268 | | PIXIS_VSPEED2_TSEC4SER) | |
| 269 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ | |
| 270 | | PIXIS_VCFGEN1_TSEC2SER \ | |
| 271 | | PIXIS_VCFGEN1_TSEC3SER \ | |
| 272 | | PIXIS_VCFGEN1_TSEC4SER) | |
| 129ba616 | 273 | |
| 6d0f6bcf JCPV |
274 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 275 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
| 276 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
| 129ba616 | 277 | |
| 6d0f6bcf JCPV |
278 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 279 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 280 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 129ba616 | 281 | |
| 6d0f6bcf JCPV |
282 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 283 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| 129ba616 | 284 | |
| c013b749 | 285 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| 18af1c5f KG |
286 | #ifdef CONFIG_PHYS_64BIT |
| 287 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
| 288 | #else | |
| c013b749 | 289 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 18af1c5f | 290 | #endif |
| c013b749 HW |
291 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 292 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
| 293 | CONFIG_SYS_NAND_BASE + 0x80000,\ | |
| 294 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
| 295 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
| c013b749 | 296 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 3cbd8231 WD |
297 | #define CONFIG_CMD_NAND 1 |
| 298 | #define CONFIG_NAND_FSL_ELBC 1 | |
| c013b749 HW |
299 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 300 | ||
| 301 | /* NAND flash config */ | |
| 72a9414a | 302 | #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 3cbd8231 WD |
303 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 304 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 305 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 306 | | BR_V) /* valid */ | |
| 307 | #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
| 308 | | OR_FCM_PGS /* Large Page*/ \ | |
| 309 | | OR_FCM_CSCT \ | |
| 310 | | OR_FCM_CST \ | |
| 311 | | OR_FCM_CHT \ | |
| 312 | | OR_FCM_SCY_1 \ | |
| 313 | | OR_FCM_TRLX \ | |
| 314 | | OR_FCM_EHTR) | |
| c013b749 HW |
315 | |
| 316 | #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ | |
| 317 | #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 318 | ||
| 72a9414a | 319 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ |
| 3cbd8231 WD |
320 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 321 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 322 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 323 | | BR_V) /* valid */ | |
| 324 | #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 72a9414a | 325 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ |
| 3cbd8231 WD |
326 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 327 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 328 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 329 | | BR_V) /* valid */ | |
| 330 | #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| c013b749 | 331 | |
| 72a9414a | 332 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ |
| 3cbd8231 WD |
333 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 334 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 335 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 336 | | BR_V) /* valid */ | |
| 337 | #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| c013b749 HW |
338 | |
| 339 | ||
| 129ba616 KG |
340 | /* Serial Port - controlled on board with jumper J8 |
| 341 | * open - index 2 | |
| 342 | * shorted - index 1 | |
| 343 | */ | |
| 344 | #define CONFIG_CONS_INDEX 1 | |
| 345 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 6d0f6bcf JCPV |
346 | #define CONFIG_SYS_NS16550 |
| 347 | #define CONFIG_SYS_NS16550_SERIAL | |
| 348 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 349 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 129ba616 | 350 | |
| 6d0f6bcf | 351 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 129ba616 KG |
352 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 353 | ||
| 6d0f6bcf JCPV |
354 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 355 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 129ba616 KG |
356 | |
| 357 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
358 | #define CONFIG_SYS_HUSH_PARSER |
| 359 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 360 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 129ba616 KG |
361 | #endif |
| 362 | ||
| 363 | /* | |
| 364 | * Pass open firmware flat tree | |
| 365 | */ | |
| 366 | #define CONFIG_OF_LIBFDT 1 | |
| 367 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 368 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 369 | ||
| 129ba616 KG |
370 | /* new uImage format support */ |
| 371 | #define CONFIG_FIT 1 | |
| 372 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
| 373 | ||
| 374 | /* I2C */ | |
| 375 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 376 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 377 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 1f3ba317 | 378 | #define CONFIG_I2C_MULTI_BUS |
| 6d0f6bcf JCPV |
379 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 380 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 381 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 382 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ | |
| 383 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 384 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 129ba616 | 385 | |
| 445a7b38 HW |
386 | /* |
| 387 | * I2C2 EEPROM | |
| 388 | */ | |
| 389 | #define CONFIG_ID_EEPROM | |
| 390 | #ifdef CONFIG_ID_EEPROM | |
| 6d0f6bcf | 391 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 445a7b38 | 392 | #endif |
| 6d0f6bcf JCPV |
393 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 394 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 395 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
| 445a7b38 | 396 | |
| 129ba616 KG |
397 | /* |
| 398 | * General PCI | |
| 399 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 400 | */ | |
| 401 | ||
| 129ba616 | 402 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
| 5af0fdd8 | 403 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
| 18af1c5f | 404 | #ifdef CONFIG_PHYS_64BIT |
| 156984a3 | 405 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| 18af1c5f KG |
406 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
| 407 | #else | |
| ad97dce1 | 408 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
| 5af0fdd8 | 409 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
| 18af1c5f | 410 | #endif |
| 6d0f6bcf | 411 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 412 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
| 5f91ef6a | 413 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 18af1c5f KG |
414 | #ifdef CONFIG_PHYS_64BIT |
| 415 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull | |
| 416 | #else | |
| 6d0f6bcf | 417 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
| 18af1c5f | 418 | #endif |
| 6d0f6bcf | 419 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 129ba616 KG |
420 | |
| 421 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
| 5af0fdd8 | 422 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 18af1c5f | 423 | #ifdef CONFIG_PHYS_64BIT |
| 156984a3 | 424 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| 18af1c5f KG |
425 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 426 | #else | |
| ad97dce1 | 427 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| 5af0fdd8 | 428 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| 18af1c5f | 429 | #endif |
| 6d0f6bcf | 430 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 431 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| 5f91ef6a | 432 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 18af1c5f KG |
433 | #ifdef CONFIG_PHYS_64BIT |
| 434 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
| 435 | #else | |
| 6d0f6bcf | 436 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| 18af1c5f | 437 | #endif |
| 6d0f6bcf | 438 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 129ba616 KG |
439 | |
| 440 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 5af0fdd8 | 441 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
| 18af1c5f | 442 | #ifdef CONFIG_PHYS_64BIT |
| 156984a3 | 443 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 18af1c5f KG |
444 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
| 445 | #else | |
| ad97dce1 | 446 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
| 5af0fdd8 | 447 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
| 18af1c5f | 448 | #endif |
| 6d0f6bcf | 449 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 450 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
| 5f91ef6a | 451 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 18af1c5f KG |
452 | #ifdef CONFIG_PHYS_64BIT |
| 453 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull | |
| 454 | #else | |
| 6d0f6bcf | 455 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
| 18af1c5f | 456 | #endif |
| 6d0f6bcf | 457 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 129ba616 KG |
458 | |
| 459 | #if defined(CONFIG_PCI) | |
| 460 | ||
| 461 | /*PCIE video card used*/ | |
| aca5f018 | 462 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
| 129ba616 KG |
463 | |
| 464 | /* video */ | |
| 465 | #define CONFIG_VIDEO | |
| 466 | ||
| 467 | #if defined(CONFIG_VIDEO) | |
| 468 | #define CONFIG_BIOSEMU | |
| 469 | #define CONFIG_CFB_CONSOLE | |
| 470 | #define CONFIG_VIDEO_SW_CURSOR | |
| 471 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 472 | #define CONFIG_ATI_RADEON_FB | |
| 473 | #define CONFIG_VIDEO_LOGO | |
| 474 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
| 6d0f6bcf | 475 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| 129ba616 KG |
476 | #endif |
| 477 | ||
| 478 | #define CONFIG_NET_MULTI | |
| 479 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 480 | ||
| 481 | #undef CONFIG_EEPRO100 | |
| 482 | #undef CONFIG_TULIP | |
| 483 | #undef CONFIG_RTL8139 | |
| 484 | ||
| 129ba616 | 485 | #ifndef CONFIG_PCI_PNP |
| 5f91ef6a KG |
486 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
| 487 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS | |
| 129ba616 KG |
488 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 489 | #endif | |
| 490 | ||
| 491 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 492 | #define CONFIG_DOS_PARTITION | |
| 493 | #define CONFIG_SCSI_AHCI | |
| 494 | ||
| 495 | #ifdef CONFIG_SCSI_AHCI | |
| 496 | #define CONFIG_SATA_ULI5288 | |
| 6d0f6bcf JCPV |
497 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 498 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 499 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
| 500 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
| 129ba616 KG |
501 | #endif /* SCSI */ |
| 502 | ||
| 503 | #endif /* CONFIG_PCI */ | |
| 504 | ||
| 505 | ||
| 506 | #if defined(CONFIG_TSEC_ENET) | |
| 507 | ||
| 508 | #ifndef CONFIG_NET_MULTI | |
| 509 | #define CONFIG_NET_MULTI 1 | |
| 510 | #endif | |
| 511 | ||
| 512 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 513 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 514 | #define CONFIG_TSEC1 1 | |
| 515 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 516 | #define CONFIG_TSEC2 1 | |
| 517 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 518 | #define CONFIG_TSEC3 1 | |
| 519 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 520 | #define CONFIG_TSEC4 1 | |
| 521 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| 522 | ||
| 7e183cad LY |
523 | #define CONFIG_PIXIS_SGMII_CMD |
| 524 | #define CONFIG_FSL_SGMII_RISER 1 | |
| 525 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
| 526 | ||
| 527 | #ifdef CONFIG_FSL_SGMII_RISER | |
| 528 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ | |
| 529 | #endif | |
| 530 | ||
| 129ba616 KG |
531 | #define TSEC1_PHY_ADDR 0 |
| 532 | #define TSEC2_PHY_ADDR 1 | |
| 533 | #define TSEC3_PHY_ADDR 2 | |
| 534 | #define TSEC4_PHY_ADDR 3 | |
| 535 | ||
| 536 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 537 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 538 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 539 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 540 | ||
| 541 | #define TSEC1_PHYIDX 0 | |
| 542 | #define TSEC2_PHYIDX 0 | |
| 543 | #define TSEC3_PHYIDX 0 | |
| 544 | #define TSEC4_PHYIDX 0 | |
| 545 | ||
| 546 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 547 | ||
| 548 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 549 | #endif /* CONFIG_TSEC_ENET */ | |
| 550 | ||
| 551 | /* | |
| 552 | * Environment | |
| 553 | */ | |
| 5a1aceb0 | 554 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 555 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
| 0e8d1586 | 556 | #define CONFIG_ENV_ADDR 0xfff80000 |
| 129ba616 | 557 | #else |
| 6fc110bd | 558 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 129ba616 | 559 | #endif |
| 0e8d1586 JCPV |
560 | #define CONFIG_ENV_SIZE 0x2000 |
| 561 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 129ba616 KG |
562 | |
| 563 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 564 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 129ba616 KG |
565 | |
| 566 | /* | |
| 567 | * Command line configuration. | |
| 568 | */ | |
| 569 | #include <config_cmd_default.h> | |
| 570 | ||
| 571 | #define CONFIG_CMD_IRQ | |
| 572 | #define CONFIG_CMD_PING | |
| 573 | #define CONFIG_CMD_I2C | |
| 574 | #define CONFIG_CMD_MII | |
| 575 | #define CONFIG_CMD_ELF | |
| 1c9aa76b KG |
576 | #define CONFIG_CMD_IRQ |
| 577 | #define CONFIG_CMD_SETEXPR | |
| 129ba616 KG |
578 | |
| 579 | #if defined(CONFIG_PCI) | |
| 580 | #define CONFIG_CMD_PCI | |
| 129ba616 KG |
581 | #define CONFIG_CMD_NET |
| 582 | #define CONFIG_CMD_SCSI | |
| 583 | #define CONFIG_CMD_EXT2 | |
| 584 | #endif | |
| 585 | ||
| 586 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 587 | ||
| 588 | /* | |
| 589 | * Miscellaneous configurable options | |
| 590 | */ | |
| 6d0f6bcf | 591 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 129ba616 | 592 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 6d0f6bcf JCPV |
593 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 594 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 129ba616 | 595 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 596 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 129ba616 | 597 | #else |
| 6d0f6bcf | 598 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 129ba616 | 599 | #endif |
| 6d0f6bcf JCPV |
600 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 601 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 602 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 603 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 129ba616 KG |
604 | |
| 605 | /* | |
| 606 | * For booting Linux, the board info and command line data | |
| 89188a62 | 607 | * have to be in the first 16 MB of memory, since this is |
| 129ba616 KG |
608 | * the maximum mapped by the Linux kernel during initialization. |
| 609 | */ | |
| 89188a62 | 610 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ |
| 129ba616 KG |
611 | |
| 612 | /* | |
| 613 | * Internal Definitions | |
| 614 | * | |
| 615 | * Boot Flags | |
| 616 | */ | |
| 617 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 618 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 619 | ||
| 620 | #if defined(CONFIG_CMD_KGDB) | |
| 621 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 622 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 623 | #endif | |
| 624 | ||
| 625 | /* | |
| 626 | * Environment Configuration | |
| 627 | */ | |
| 628 | ||
| 629 | /* The mac addresses for all ethernet interface */ | |
| 630 | #if defined(CONFIG_TSEC_ENET) | |
| 631 | #define CONFIG_HAS_ETH0 | |
| 632 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
| 633 | #define CONFIG_HAS_ETH1 | |
| 634 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
| 635 | #define CONFIG_HAS_ETH2 | |
| 636 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
| 637 | #define CONFIG_HAS_ETH3 | |
| 638 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
| 639 | #endif | |
| 640 | ||
| 641 | #define CONFIG_IPADDR 192.168.1.254 | |
| 642 | ||
| 643 | #define CONFIG_HOSTNAME unknown | |
| 644 | #define CONFIG_ROOTPATH /opt/nfsroot | |
| 645 | #define CONFIG_BOOTFILE uImage | |
| 646 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
| 647 | ||
| 648 | #define CONFIG_SERVERIP 192.168.1.1 | |
| 649 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
| 650 | #define CONFIG_NETMASK 255.255.255.0 | |
| 651 | ||
| 652 | /* default location for tftp and bootm */ | |
| 653 | #define CONFIG_LOADADDR 1000000 | |
| 654 | ||
| 655 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 656 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 657 | ||
| 658 | #define CONFIG_BAUDRATE 115200 | |
| 659 | ||
| 660 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 4ca06607 | 661 | "memctl_intlv_ctl=2\0" \ |
| 129ba616 KG |
662 | "netdev=eth0\0" \ |
| 663 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 664 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 665 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 666 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 667 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
| 668 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 669 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
| 670 | "consoledev=ttyS0\0" \ | |
| 671 | "ramdiskaddr=2000000\0" \ | |
| 672 | "ramdiskfile=8572ds/ramdisk.uboot\0" \ | |
| 673 | "fdtaddr=c00000\0" \ | |
| 674 | "fdtfile=8572ds/mpc8572ds.dtb\0" \ | |
| 675 | "bdev=sda3\0" | |
| 676 | ||
| 677 | #define CONFIG_HDBOOT \ | |
| 678 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 679 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 680 | "tftp $loadaddr $bootfile;" \ | |
| 681 | "tftp $fdtaddr $fdtfile;" \ | |
| 682 | "bootm $loadaddr - $fdtaddr" | |
| 683 | ||
| 684 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 685 | "setenv bootargs root=/dev/nfs rw " \ | |
| 686 | "nfsroot=$serverip:$rootpath " \ | |
| 687 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 688 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 689 | "tftp $loadaddr $bootfile;" \ | |
| 690 | "tftp $fdtaddr $fdtfile;" \ | |
| 691 | "bootm $loadaddr - $fdtaddr" | |
| 692 | ||
| 693 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 694 | "setenv bootargs root=/dev/ram rw " \ | |
| 695 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 696 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 697 | "tftp $loadaddr $bootfile;" \ | |
| 698 | "tftp $fdtaddr $fdtfile;" \ | |
| 699 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 700 | ||
| 701 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
| 702 | ||
| 703 | #endif /* __CONFIG_H */ |