projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5c9efb36 | 1 | /* |
| 1b77ca8a | 2 | * Copyright 2006, 2010-2011 Freescale Semiconductor. |
| 5c9efb36 | 3 | * |
| debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
| 5 | * | |
| 3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| debb7354 JL |
7 | */ |
| 8 | ||
| 9 | /* | |
| 5c9efb36 | 10 | * MPC8641HPCN board configuration file |
| debb7354 JL |
11 | * |
| 12 | * Make sure you change the MAC address and other network params first, | |
| 92ac5208 | 13 | * search for CONFIG_SERVERIP, etc. in this file. |
| debb7354 JL |
14 | */ |
| 15 | ||
| 16 | #ifndef __CONFIG_H | |
| 17 | #define __CONFIG_H | |
| 18 | ||
| 19 | /* High Level Configuration Options */ | |
| 7649a590 | 20 | #define CONFIG_MP 1 /* support multiple processors */ |
| 53677ef1 | 21 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
| d591a80e | 22 | #define CONFIG_ADDR_MAP 1 /* Use addr map */ |
| debb7354 | 23 | |
| 2ae18241 WD |
24 | /* |
| 25 | * default CCSRBAR is at 0xff700000 | |
| 26 | * assume U-Boot is less than 0.5MB | |
| 27 | */ | |
| 2ae18241 | 28 | |
| debb7354 | 29 | #ifdef RUN_DIAG |
| 6bf98b13 | 30 | #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE |
| debb7354 | 31 | #endif |
| 5c9efb36 | 32 | |
| 1266df88 BB |
33 | /* |
| 34 | * virtual address to be used for temporary mappings. There | |
| 35 | * should be 128k free at this VA. | |
| 36 | */ | |
| 37 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
| 38 | ||
| 1b77ca8a KG |
39 | #define CONFIG_SYS_SRIO |
| 40 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
| af5d100e | 41 | |
| b38eaec5 RD |
42 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ |
| 43 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ | |
| 63cec581 | 44 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
| 8ba93f68 | 45 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 5c9efb36 | 46 | |
| 53677ef1 | 47 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| debb7354 | 48 | #define CONFIG_ENV_OVERWRITE |
| debb7354 | 49 | |
| 4bbfd3e2 | 50 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
| 31d82672 | 51 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
| d591a80e | 52 | #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ |
| debb7354 | 53 | |
| 53677ef1 | 54 | #define CONFIG_ALTIVEC 1 |
| debb7354 | 55 | |
| 5c9efb36 | 56 | /* |
| debb7354 JL |
57 | * L2CR setup -- make sure this is right for your board! |
| 58 | */ | |
| 6d0f6bcf | 59 | #define CONFIG_SYS_L2 |
| debb7354 JL |
60 | #define L2_INIT 0 |
| 61 | #define L2_ENABLE (L2CR_L2E) | |
| 62 | ||
| 63 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 63cec581 ES |
64 | #ifndef __ASSEMBLY__ |
| 65 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 66 | #endif | |
| 53677ef1 | 67 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
| debb7354 JL |
68 | #endif |
| 69 | ||
| 6d0f6bcf JCPV |
70 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 71 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| debb7354 | 72 | |
| 3111d32c BB |
73 | /* |
| 74 | * With the exception of PCI Memory and Rapid IO, most devices will simply | |
| 75 | * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA | |
| 76 | * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. | |
| 77 | */ | |
| 78 | #ifdef CONFIG_PHYS_64BIT | |
| 1605cc9e | 79 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f |
| 3111d32c | 80 | #else |
| 1605cc9e | 81 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 |
| 3111d32c BB |
82 | #endif |
| 83 | ||
| debb7354 JL |
84 | /* |
| 85 | * Base addresses -- Note these are effective addresses where the | |
| 86 | * actual resources get mapped (not physical addresses) | |
| 87 | */ | |
| c759a01a | 88 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
| 6d0f6bcf | 89 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
| debb7354 | 90 | |
| 3111d32c BB |
91 | /* Physical addresses */ |
| 92 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 1605cc9e BB |
93 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH |
| 94 | #define CONFIG_SYS_CCSRBAR_PHYS \ | |
| 95 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ | |
| 96 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) | |
| 3111d32c | 97 | |
| 076bff8f YS |
98 | #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ |
| 99 | ||
| debb7354 JL |
100 | /* |
| 101 | * DDR Setup | |
| 102 | */ | |
| e02eae6f | 103 | #define CONFIG_FSL_DDR_INTERACTIVE |
| 6a8e5692 KG |
104 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 105 | #define CONFIG_DDR_SPD | |
| 106 | ||
| 107 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
| 108 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 109 | ||
| 6d0f6bcf JCPV |
110 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 111 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 1266df88 | 112 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
| fcb28e76 | 113 | #define CONFIG_VERY_BIG_RAM |
| debb7354 | 114 | |
| 6a8e5692 KG |
115 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
| 116 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 117 | ||
| 118 | /* | |
| 119 | * I2C addresses of SPD EEPROMs | |
| 120 | */ | |
| 121 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
| 122 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ | |
| 123 | #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ | |
| 124 | #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ | |
| 125 | ||
| 6a8e5692 KG |
126 | /* |
| 127 | * These are used when DDR doesn't use SPD. | |
| 128 | */ | |
| 6d0f6bcf JCPV |
129 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
| 130 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
| 131 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
| 132 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
| 133 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
| 134 | #define CONFIG_SYS_DDR_TIMING_1 0x39357322 | |
| 135 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
| 136 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
| 137 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 138 | #define CONFIG_SYS_DDR_INTERVAL 0x06090100 | |
| 139 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 140 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
| 141 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 142 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
| 143 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
| 144 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 | |
| 6a8e5692 | 145 | |
| ad8f8687 | 146 | #define CONFIG_ID_EEPROM |
| 6d0f6bcf | 147 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 32628c50 | 148 | #define CONFIG_ID_EEPROM |
| 6d0f6bcf JCPV |
149 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 150 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| debb7354 | 151 | |
| c759a01a | 152 | #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ |
| 1605cc9e BB |
153 | #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE |
| 154 | #define CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 155 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ | |
| 156 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| 3111d32c | 157 | |
| b81b773e | 158 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| debb7354 | 159 | |
| 3111d32c BB |
160 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 161 | | 0x00001001) /* port size 16bit */ | |
| 162 | #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ | |
| debb7354 | 163 | |
| 3111d32c BB |
164 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ |
| 165 | | 0x00001001) /* port size 16bit */ | |
| 166 | #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ | |
| debb7354 | 167 | |
| 3111d32c BB |
168 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ |
| 169 | | 0x00000801) /* port size 8bit */ | |
| 170 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ | |
| debb7354 | 171 | |
| c759a01a BB |
172 | /* |
| 173 | * The LBC_BASE is the base of the region that contains the PIXIS and the CF. | |
| 174 | * The PIXIS and CF by themselves aren't large enough to take up the 128k | |
| 175 | * required for the smallest BAT mapping, so there's a 64k hole. | |
| 176 | */ | |
| 177 | #define CONFIG_SYS_LBC_BASE 0xffde0000 | |
| 1605cc9e | 178 | #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE |
| debb7354 | 179 | |
| 7608d75f | 180 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| c759a01a | 181 | #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) |
| 1605cc9e BB |
182 | #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) |
| 183 | #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ | |
| 184 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| c759a01a | 185 | #define PIXIS_SIZE 0x00008000 /* 32k */ |
| 5c9efb36 JL |
186 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 187 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 188 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 189 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 190 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
| 191 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 192 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 193 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 194 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 195 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 9af9c6bd KG |
196 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
| 197 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
| 5c9efb36 JL |
198 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 199 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 200 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 201 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 6d0f6bcf | 202 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
| debb7354 | 203 | |
| b5431560 | 204 | /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ |
| c759a01a | 205 | #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) |
| 3111d32c | 206 | #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) |
| b5431560 | 207 | |
| 170deacb | 208 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 6d0f6bcf | 209 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| debb7354 | 210 | |
| 6d0f6bcf JCPV |
211 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 212 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 213 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 14d0a02a | 214 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| bf9a8c34 | 215 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
| debb7354 | 216 | |
| 00b1883a | 217 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
218 | #define CONFIG_SYS_FLASH_CFI |
| 219 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| debb7354 | 220 | |
| 6d0f6bcf JCPV |
221 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 222 | #define CONFIG_SYS_RAMBOOT | |
| debb7354 | 223 | #else |
| 6d0f6bcf | 224 | #undef CONFIG_SYS_RAMBOOT |
| debb7354 JL |
225 | #endif |
| 226 | ||
| 6d0f6bcf | 227 | #if defined(CONFIG_SYS_RAMBOOT) |
| fa7db9c3 | 228 | #undef CONFIG_SPD_EEPROM |
| 6d0f6bcf | 229 | #define CONFIG_SYS_SDRAM_SIZE 256 |
| debb7354 JL |
230 | #endif |
| 231 | ||
| 232 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 233 | ||
| 6d0f6bcf JCPV |
234 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 235 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
| 236 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
| debb7354 | 237 | #else |
| 6d0f6bcf | 238 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
| debb7354 | 239 | #endif |
| 553f0982 | 240 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
| debb7354 | 241 | |
| 25ddd1fb | 242 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 243 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| debb7354 | 244 | |
| 221fbd22 | 245 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
| 6d0f6bcf | 246 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
| debb7354 JL |
247 | |
| 248 | /* Serial Port */ | |
| 249 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
250 | #define CONFIG_SYS_NS16550_SERIAL |
| 251 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 252 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| debb7354 | 253 | |
| 6d0f6bcf | 254 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| debb7354 JL |
255 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 256 | ||
| 6d0f6bcf JCPV |
257 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 258 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| debb7354 | 259 | |
| 586d1d5a JL |
260 | /* |
| 261 | * I2C | |
| 262 | */ | |
| 00f792e0 HS |
263 | #define CONFIG_SYS_I2C |
| 264 | #define CONFIG_SYS_I2C_FSL | |
| 265 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 266 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 267 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
| 268 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
| debb7354 | 269 | |
| 586d1d5a JL |
270 | /* |
| 271 | * RapidIO MMU | |
| 272 | */ | |
| 1b77ca8a | 273 | #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ |
| 3111d32c | 274 | #ifdef CONFIG_PHYS_64BIT |
| 1605cc9e BB |
275 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 |
| 276 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c | |
| 3111d32c | 277 | #else |
| 1605cc9e BB |
278 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE |
| 279 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 | |
| 3111d32c | 280 | #endif |
| 1605cc9e BB |
281 | #define CONFIG_SYS_SRIO1_MEM_PHYS \ |
| 282 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ | |
| 283 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) | |
| 1b77ca8a | 284 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ |
| debb7354 JL |
285 | |
| 286 | /* | |
| 287 | * General PCI | |
| 288 | * Addresses are mapped 1-1. | |
| 289 | */ | |
| 49f46f3b | 290 | |
| 64e55d5e | 291 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
| 46f3e385 | 292 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 3111d32c | 293 | #ifdef CONFIG_PHYS_64BIT |
| 46f3e385 | 294 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 1605cc9e BB |
295 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 |
| 296 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c | |
| 3111d32c | 297 | #else |
| 46f3e385 | 298 | #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT |
| 1605cc9e BB |
299 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT |
| 300 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 | |
| 3111d32c | 301 | #endif |
| 1605cc9e BB |
302 | #define CONFIG_SYS_PCIE1_MEM_PHYS \ |
| 303 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ | |
| 304 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) | |
| 46f3e385 KG |
305 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 306 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 307 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
| 1605cc9e BB |
308 | #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT |
| 309 | #define CONFIG_SYS_PCIE1_IO_PHYS \ | |
| 310 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ | |
| 311 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| 46f3e385 | 312 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ |
| debb7354 | 313 | |
| 4c78d4a6 BB |
314 | #ifdef CONFIG_PHYS_64BIT |
| 315 | /* | |
| 46f3e385 | 316 | * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. |
| 4c78d4a6 BB |
317 | * This will increase the amount of PCI address space available for |
| 318 | * for mapping RAM. | |
| 319 | */ | |
| 46f3e385 | 320 | #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS |
| 4c78d4a6 | 321 | #else |
| 46f3e385 KG |
322 | #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ |
| 323 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 4c78d4a6 | 324 | #endif |
| 46f3e385 KG |
325 | #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ |
| 326 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 1605cc9e BB |
327 | #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ |
| 328 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 329 | #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH | |
| 46f3e385 KG |
330 | #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ |
| 331 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 332 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
| 333 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 334 | #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ | |
| 335 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
| 1605cc9e BB |
336 | #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ |
| 337 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
| 46f3e385 KG |
338 | #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ |
| 339 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
| 340 | #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE | |
| debb7354 | 341 | |
| debb7354 JL |
342 | #if defined(CONFIG_PCI) |
| 343 | ||
| 53677ef1 | 344 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| debb7354 | 345 | |
| debb7354 JL |
346 | #undef CONFIG_EEPRO100 |
| 347 | #undef CONFIG_TULIP | |
| 348 | ||
| a81d1c0b ZW |
349 | /************************************************************ |
| 350 | * USB support | |
| 351 | ************************************************************/ | |
| 53677ef1 | 352 | #define CONFIG_PCI_OHCI 1 |
| a81d1c0b | 353 | #define CONFIG_USB_OHCI_NEW 1 |
| 6d0f6bcf JCPV |
354 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" |
| 355 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
| 356 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
| a81d1c0b | 357 | |
| 0f460a1e | 358 | /*PCIE video card used*/ |
| 46f3e385 | 359 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
| 0f460a1e JJ |
360 | |
| 361 | /*PCI video card used*/ | |
| 46f3e385 | 362 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ |
| 0f460a1e JJ |
363 | |
| 364 | /* video */ | |
| 0f460a1e JJ |
365 | |
| 366 | #if defined(CONFIG_VIDEO) | |
| 367 | #define CONFIG_BIOSEMU | |
| 0f460a1e JJ |
368 | #define CONFIG_ATI_RADEON_FB |
| 369 | #define CONFIG_VIDEO_LOGO | |
| 46f3e385 | 370 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT |
| 0f460a1e JJ |
371 | #endif |
| 372 | ||
| debb7354 | 373 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| debb7354 | 374 | |
| dabf9ef8 JZ |
375 | #ifdef CONFIG_SCSI_AHCI |
| 376 | #define CONFIG_SATA_ULI5288 | |
| 6d0f6bcf JCPV |
377 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 378 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 379 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
| 380 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
| dabf9ef8 JZ |
381 | #endif |
| 382 | ||
| debb7354 JL |
383 | #endif /* CONFIG_PCI */ |
| 384 | ||
| debb7354 JL |
385 | #if defined(CONFIG_TSEC_ENET) |
| 386 | ||
| debb7354 JL |
387 | #define CONFIG_MII 1 /* MII PHY management */ |
| 388 | ||
| 53677ef1 WD |
389 | #define CONFIG_TSEC1 1 |
| 390 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 391 | #define CONFIG_TSEC2 1 | |
| 392 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 393 | #define CONFIG_TSEC3 1 | |
| 394 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 395 | #define CONFIG_TSEC4 1 | |
| 396 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| debb7354 | 397 | |
| debb7354 JL |
398 | #define TSEC1_PHY_ADDR 0 |
| 399 | #define TSEC2_PHY_ADDR 1 | |
| 400 | #define TSEC3_PHY_ADDR 2 | |
| 401 | #define TSEC4_PHY_ADDR 3 | |
| 402 | #define TSEC1_PHYIDX 0 | |
| 403 | #define TSEC2_PHYIDX 0 | |
| 404 | #define TSEC3_PHYIDX 0 | |
| 405 | #define TSEC4_PHYIDX 0 | |
| 3a79013e AF |
406 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 407 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 408 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 409 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| debb7354 JL |
410 | |
| 411 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 412 | ||
| 413 | #endif /* CONFIG_TSEC_ENET */ | |
| 414 | ||
| 1605cc9e | 415 | #ifdef CONFIG_PHYS_64BIT |
| 3111d32c BB |
416 | #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) |
| 417 | #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) | |
| 418 | ||
| 1605cc9e BB |
419 | /* Put physical address into the BAT format */ |
| 420 | #define BAT_PHYS_ADDR(low, high) \ | |
| 421 | (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) | |
| 422 | /* Convert high/low pairs to actual 64-bit value */ | |
| 423 | #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) | |
| 424 | #else | |
| 425 | /* 32-bit systems just ignore the "high" bits */ | |
| 426 | #define BAT_PHYS_ADDR(low, high) (low) | |
| 427 | #define PAIRED_PHYS_TO_PHYS(low, high) (low) | |
| 428 | #endif | |
| 429 | ||
| 586d1d5a | 430 | /* |
| c759a01a | 431 | * BAT0 DDR |
| debb7354 | 432 | */ |
| 6d0f6bcf | 433 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| 9ff32d8c | 434 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| debb7354 | 435 | |
| 586d1d5a | 436 | /* |
| c759a01a | 437 | * BAT1 LBC (PIXIS/CF) |
| af5d100e | 438 | */ |
| 1605cc9e BB |
439 | #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
| 440 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c BB |
441 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
| 442 | BATL_GUARDEDSTORAGE) | |
| c759a01a BB |
443 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ |
| 444 | | BATU_VS | BATU_VP) | |
| 1605cc9e BB |
445 | #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
| 446 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c | 447 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
| c759a01a | 448 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
| af5d100e BB |
449 | |
| 450 | /* if CONFIG_PCI: | |
| 46f3e385 | 451 | * BAT2 PCIE1 and PCIE1 MEM |
| af5d100e | 452 | * if CONFIG_RIO |
| c759a01a | 453 | * BAT2 Rapidio Memory |
| debb7354 | 454 | */ |
| af5d100e | 455 | #ifdef CONFIG_PCI |
| 842033e6 | 456 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 1605cc9e BB |
457 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
| 458 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
| 3111d32c BB |
459 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 460 | | BATL_GUARDEDSTORAGE) | |
| 46f3e385 | 461 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ |
| af5d100e | 462 | | BATU_VS | BATU_VP) |
| 1605cc9e BB |
463 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
| 464 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
| 3111d32c | 465 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| af5d100e BB |
466 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
| 467 | #else /* CONFIG_RIO */ | |
| 1605cc9e BB |
468 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
| 469 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
| 3111d32c BB |
470 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
| 471 | BATL_GUARDEDSTORAGE) | |
| 1b77ca8a | 472 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ |
| 3111d32c | 473 | | BATU_VS | BATU_VP) |
| 1605cc9e BB |
474 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
| 475 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
| 3111d32c | 476 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 6d0f6bcf | 477 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
| af5d100e | 478 | #endif |
| debb7354 | 479 | |
| 586d1d5a | 480 | /* |
| c759a01a | 481 | * BAT3 CCSR Space |
| debb7354 | 482 | */ |
| 1605cc9e BB |
483 | #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
| 484 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 3111d32c BB |
485 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 486 | | BATL_GUARDEDSTORAGE) | |
| c759a01a BB |
487 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ |
| 488 | | BATU_VP) | |
| 1605cc9e BB |
489 | #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
| 490 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 3111d32c | 491 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 6d0f6bcf | 492 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
| debb7354 | 493 | |
| 3111d32c BB |
494 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
| 495 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 496 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 497 | | BATL_GUARDEDSTORAGE) | |
| 498 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 499 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 500 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 501 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 502 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
| 503 | #endif | |
| 504 | ||
| 586d1d5a | 505 | /* |
| 46f3e385 | 506 | * BAT4 PCIE1_IO and PCIE2_IO |
| debb7354 | 507 | */ |
| 1605cc9e BB |
508 | #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
| 509 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c BB |
510 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 511 | | BATL_GUARDEDSTORAGE) | |
| 46f3e385 | 512 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ |
| c759a01a | 513 | | BATU_VS | BATU_VP) |
| 1605cc9e BB |
514 | #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
| 515 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c | 516 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 6d0f6bcf | 517 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
| debb7354 | 518 | |
| 586d1d5a | 519 | /* |
| c759a01a | 520 | * BAT5 Init RAM for stack in the CPU DCache (no backing memory) |
| debb7354 | 521 | */ |
| 6d0f6bcf JCPV |
522 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 523 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 524 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
| 525 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
| debb7354 | 526 | |
| 586d1d5a | 527 | /* |
| c759a01a | 528 | * BAT6 FLASH |
| debb7354 | 529 | */ |
| 1605cc9e BB |
530 | #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
| 531 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c BB |
532 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 533 | | BATL_GUARDEDSTORAGE) | |
| 170deacb BB |
534 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ |
| 535 | | BATU_VP) | |
| 1605cc9e BB |
536 | #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
| 537 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c | 538 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 6d0f6bcf | 539 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
| debb7354 | 540 | |
| bf9a8c34 BB |
541 | /* Map the last 1M of flash where we're running from reset */ |
| 542 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
| 543 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 14d0a02a | 544 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
| bf9a8c34 BB |
545 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
| 546 | | BATL_MEMCOHERENCE) | |
| 547 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
| 548 | ||
| c759a01a BB |
549 | /* |
| 550 | * BAT7 FREE - used later for tmp mappings | |
| 551 | */ | |
| 6d0f6bcf JCPV |
552 | #define CONFIG_SYS_DBAT7L 0x00000000 |
| 553 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
| 554 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
| 555 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
| debb7354 | 556 | |
| debb7354 JL |
557 | /* |
| 558 | * Environment | |
| 559 | */ | |
| 6d0f6bcf | 560 | #ifndef CONFIG_SYS_RAMBOOT |
| 221fbd22 SW |
561 | #define CONFIG_ENV_ADDR \ |
| 562 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
| 0e8d1586 | 563 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
| 5c9efb36 | 564 | #else |
| 6d0f6bcf | 565 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 5c9efb36 | 566 | #endif |
| 0f2d6602 | 567 | #define CONFIG_ENV_SIZE 0x2000 |
| debb7354 JL |
568 | |
| 569 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 570 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| debb7354 | 571 | |
| 659e2f67 JL |
572 | /* |
| 573 | * BOOTP options | |
| 574 | */ | |
| 575 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 659e2f67 | 576 | |
| debb7354 JL |
577 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 578 | ||
| 579 | /* | |
| 580 | * Miscellaneous configurable options | |
| 581 | */ | |
| 6d0f6bcf | 582 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| debb7354 | 583 | |
| debb7354 JL |
584 | /* |
| 585 | * For booting Linux, the board info and command line data | |
| 586 | * have to be in the first 8 MB of memory, since this is | |
| 587 | * the maximum mapped by the Linux kernel during initialization. | |
| 588 | */ | |
| e1efe43c SW |
589 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
| 590 | #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ | |
| debb7354 | 591 | |
| 2f9c19e4 JL |
592 | #if defined(CONFIG_CMD_KGDB) |
| 593 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| debb7354 JL |
594 | #endif |
| 595 | ||
| debb7354 JL |
596 | /* |
| 597 | * Environment Configuration | |
| 598 | */ | |
| 599 | ||
| 10327dc5 | 600 | #define CONFIG_HAS_ETH0 1 |
| 5c9efb36 JL |
601 | #define CONFIG_HAS_ETH1 1 |
| 602 | #define CONFIG_HAS_ETH2 1 | |
| 603 | #define CONFIG_HAS_ETH3 1 | |
| debb7354 | 604 | |
| 18b6c8cd | 605 | #define CONFIG_IPADDR 192.168.1.100 |
| debb7354 JL |
606 | |
| 607 | #define CONFIG_HOSTNAME unknown | |
| 8b3637c6 | 608 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| b3f44c21 | 609 | #define CONFIG_BOOTFILE "uImage" |
| 32922cdc | 610 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| debb7354 | 611 | |
| 5c9efb36 | 612 | #define CONFIG_SERVERIP 192.168.1.1 |
| 18b6c8cd | 613 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 5c9efb36 | 614 | #define CONFIG_NETMASK 255.255.255.0 |
| debb7354 | 615 | |
| 5c9efb36 | 616 | /* default location for tftp and bootm */ |
| e1efe43c | 617 | #define CONFIG_LOADADDR 0x10000000 |
| debb7354 | 618 | |
| 53677ef1 WD |
619 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 620 | "netdev=eth0\0" \ | |
| 5368c55d | 621 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 53677ef1 | 622 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 5368c55d MV |
623 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 624 | " +$filesize; " \ | |
| 625 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 626 | " +$filesize; " \ | |
| 627 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 628 | " $filesize; " \ | |
| 629 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 630 | " +$filesize; " \ | |
| 631 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 632 | " $filesize\0" \ | |
| 53677ef1 | 633 | "consoledev=ttyS0\0" \ |
| e1efe43c | 634 | "ramdiskaddr=0x18000000\0" \ |
| 53677ef1 | 635 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
| e1efe43c | 636 | "fdtaddr=0x17c00000\0" \ |
| 53677ef1 | 637 | "fdtfile=mpc8641_hpcn.dtb\0" \ |
| 3111d32c BB |
638 | "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ |
| 639 | "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ | |
| 53677ef1 WD |
640 | "maxcpus=2" |
| 641 | ||
| 53677ef1 WD |
642 | #define CONFIG_NFSBOOTCOMMAND \ |
| 643 | "setenv bootargs root=/dev/nfs rw " \ | |
| 644 | "nfsroot=$serverip:$rootpath " \ | |
| 645 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 646 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 647 | "tftp $loadaddr $bootfile;" \ | |
| 648 | "tftp $fdtaddr $fdtfile;" \ | |
| 649 | "bootm $loadaddr - $fdtaddr" | |
| 650 | ||
| 651 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 652 | "setenv bootargs root=/dev/ram rw " \ | |
| 653 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 654 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 655 | "tftp $loadaddr $bootfile;" \ | |
| 656 | "tftp $fdtaddr $fdtfile;" \ | |
| 657 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| debb7354 JL |
658 | |
| 659 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 660 | ||
| 661 | #endif /* __CONFIG_H */ |